Searched refs:current_sclk (Results 1 – 22 of 22) sorted by relevance
206 if (sclk < rdev->pm.current_sclk) in radeon_set_power_state()223 if (sclk != rdev->pm.current_sclk) { in radeon_set_power_state()227 rdev->pm.current_sclk = sclk; in radeon_set_power_state()1270 rdev->pm.current_sclk = rdev->pm.default_sclk; in radeon_pm_resume_old()1338 rdev->pm.current_sclk = rdev->clock.default_sclk; in radeon_pm_init_old()1404 rdev->pm.current_sclk = rdev->clock.default_sclk; in radeon_pm_init_dpm()1912 seq_printf(m, "current engine clock: %u0 kHz\n", rdev->pm.current_sclk); in radeon_debugfs_pm_info()
1405 u32 current_sclk; in trinity_patch_thermal_state() local1410 current_sclk = current_ps->levels[current_index].sclk; in trinity_patch_thermal_state()1413 current_sclk = pi->boot_pl.sclk; in trinity_patch_thermal_state()1418 if (ps->levels[0].sclk > current_sclk) in trinity_patch_thermal_state()1419 ps->levels[0].sclk = current_sclk; in trinity_patch_thermal_state()
1049 u32 current_sclk; in sumo_patch_thermal_state() local1054 current_sclk = current_ps->levels[current_index].sclk; in sumo_patch_thermal_state()1057 current_sclk = pi->boot_pl.sclk; in sumo_patch_thermal_state()1062 if (ps->levels[0].sclk > current_sclk) in sumo_patch_thermal_state()1063 ps->levels[0].sclk = current_sclk; in sumo_patch_thermal_state()
345 rdev->pm.current_sclk = rdev->clock.default_sclk; in radeon_get_clock_info()
573 *value = rdev->pm.current_sclk / 100; in radeon_info_ioctl()
241 u32 sclk = rdev->pm.current_sclk; in radeon_get_i2c_prescale()
294 selected_sclk = rdev->pm.current_sclk; in rs690_crtc_bandwidth_compute()
726 u32 sclk = rdev->pm.current_sclk; in radeon_update_bandwidth_info()
978 selected_sclk = rdev->pm.current_sclk; in rv515_crtc_bandwidth_compute()
2187 wm_high.sclk = rdev->pm.current_sclk * 10; in evergreen_program_watermarks()2214 wm_low.sclk = rdev->pm.current_sclk * 10; in evergreen_program_watermarks()
2336 wm_high.sclk = rdev->pm.current_sclk * 10; in dce6_program_watermarks()2363 wm_low.sclk = rdev->pm.current_sclk * 10; in dce6_program_watermarks()
1621 u32 current_sclk; member
9273 wm_high.sclk = rdev->pm.current_sclk * 10; in dce8_program_watermarks()9313 wm_low.sclk = rdev->pm.current_sclk * 10; in dce8_program_watermarks()
399 adev->pm.current_sclk = adev->clock.default_sclk; in amdgpu_atomfirmware_get_clock_info()
859 wm_high.sclk = adev->pm.current_sclk * 10; in dce_v6_0_program_watermarks()886 wm_low.sclk = adev->pm.current_sclk * 10; in dce_v6_0_program_watermarks()
987 wm_high.sclk = adev->pm.current_sclk * 10; in dce_v8_0_program_watermarks()1026 wm_low.sclk = adev->pm.current_sclk * 10; in dce_v8_0_program_watermarks()
1052 wm_high.sclk = adev->pm.current_sclk * 10; in dce_v10_0_program_watermarks()1091 wm_low.sclk = adev->pm.current_sclk * 10; in dce_v10_0_program_watermarks()
1078 wm_high.sclk = adev->pm.current_sclk * 10; in dce_v11_0_program_watermarks()1117 wm_low.sclk = adev->pm.current_sclk * 10; in dce_v11_0_program_watermarks()
702 adev->pm.current_sclk = adev->clock.default_sclk; in amdgpu_atombios_get_clock_info()
422 u32 current_sclk; member
3013 adev->pm.current_sclk = adev->clock.default_sclk; in kv_dpm_sw_init()
7705 adev->pm.current_sclk = adev->clock.default_sclk; in si_dpm_sw_init()
