| /Linux-v5.10/drivers/gpu/drm/i915/display/ |
| D | intel_color.c | 118 static bool crtc_state_is_legacy_gamma(const struct intel_crtc_state *crtc_state) in crtc_state_is_legacy_gamma() argument
120 return !crtc_state->hw.degamma_lut && in crtc_state_is_legacy_gamma()
121 !crtc_state->hw.ctm && in crtc_state_is_legacy_gamma()
122 crtc_state->hw.gamma_lut && in crtc_state_is_legacy_gamma()
123 lut_is_legacy(crtc_state->hw.gamma_lut); in crtc_state_is_legacy_gamma()
218 static bool ilk_csc_limited_range(const struct intel_crtc_state *crtc_state) in ilk_csc_limited_range() argument
220 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); in ilk_csc_limited_range()
226 return crtc_state->limited_color_range && in ilk_csc_limited_range()
231 static void ilk_csc_convert_ctm(const struct intel_crtc_state *crtc_state, in ilk_csc_convert_ctm() argument
234 const struct drm_color_ctm *ctm = crtc_state->hw.ctm->data; in ilk_csc_convert_ctm()
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| D | intel_atomic.c | 133 struct drm_crtc_state *crtc_state; in intel_digital_connector_atomic_check() local
141 crtc_state = drm_atomic_get_new_crtc_state(state, new_state->crtc); in intel_digital_connector_atomic_check()
155 crtc_state->mode_changed = true; in intel_digital_connector_atomic_check()
229 struct intel_crtc_state *crtc_state; in intel_crtc_duplicate_state() local
231 crtc_state = kmemdup(old_crtc_state, sizeof(*crtc_state), GFP_KERNEL); in intel_crtc_duplicate_state()
232 if (!crtc_state) in intel_crtc_duplicate_state()
235 __drm_atomic_helper_crtc_duplicate_state(crtc, &crtc_state->uapi); in intel_crtc_duplicate_state()
238 if (crtc_state->hw.degamma_lut) in intel_crtc_duplicate_state()
239 drm_property_blob_get(crtc_state->hw.degamma_lut); in intel_crtc_duplicate_state()
240 if (crtc_state->hw.ctm) in intel_crtc_duplicate_state()
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| D | intel_vdsc.c | 336 const struct intel_crtc_state *crtc_state) in intel_dsc_source_support() argument
338 const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_dsc_source_support()
340 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; in intel_dsc_source_support()
360 static bool is_pipe_dsc(const struct intel_crtc_state *crtc_state) in is_pipe_dsc() argument
362 const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in is_pipe_dsc()
364 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; in is_pipe_dsc()
468 intel_dsc_power_domain(const struct intel_crtc_state *crtc_state) in intel_dsc_power_domain() argument
470 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_dsc_power_domain()
487 else if (is_pipe_dsc(crtc_state)) in intel_dsc_power_domain()
494 const struct intel_crtc_state *crtc_state) in intel_dsc_pps_configure() argument
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| D | intel_hdmi.c | 213 const struct intel_crtc_state *crtc_state, in g4x_write_infoframe() argument
249 const struct intel_crtc_state *crtc_state, in g4x_read_infoframe() argument
285 const struct intel_crtc_state *crtc_state, in ibx_write_infoframe() argument
291 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc); in ibx_write_infoframe()
324 const struct intel_crtc_state *crtc_state, in ibx_read_infoframe() argument
329 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in ibx_read_infoframe()
364 const struct intel_crtc_state *crtc_state, in cpt_write_infoframe() argument
370 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc); in cpt_write_infoframe()
406 const struct intel_crtc_state *crtc_state, in cpt_read_infoframe() argument
411 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in cpt_read_infoframe()
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| D | intel_ddi.c | 1224 const struct intel_crtc_state *crtc_state) in intel_prepare_dp_ddi_buffers() argument
1232 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) in intel_prepare_dp_ddi_buffers()
1235 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) in intel_prepare_dp_ddi_buffers()
1337 const struct intel_crtc_state *crtc_state) in icl_pll_to_ddi_clk_sel() argument
1339 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; in icl_pll_to_ddi_clk_sel()
1340 int clock = crtc_state->port_clock; in icl_pll_to_ddi_clk_sel()
1385 const struct intel_crtc_state *crtc_state) in hsw_fdi_link_train() argument
1387 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in hsw_fdi_link_train()
1391 intel_prepare_dp_ddi_buffers(encoder, crtc_state); in hsw_fdi_link_train()
1406 FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes); in hsw_fdi_link_train()
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| D | intel_ddi.h | 26 const struct intel_crtc_state *crtc_state);
30 const struct intel_crtc_state *crtc_state);
31 void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state);
33 const struct intel_crtc_state *crtc_state);
34 void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state);
35 void intel_ddi_set_dp_msa(const struct intel_crtc_state *crtc_state,
40 void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state,
43 struct intel_crtc_state *crtc_state);
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| D | intel_dp.h | 36 bool intel_dp_limited_color_range(const struct intel_crtc_state *crtc_state,
38 int intel_dp_min_bpp(const struct intel_crtc_state *crtc_state);
56 const struct intel_crtc_state *crtc_state,
68 void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
83 const struct intel_crtc_state *crtc_state);
85 const struct intel_crtc_state *crtc_state);
87 const struct intel_crtc_state *crtc_state);
109 bool intel_dp_needs_vsc_sdp(const struct intel_crtc_state *crtc_state,
112 const struct intel_crtc_state *crtc_state,
116 const struct intel_crtc_state *crtc_state,
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| D | intel_dsb.c | 92 void intel_dsb_indexed_reg_write(const struct intel_crtc_state *crtc_state, in intel_dsb_indexed_reg_write() argument
95 struct intel_dsb *dsb = crtc_state->dsb; in intel_dsb_indexed_reg_write()
96 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_dsb_indexed_reg_write()
169 void intel_dsb_reg_write(const struct intel_crtc_state *crtc_state, in intel_dsb_reg_write() argument
172 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_dsb_reg_write()
177 dsb = crtc_state->dsb; in intel_dsb_reg_write()
203 void intel_dsb_commit(const struct intel_crtc_state *crtc_state) in intel_dsb_commit() argument
205 struct intel_dsb *dsb = crtc_state->dsb; in intel_dsb_commit()
206 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_dsb_commit()
260 void intel_dsb_prepare(struct intel_crtc_state *crtc_state) in intel_dsb_prepare() argument
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| D | intel_display.c | 157 static void intel_set_pipe_timings(const struct intel_crtc_state *crtc_state);
158 static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state);
159 static void intel_cpu_transcoder_set_m_n(const struct intel_crtc_state *crtc_state,
162 static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state);
163 static void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state);
164 static void hsw_set_pipeconf(const struct intel_crtc_state *crtc_state);
165 static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state);
170 static void skl_pfit_enable(const struct intel_crtc_state *crtc_state);
171 static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state);
551 is_trans_port_sync_slave(const struct intel_crtc_state *crtc_state) in is_trans_port_sync_slave() argument
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| D | intel_audio.c | 125 audio_config_dp_get_n_m(const struct intel_crtc_state *crtc_state, int rate) in audio_config_dp_get_n_m() argument
131 crtc_state->port_clock == dp_aud_n_m[i].clock) in audio_config_dp_get_n_m()
239 static u32 audio_config_hdmi_pixel_clock(const struct intel_crtc_state *crtc_state) in audio_config_hdmi_pixel_clock() argument
241 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); in audio_config_hdmi_pixel_clock()
243 &crtc_state->hw.adjusted_mode; in audio_config_hdmi_pixel_clock()
269 static int audio_config_hdmi_get_n(const struct intel_crtc_state *crtc_state, in audio_config_hdmi_get_n() argument
275 if (crtc_state->pipe_bpp == 36) { in audio_config_hdmi_get_n()
278 } else if (crtc_state->pipe_bpp == 30) { in audio_config_hdmi_get_n()
288 crtc_state->port_clock == hdmi_ncts_table[i].clock) { in audio_config_hdmi_get_n()
344 const struct intel_crtc_state *crtc_state, in g4x_audio_codec_enable() argument
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| D | intel_psr.c | 95 const struct intel_crtc_state *crtc_state) in intel_psr2_enabled() argument
98 drm_WARN_ON(&dev_priv->drm, crtc_state->dsc.compression_enable && in intel_psr2_enabled()
99 crtc_state->has_psr2); in intel_psr2_enabled()
106 return crtc_state->has_psr2; in intel_psr2_enabled()
654 struct intel_crtc_state *crtc_state) in tgl_dc3co_exitline_compute_config() argument
656 const u32 crtc_vdisplay = crtc_state->uapi.adjusted_mode.crtc_vdisplay; in tgl_dc3co_exitline_compute_config()
665 if (to_intel_crtc(crtc_state->uapi.crtc)->pipe != PIPE_A || in tgl_dc3co_exitline_compute_config()
674 intel_usecs_to_scanlines(&crtc_state->uapi.adjusted_mode, 200) + 1; in tgl_dc3co_exitline_compute_config()
679 crtc_state->dc3co_exitline = crtc_vdisplay - exit_scanlines; in tgl_dc3co_exitline_compute_config()
683 struct intel_crtc_state *crtc_state) in intel_psr2_sel_fetch_config_valid() argument
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| D | intel_atomic_plane.h | 21 unsigned int intel_plane_pixel_rate(const struct intel_crtc_state *crtc_state,
24 unsigned int intel_plane_data_rate(const struct intel_crtc_state *crtc_state,
29 const struct intel_crtc_state *crtc_state,
32 const struct intel_crtc_state *crtc_state);
43 struct intel_crtc_state *crtc_state,
49 struct intel_crtc_state *crtc_state,
55 void intel_plane_set_invisible(struct intel_crtc_state *crtc_state,
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| D | intel_atomic_plane.c | 136 unsigned int intel_plane_pixel_rate(const struct intel_crtc_state *crtc_state, in intel_plane_pixel_rate() argument
140 unsigned int pixel_rate = crtc_state->pixel_rate; in intel_plane_pixel_rate()
155 unsigned int intel_plane_data_rate(const struct intel_crtc_state *crtc_state, in intel_plane_data_rate() argument
165 pixel_rate = intel_plane_pixel_rate(crtc_state, plane_state); in intel_plane_data_rate()
267 void intel_plane_set_invisible(struct intel_crtc_state *crtc_state, in intel_plane_set_invisible() argument
272 crtc_state->active_planes &= ~BIT(plane->id); in intel_plane_set_invisible()
273 crtc_state->nv12_planes &= ~BIT(plane->id); in intel_plane_set_invisible()
274 crtc_state->c8_planes &= ~BIT(plane->id); in intel_plane_set_invisible()
275 crtc_state->data_rate[plane->id] = 0; in intel_plane_set_invisible()
276 crtc_state->min_cdclk[plane->id] = 0; in intel_plane_set_invisible()
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| D | intel_dp_mst.c | 43 struct intel_crtc_state *crtc_state, in intel_dp_mst_compute_link_config() argument
47 struct drm_atomic_state *state = crtc_state->uapi.state; in intel_dp_mst_compute_link_config()
54 &crtc_state->hw.adjusted_mode; in intel_dp_mst_compute_link_config()
59 crtc_state->lane_count = limits->max_lane_count; in intel_dp_mst_compute_link_config()
60 crtc_state->port_clock = limits->max_clock; in intel_dp_mst_compute_link_config()
63 crtc_state->pipe_bpp = bpp; in intel_dp_mst_compute_link_config()
65 crtc_state->pbn = drm_dp_calc_pbn_mode(adjusted_mode->crtc_clock, in intel_dp_mst_compute_link_config()
66 crtc_state->pipe_bpp, in intel_dp_mst_compute_link_config()
71 crtc_state->pbn, 0); in intel_dp_mst_compute_link_config()
84 intel_link_compute_m_n(crtc_state->pipe_bpp, in intel_dp_mst_compute_link_config()
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| D | intel_vdsc.h | 15 const struct intel_crtc_state *crtc_state);
17 const struct intel_crtc_state *crtc_state);
18 void intel_dsc_disable(const struct intel_crtc_state *crtc_state);
22 struct intel_crtc_state *crtc_state);
24 intel_dsc_power_domain(const struct intel_crtc_state *crtc_state);
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| D | intel_color.h | 16 int intel_color_check(struct intel_crtc_state *crtc_state);
17 void intel_color_commit(const struct intel_crtc_state *crtc_state);
18 void intel_color_load_luts(const struct intel_crtc_state *crtc_state);
19 void intel_color_get_config(struct intel_crtc_state *crtc_state);
20 int intel_color_get_gamma_bit_precision(const struct intel_crtc_state *crtc_state);
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| D | intel_dpll_mgr.c | 169 void intel_prepare_shared_dpll(const struct intel_crtc_state *crtc_state) in intel_prepare_shared_dpll() argument
171 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_prepare_shared_dpll()
173 struct intel_shared_dpll *pll = crtc_state->shared_dpll; in intel_prepare_shared_dpll()
196 void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state) in intel_enable_shared_dpll() argument
198 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_enable_shared_dpll()
200 struct intel_shared_dpll *pll = crtc_state->shared_dpll; in intel_enable_shared_dpll()
242 void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state) in intel_disable_shared_dpll() argument
244 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_disable_shared_dpll()
246 struct intel_shared_dpll *pll = crtc_state->shared_dpll; in intel_disable_shared_dpll()
487 struct intel_crtc_state *crtc_state = in ibx_get_dpll() local
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| D | intel_dsb.h | 43 void intel_dsb_prepare(struct intel_crtc_state *crtc_state);
44 void intel_dsb_cleanup(struct intel_crtc_state *crtc_state);
45 void intel_dsb_reg_write(const struct intel_crtc_state *crtc_state,
47 void intel_dsb_indexed_reg_write(const struct intel_crtc_state *crtc_state,
49 void intel_dsb_commit(const struct intel_crtc_state *crtc_state);
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| /Linux-v5.10/drivers/gpu/drm/gma500/ |
| D | gma_display.c | 501 kfree(gma_crtc->crtc_state); in gma_crtc_destroy()
577 struct psb_intel_crtc_state *crtc_state = gma_crtc->crtc_state; in gma_crtc_save() local
582 if (!crtc_state) { in gma_crtc_save()
587 crtc_state->saveDSPCNTR = REG_READ(map->cntr); in gma_crtc_save()
588 crtc_state->savePIPECONF = REG_READ(map->conf); in gma_crtc_save()
589 crtc_state->savePIPESRC = REG_READ(map->src); in gma_crtc_save()
590 crtc_state->saveFP0 = REG_READ(map->fp0); in gma_crtc_save()
591 crtc_state->saveFP1 = REG_READ(map->fp1); in gma_crtc_save()
592 crtc_state->saveDPLL = REG_READ(map->dpll); in gma_crtc_save()
593 crtc_state->saveHTOTAL = REG_READ(map->htotal); in gma_crtc_save()
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| /Linux-v5.10/drivers/gpu/drm/amd/display/amdgpu_dm/ |
| D | amdgpu_dm_crc.c | 146 struct dm_crtc_state *crtc_state; in amdgpu_dm_crtc_set_crc_source() local
184 crtc_state = to_dm_crtc_state(crtc->state); in amdgpu_dm_crtc_set_crc_source()
201 dm_is_crc_source_dprx(crtc_state->crc_src))) { in amdgpu_dm_crtc_set_crc_source()
231 if (amdgpu_dm_crtc_configure_crc_source(crtc, crtc_state, source)) { in amdgpu_dm_crtc_set_crc_source()
240 enabled = amdgpu_dm_is_valid_crc_source(crtc_state->crc_src); in amdgpu_dm_crtc_set_crc_source()
264 crtc_state->crc_src = source; in amdgpu_dm_crtc_set_crc_source()
267 crtc_state->crc_skip_count = 0; in amdgpu_dm_crtc_set_crc_source()
287 struct dm_crtc_state *crtc_state; in amdgpu_dm_crtc_handle_crc_irq() local
294 crtc_state = to_dm_crtc_state(crtc->state); in amdgpu_dm_crtc_handle_crc_irq()
295 stream_state = crtc_state->stream; in amdgpu_dm_crtc_handle_crc_irq()
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| /Linux-v5.10/drivers/gpu/drm/i915/ |
| D | intel_pm.c | 485 static void vlv_get_fifo_size(struct intel_crtc_state *crtc_state) in vlv_get_fifo_size() argument
487 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in vlv_get_fifo_size()
489 struct vlv_fifo_state *fifo_state = &crtc_state->wm.vlv.fifo_state; in vlv_get_fifo_size()
824 static bool intel_wm_plane_visible(const struct intel_crtc_state *crtc_state, in intel_wm_plane_visible() argument
830 if (!crtc_state->hw.active) in intel_wm_plane_visible()
1132 static u16 g4x_compute_wm(const struct intel_crtc_state *crtc_state, in g4x_compute_wm() argument
1139 &crtc_state->hw.adjusted_mode; in g4x_compute_wm()
1146 if (!intel_wm_plane_visible(crtc_state, plane_state)) in g4x_compute_wm()
1193 static bool g4x_raw_plane_wm_set(struct intel_crtc_state *crtc_state, in g4x_raw_plane_wm_set() argument
1196 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); in g4x_raw_plane_wm_set()
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| /Linux-v5.10/drivers/gpu/drm/ |
| D | drm_self_refresh_helper.c | 78 struct drm_crtc_state *crtc_state; in drm_self_refresh_helper_entry_work() local
92 crtc_state = drm_atomic_get_crtc_state(state, crtc); in drm_self_refresh_helper_entry_work()
93 if (IS_ERR(crtc_state)) { in drm_self_refresh_helper_entry_work()
94 ret = PTR_ERR(crtc_state); in drm_self_refresh_helper_entry_work()
98 if (!crtc_state->enable) in drm_self_refresh_helper_entry_work()
110 crtc_state->active = false; in drm_self_refresh_helper_entry_work()
111 crtc_state->self_refresh_active = true; in drm_self_refresh_helper_entry_work()
190 struct drm_crtc_state *crtc_state; in drm_self_refresh_helper_alter_state() local
194 for_each_old_crtc_in_state(state, crtc, crtc_state, i) { in drm_self_refresh_helper_alter_state()
195 if (crtc_state->self_refresh_active) { in drm_self_refresh_helper_alter_state()
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| /Linux-v5.10/drivers/gpu/drm/tilcdc/ |
| D | tilcdc_plane.c | 26 struct drm_crtc_state *crtc_state; in tilcdc_plane_atomic_check() local
42 crtc_state = drm_atomic_get_existing_crtc_state(state->state, in tilcdc_plane_atomic_check()
45 if (WARN_ON(!crtc_state)) in tilcdc_plane_atomic_check()
48 if (crtc_state->mode.hdisplay != state->crtc_w || in tilcdc_plane_atomic_check()
49 crtc_state->mode.vdisplay != state->crtc_h) { in tilcdc_plane_atomic_check()
52 crtc_state->mode.hdisplay, crtc_state->mode.vdisplay, in tilcdc_plane_atomic_check()
57 pitch = crtc_state->mode.hdisplay * in tilcdc_plane_atomic_check()
69 crtc_state->mode_changed = true; in tilcdc_plane_atomic_check()
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| /Linux-v5.10/drivers/gpu/drm/selftests/ |
| D | test-drm_plane_helper.c | 80 const struct drm_crtc_state crtc_state = { in igt_check_plane_state() local
103 ret = drm_atomic_helper_check_plane_state(&plane_state, &crtc_state, in igt_check_plane_state()
114 ret = drm_atomic_helper_check_plane_state(&plane_state, &crtc_state, in igt_check_plane_state()
127 ret = drm_atomic_helper_check_plane_state(&plane_state, &crtc_state, in igt_check_plane_state()
133 ret = drm_atomic_helper_check_plane_state(&plane_state, &crtc_state, in igt_check_plane_state()
145 ret = drm_atomic_helper_check_plane_state(&plane_state, &crtc_state, in igt_check_plane_state()
150 ret = drm_atomic_helper_check_plane_state(&plane_state, &crtc_state, in igt_check_plane_state()
160 ret = drm_atomic_helper_check_plane_state(&plane_state, &crtc_state, in igt_check_plane_state()
164 ret = drm_atomic_helper_check_plane_state(&plane_state, &crtc_state, in igt_check_plane_state()
175 ret = drm_atomic_helper_check_plane_state(&plane_state, &crtc_state, in igt_check_plane_state()
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| /Linux-v5.10/drivers/gpu/drm/vkms/ |
| D | vkms_composer.c | 182 struct vkms_crtc_state *crtc_state = container_of(work, in vkms_composer_worker() local
185 struct drm_crtc *crtc = crtc_state->base.crtc; in vkms_composer_worker()
196 frame_start = crtc_state->frame_start; in vkms_composer_worker()
197 frame_end = crtc_state->frame_end; in vkms_composer_worker()
198 crc_pending = crtc_state->crc_pending; in vkms_composer_worker()
199 wb_pending = crtc_state->wb_pending; in vkms_composer_worker()
200 crtc_state->frame_start = 0; in vkms_composer_worker()
201 crtc_state->frame_end = 0; in vkms_composer_worker()
202 crtc_state->crc_pending = false; in vkms_composer_worker()
212 if (crtc_state->num_active_planes >= 1) in vkms_composer_worker()
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