1 /* SPDX-License-Identifier: GPL-2.0 2 * 3 * Copyright 2020 HabanaLabs, Ltd. 4 * All Rights Reserved. 5 * 6 */ 7 8 #ifndef CPUCP_IF_H 9 #define CPUCP_IF_H 10 11 #include <linux/types.h> 12 13 /* 14 * EVENT QUEUE 15 */ 16 17 struct hl_eq_header { 18 __le32 reserved; 19 __le32 ctl; 20 }; 21 22 struct hl_eq_ecc_data { 23 __le64 ecc_address; 24 __le64 ecc_syndrom; 25 __u8 memory_wrapper_idx; 26 __u8 pad[7]; 27 }; 28 29 struct hl_eq_entry { 30 struct hl_eq_header hdr; 31 union { 32 struct hl_eq_ecc_data ecc_data; 33 __le64 data[7]; 34 }; 35 }; 36 37 #define HL_EQ_ENTRY_SIZE sizeof(struct hl_eq_entry) 38 39 #define EQ_CTL_READY_SHIFT 31 40 #define EQ_CTL_READY_MASK 0x80000000 41 42 #define EQ_CTL_EVENT_TYPE_SHIFT 16 43 #define EQ_CTL_EVENT_TYPE_MASK 0x03FF0000 44 45 enum pq_init_status { 46 PQ_INIT_STATUS_NA = 0, 47 PQ_INIT_STATUS_READY_FOR_CP, 48 PQ_INIT_STATUS_READY_FOR_HOST, 49 PQ_INIT_STATUS_READY_FOR_CP_SINGLE_MSI 50 }; 51 52 /* 53 * CpuCP Primary Queue Packets 54 * 55 * During normal operation, the host's kernel driver needs to send various 56 * messages to CpuCP, usually either to SET some value into a H/W periphery or 57 * to GET the current value of some H/W periphery. For example, SET the 58 * frequency of MME/TPC and GET the value of the thermal sensor. 59 * 60 * These messages can be initiated either by the User application or by the 61 * host's driver itself, e.g. power management code. In either case, the 62 * communication from the host's driver to CpuCP will *always* be in 63 * synchronous mode, meaning that the host will send a single message and poll 64 * until the message was acknowledged and the results are ready (if results are 65 * needed). 66 * 67 * This means that only a single message can be sent at a time and the host's 68 * driver must wait for its result before sending the next message. Having said 69 * that, because these are control messages which are sent in a relatively low 70 * frequency, this limitation seems acceptable. It's important to note that 71 * in case of multiple devices, messages to different devices *can* be sent 72 * at the same time. 73 * 74 * The message, inputs/outputs (if relevant) and fence object will be located 75 * on the device DDR at an address that will be determined by the host's driver. 76 * During device initialization phase, the host will pass to CpuCP that address. 77 * Most of the message types will contain inputs/outputs inside the message 78 * itself. The common part of each message will contain the opcode of the 79 * message (its type) and a field representing a fence object. 80 * 81 * When the host's driver wishes to send a message to CPU CP, it will write the 82 * message contents to the device DDR, clear the fence object and then write to 83 * the PSOC_ARC1_AUX_SW_INTR, to issue interrupt 121 to ARC Management CPU. 84 * 85 * Upon receiving the interrupt (#121), CpuCP will read the message from the 86 * DDR. In case the message is a SET operation, CpuCP will first perform the 87 * operation and then write to the fence object on the device DDR. In case the 88 * message is a GET operation, CpuCP will first fill the results section on the 89 * device DDR and then write to the fence object. If an error occurred, CpuCP 90 * will fill the rc field with the right error code. 91 * 92 * In the meantime, the host's driver will poll on the fence object. Once the 93 * host sees that the fence object is signaled, it will read the results from 94 * the device DDR (if relevant) and resume the code execution in the host's 95 * driver. 96 * 97 * To use QMAN packets, the opcode must be the QMAN opcode, shifted by 8 98 * so the value being put by the host's driver matches the value read by CpuCP 99 * 100 * Non-QMAN packets should be limited to values 1 through (2^8 - 1) 101 * 102 * Detailed description: 103 * 104 * CPUCP_PACKET_DISABLE_PCI_ACCESS - 105 * After receiving this packet the embedded CPU must NOT issue PCI 106 * transactions (read/write) towards the Host CPU. This also include 107 * sending MSI-X interrupts. 108 * This packet is usually sent before the device is moved to D3Hot state. 109 * 110 * CPUCP_PACKET_ENABLE_PCI_ACCESS - 111 * After receiving this packet the embedded CPU is allowed to issue PCI 112 * transactions towards the Host CPU, including sending MSI-X interrupts. 113 * This packet is usually send after the device is moved to D0 state. 114 * 115 * CPUCP_PACKET_TEMPERATURE_GET - 116 * Fetch the current temperature / Max / Max Hyst / Critical / 117 * Critical Hyst of a specified thermal sensor. The packet's 118 * arguments specify the desired sensor and the field to get. 119 * 120 * CPUCP_PACKET_VOLTAGE_GET - 121 * Fetch the voltage / Max / Min of a specified sensor. The packet's 122 * arguments specify the sensor and type. 123 * 124 * CPUCP_PACKET_CURRENT_GET - 125 * Fetch the current / Max / Min of a specified sensor. The packet's 126 * arguments specify the sensor and type. 127 * 128 * CPUCP_PACKET_FAN_SPEED_GET - 129 * Fetch the speed / Max / Min of a specified fan. The packet's 130 * arguments specify the sensor and type. 131 * 132 * CPUCP_PACKET_PWM_GET - 133 * Fetch the pwm value / mode of a specified pwm. The packet's 134 * arguments specify the sensor and type. 135 * 136 * CPUCP_PACKET_PWM_SET - 137 * Set the pwm value / mode of a specified pwm. The packet's 138 * arguments specify the sensor, type and value. 139 * 140 * CPUCP_PACKET_FREQUENCY_SET - 141 * Set the frequency of a specified PLL. The packet's arguments specify 142 * the PLL and the desired frequency. The actual frequency in the device 143 * might differ from the requested frequency. 144 * 145 * CPUCP_PACKET_FREQUENCY_GET - 146 * Fetch the frequency of a specified PLL. The packet's arguments specify 147 * the PLL. 148 * 149 * CPUCP_PACKET_LED_SET - 150 * Set the state of a specified led. The packet's arguments 151 * specify the led and the desired state. 152 * 153 * CPUCP_PACKET_I2C_WR - 154 * Write 32-bit value to I2C device. The packet's arguments specify the 155 * I2C bus, address and value. 156 * 157 * CPUCP_PACKET_I2C_RD - 158 * Read 32-bit value from I2C device. The packet's arguments specify the 159 * I2C bus and address. 160 * 161 * CPUCP_PACKET_INFO_GET - 162 * Fetch information from the device as specified in the packet's 163 * structure. The host's driver passes the max size it allows the CpuCP to 164 * write to the structure, to prevent data corruption in case of 165 * mismatched driver/FW versions. 166 * 167 * CPUCP_PACKET_FLASH_PROGRAM_REMOVED - this packet was removed 168 * 169 * CPUCP_PACKET_UNMASK_RAZWI_IRQ - 170 * Unmask the given IRQ. The IRQ number is specified in the value field. 171 * The packet is sent after receiving an interrupt and printing its 172 * relevant information. 173 * 174 * CPUCP_PACKET_UNMASK_RAZWI_IRQ_ARRAY - 175 * Unmask the given IRQs. The IRQs numbers are specified in an array right 176 * after the cpucp_packet structure, where its first element is the array 177 * length. The packet is sent after a soft reset was done in order to 178 * handle any interrupts that were sent during the reset process. 179 * 180 * CPUCP_PACKET_TEST - 181 * Test packet for CpuCP connectivity. The CPU will put the fence value 182 * in the result field. 183 * 184 * CPUCP_PACKET_FREQUENCY_CURR_GET - 185 * Fetch the current frequency of a specified PLL. The packet's arguments 186 * specify the PLL. 187 * 188 * CPUCP_PACKET_MAX_POWER_GET - 189 * Fetch the maximal power of the device. 190 * 191 * CPUCP_PACKET_MAX_POWER_SET - 192 * Set the maximal power of the device. The packet's arguments specify 193 * the power. 194 * 195 * CPUCP_PACKET_EEPROM_DATA_GET - 196 * Get EEPROM data from the CpuCP kernel. The buffer is specified in the 197 * addr field. The CPU will put the returned data size in the result 198 * field. In addition, the host's driver passes the max size it allows the 199 * CpuCP to write to the structure, to prevent data corruption in case of 200 * mismatched driver/FW versions. 201 * 202 * CPUCP_PACKET_TEMPERATURE_SET - 203 * Set the value of the offset property of a specified thermal sensor. 204 * The packet's arguments specify the desired sensor and the field to 205 * set. 206 * 207 * CPUCP_PACKET_VOLTAGE_SET - 208 * Trigger the reset_history property of a specified voltage sensor. 209 * The packet's arguments specify the desired sensor and the field to 210 * set. 211 * 212 * CPUCP_PACKET_CURRENT_SET - 213 * Trigger the reset_history property of a specified current sensor. 214 * The packet's arguments specify the desired sensor and the field to 215 * set. 216 * 217 * CPUCP_PACKET_PLL_REG_GET 218 * Fetch register of PLL from the required PLL IP. 219 * The packet's arguments specify the PLL IP and the register to get. 220 * Each register is 32-bit value which is returned in result field. 221 * 222 */ 223 224 enum cpucp_packet_id { 225 CPUCP_PACKET_DISABLE_PCI_ACCESS = 1, /* internal */ 226 CPUCP_PACKET_ENABLE_PCI_ACCESS, /* internal */ 227 CPUCP_PACKET_TEMPERATURE_GET, /* sysfs */ 228 CPUCP_PACKET_VOLTAGE_GET, /* sysfs */ 229 CPUCP_PACKET_CURRENT_GET, /* sysfs */ 230 CPUCP_PACKET_FAN_SPEED_GET, /* sysfs */ 231 CPUCP_PACKET_PWM_GET, /* sysfs */ 232 CPUCP_PACKET_PWM_SET, /* sysfs */ 233 CPUCP_PACKET_FREQUENCY_SET, /* sysfs */ 234 CPUCP_PACKET_FREQUENCY_GET, /* sysfs */ 235 CPUCP_PACKET_LED_SET, /* debugfs */ 236 CPUCP_PACKET_I2C_WR, /* debugfs */ 237 CPUCP_PACKET_I2C_RD, /* debugfs */ 238 CPUCP_PACKET_INFO_GET, /* IOCTL */ 239 CPUCP_PACKET_FLASH_PROGRAM_REMOVED, 240 CPUCP_PACKET_UNMASK_RAZWI_IRQ, /* internal */ 241 CPUCP_PACKET_UNMASK_RAZWI_IRQ_ARRAY, /* internal */ 242 CPUCP_PACKET_TEST, /* internal */ 243 CPUCP_PACKET_FREQUENCY_CURR_GET, /* sysfs */ 244 CPUCP_PACKET_MAX_POWER_GET, /* sysfs */ 245 CPUCP_PACKET_MAX_POWER_SET, /* sysfs */ 246 CPUCP_PACKET_EEPROM_DATA_GET, /* sysfs */ 247 CPUCP_RESERVED, 248 CPUCP_PACKET_TEMPERATURE_SET, /* sysfs */ 249 CPUCP_PACKET_VOLTAGE_SET, /* sysfs */ 250 CPUCP_PACKET_CURRENT_SET, /* sysfs */ 251 CPUCP_PACKET_PCIE_THROUGHPUT_GET, /* internal */ 252 CPUCP_PACKET_PCIE_REPLAY_CNT_GET, /* internal */ 253 CPUCP_PACKET_TOTAL_ENERGY_GET, /* internal */ 254 CPUCP_PACKET_PLL_REG_GET, /* internal */ 255 }; 256 257 #define CPUCP_PACKET_FENCE_VAL 0xFE8CE7A5 258 259 #define CPUCP_PKT_CTL_RC_SHIFT 12 260 #define CPUCP_PKT_CTL_RC_MASK 0x0000F000 261 262 #define CPUCP_PKT_CTL_OPCODE_SHIFT 16 263 #define CPUCP_PKT_CTL_OPCODE_MASK 0x1FFF0000 264 265 struct cpucp_packet { 266 union { 267 __le64 value; /* For SET packets */ 268 __le64 result; /* For GET packets */ 269 __le64 addr; /* For PQ */ 270 }; 271 272 __le32 ctl; 273 274 __le32 fence; /* Signal to host that message is completed */ 275 276 union { 277 struct {/* For temperature/current/voltage/fan/pwm get/set */ 278 __le16 sensor_index; 279 __le16 type; 280 }; 281 282 struct { /* For I2C read/write */ 283 __u8 i2c_bus; 284 __u8 i2c_addr; 285 __u8 i2c_reg; 286 __u8 pad; /* unused */ 287 }; 288 289 struct {/* For PLL register fetch */ 290 __le16 pll_type; 291 __le16 pll_reg; 292 }; 293 294 /* For any general request */ 295 __le32 index; 296 297 /* For frequency get/set */ 298 __le32 pll_index; 299 300 /* For led set */ 301 __le32 led_index; 302 303 /* For get CpuCP info/EEPROM data */ 304 __le32 data_max_size; 305 }; 306 307 __le32 reserved; 308 }; 309 310 struct cpucp_unmask_irq_arr_packet { 311 struct cpucp_packet cpucp_pkt; 312 __le32 length; 313 __le32 irqs[0]; 314 }; 315 316 enum cpucp_packet_rc { 317 cpucp_packet_success, 318 cpucp_packet_invalid, 319 cpucp_packet_fault 320 }; 321 322 /* 323 * cpucp_temp_type should adhere to hwmon_temp_attributes 324 * defined in Linux kernel hwmon.h file 325 */ 326 enum cpucp_temp_type { 327 cpucp_temp_input, 328 cpucp_temp_max = 6, 329 cpucp_temp_max_hyst, 330 cpucp_temp_crit, 331 cpucp_temp_crit_hyst, 332 cpucp_temp_offset = 19, 333 cpucp_temp_highest = 22, 334 cpucp_temp_reset_history = 23 335 }; 336 337 enum cpucp_in_attributes { 338 cpucp_in_input, 339 cpucp_in_min, 340 cpucp_in_max, 341 cpucp_in_highest = 7, 342 cpucp_in_reset_history 343 }; 344 345 enum cpucp_curr_attributes { 346 cpucp_curr_input, 347 cpucp_curr_min, 348 cpucp_curr_max, 349 cpucp_curr_highest = 7, 350 cpucp_curr_reset_history 351 }; 352 353 enum cpucp_fan_attributes { 354 cpucp_fan_input, 355 cpucp_fan_min = 2, 356 cpucp_fan_max 357 }; 358 359 enum cpucp_pwm_attributes { 360 cpucp_pwm_input, 361 cpucp_pwm_enable 362 }; 363 364 enum cpucp_pcie_throughput_attributes { 365 cpucp_pcie_throughput_tx, 366 cpucp_pcie_throughput_rx 367 }; 368 369 enum cpucp_pll_reg_attributes { 370 cpucp_pll_nr_reg, 371 cpucp_pll_nf_reg, 372 cpucp_pll_od_reg, 373 cpucp_pll_div_factor_reg, 374 cpucp_pll_div_sel_reg 375 }; 376 377 enum cpucp_pll_type_attributes { 378 cpucp_pll_cpu, 379 cpucp_pll_pci, 380 }; 381 382 /* Event Queue Packets */ 383 384 struct eq_generic_event { 385 __le64 data[7]; 386 }; 387 388 /* 389 * CpuCP info 390 */ 391 392 #define CARD_NAME_MAX_LEN 16 393 #define VERSION_MAX_LEN 128 394 #define CPUCP_MAX_SENSORS 128 395 396 struct cpucp_sensor { 397 __le32 type; 398 __le32 flags; 399 }; 400 401 /** 402 * struct cpucp_card_types - ASIC card type. 403 * @cpucp_card_type_pci: PCI card. 404 * @cpucp_card_type_pmc: PCI Mezzanine Card. 405 */ 406 enum cpucp_card_types { 407 cpucp_card_type_pci, 408 cpucp_card_type_pmc 409 }; 410 411 /** 412 * struct cpucp_info - Info from CpuCP that is necessary to the host's driver 413 * @sensors: available sensors description. 414 * @kernel_version: CpuCP linux kernel version. 415 * @reserved: reserved field. 416 * @card_type: card configuration type. 417 * @card_location: in a server, each card has different connections topology 418 * depending on its location (relevant for PMC card type) 419 * @cpld_version: CPLD programmed F/W version. 420 * @infineon_version: Infineon main DC-DC version. 421 * @fuse_version: silicon production FUSE information. 422 * @thermal_version: thermald S/W version. 423 * @cpucp_version: CpuCP S/W version. 424 * @dram_size: available DRAM size. 425 * @card_name: card name that will be displayed in HWMON subsystem on the host 426 */ 427 struct cpucp_info { 428 struct cpucp_sensor sensors[CPUCP_MAX_SENSORS]; 429 __u8 kernel_version[VERSION_MAX_LEN]; 430 __le32 reserved; 431 __le32 card_type; 432 __le32 card_location; 433 __le32 cpld_version; 434 __le32 infineon_version; 435 __u8 fuse_version[VERSION_MAX_LEN]; 436 __u8 thermal_version[VERSION_MAX_LEN]; 437 __u8 cpucp_version[VERSION_MAX_LEN]; 438 __le32 reserved2; 439 __le64 dram_size; 440 char card_name[CARD_NAME_MAX_LEN]; 441 }; 442 443 #endif /* CPUCP_IF_H */ 444
