| /Linux-v5.10/arch/arm/boot/dts/ |
| D | omap24xx-clocks.dtsi | 3 * Device Tree Source for OMAP24xx clock data
9 #clock-cells = <0>;
10 compatible = "ti,composite-mux-clock";
17 #clock-cells = <0>;
18 compatible = "ti,composite-clock";
23 #clock-cells = <0>;
24 compatible = "ti,composite-mux-clock";
31 #clock-cells = <0>;
32 compatible = "ti,composite-clock";
39 #clock-cells = <0>;
[all …]
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| D | am43xx-clocks.dtsi | 3 * Device Tree Source for AM43xx clock data
9 #clock-cells = <0>;
10 compatible = "ti,mux-clock";
17 #clock-cells = <0>;
18 compatible = "ti,mux-clock";
25 #clock-cells = <0>;
26 compatible = "ti,mux-clock";
33 #clock-cells = <0>;
34 compatible = "fixed-factor-clock";
36 clock-mult = <1>;
[all …]
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| D | am33xx-clocks.dtsi | 3 * Device Tree Source for AM33xx clock data
9 #clock-cells = <0>;
10 compatible = "ti,mux-clock";
17 #clock-cells = <0>;
18 compatible = "fixed-factor-clock";
20 clock-mult = <1>;
21 clock-div = <1>;
25 #clock-cells = <0>;
26 compatible = "fixed-factor-clock";
28 clock-mult = <1>;
[all …]
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| D | omap3xxx-clocks.dtsi | 3 * Device Tree Source for OMAP3 clock data
9 #clock-cells = <0>;
10 compatible = "fixed-clock";
11 clock-frequency = <16800000>;
15 #clock-cells = <0>;
16 compatible = "ti,mux-clock";
22 #clock-cells = <0>;
23 compatible = "ti,divider-clock";
32 #clock-cells = <0>;
33 compatible = "ti,gate-clock";
[all …]
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| D | keystone-clocks.dtsi | 3 * Device Tree Source for Keystone 2 clock tree
14 #clock-cells = <0>;
15 compatible = "ti,keystone,pll-mux-clock";
20 clock-output-names = "mainmuxclk";
24 #clock-cells = <0>;
25 compatible = "fixed-factor-clock";
27 clock-div = <1>;
28 clock-mult = <1>;
29 clock-output-names = "chipclk1";
33 #clock-cells = <0>;
[all …]
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| D | omap54xx-clocks.dtsi | 3 * Device Tree Source for OMAP5 clock data
9 #clock-cells = <0>;
10 compatible = "fixed-clock";
11 clock-frequency = <12000000>;
15 #clock-cells = <0>;
16 compatible = "ti,gate-clock";
23 #clock-cells = <0>;
24 compatible = "fixed-clock";
25 clock-frequency = <32768>;
29 #clock-cells = <0>;
[all …]
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| D | dra7xx-clocks.dtsi | 3 * Device Tree Source for DRA7xx clock data
9 #clock-cells = <0>;
10 compatible = "ti,dra7-atl-clock";
15 #clock-cells = <0>;
16 compatible = "ti,dra7-atl-clock";
21 #clock-cells = <0>;
22 compatible = "ti,dra7-atl-clock";
27 #clock-cells = <0>;
28 compatible = "ti,dra7-atl-clock";
33 #clock-cells = <0>;
[all …]
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| D | dm814x-clocks.dtsi | 10 #clock-cells = <1>;
11 compatible = "ti,dm814-adpll-s-clock";
14 clock-names = "clkinp", "clkinpulow", "clkinphif";
15 clock-output-names = "481c5040.adpll.dcoclkldo",
22 #clock-cells = <1>;
23 compatible = "ti,dm814-adpll-lj-clock";
26 clock-names = "clkinp", "clkinpulow";
27 clock-output-names = "481c5080.adpll.dcoclkldo",
33 #clock-cells = <1>;
34 compatible = "ti,dm814-adpll-lj-clock";
[all …]
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| D | omap44xx-clocks.dtsi | 3 * Device Tree Source for OMAP4 clock data
9 #clock-cells = <0>;
10 compatible = "fixed-clock";
11 clock-frequency = <59000000>;
15 #clock-cells = <0>;
16 compatible = "fixed-clock";
17 clock-frequency = <12000000>;
21 #clock-cells = <0>;
22 compatible = "ti,gate-clock";
29 #clock-cells = <0>;
[all …]
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| D | ste-nomadik-stn8815.dtsi | 41 clock-names = "timclk", "apb_pclk";
50 clock-names = "timclk", "apb_pclk";
199 #clock-cells = <0>;
200 compatible = "fixed-clock";
201 clock-frequency = <19200000>;
205 * The 2.4 MHz TIMCLK reference clock is active at
207 * divided by 8. This clock is used by the timers and
211 #clock-cells = <0>;
212 compatible = "fixed-factor-clock";
213 clock-div = <8>;
[all …]
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| D | omap36xx-omap3430es2plus-clocks.dtsi | 3 * Device Tree Source for OMAP34xx/OMAP36xx clock data
9 #clock-cells = <0>;
10 compatible = "ti,composite-no-wait-gate-clock";
17 #clock-cells = <0>;
18 compatible = "ti,composite-divider-clock";
26 #clock-cells = <0>;
27 compatible = "ti,composite-clock";
32 #clock-cells = <0>;
33 compatible = "fixed-factor-clock";
35 clock-mult = <1>;
[all …]
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| D | dm816x-clocks.dtsi | 5 #clock-cells = <1>;
6 compatible = "ti,dm816-fapll-clock";
9 clock-indices = <1>, <2>, <3>, <4>, <5>,
11 clock-output-names = "main_pll_clk1",
21 #clock-cells = <1>;
22 compatible = "ti,dm816-fapll-clock";
25 clock-indices = <1>, <2>, <3>, <4>;
26 clock-output-names = "ddr_pll_clk1",
33 #clock-cells = <1>;
34 compatible = "ti,dm816-fapll-clock";
[all …]
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| D | keystone-k2hk-clocks.dtsi | 3 * Keystone 2 Kepler/Hawking SoC clock nodes
10 #clock-cells = <0>;
11 compatible = "ti,keystone,pll-clock";
13 clock-output-names = "arm-pll-clk";
19 #clock-cells = <0>;
20 compatible = "ti,keystone,main-pll-clock";
27 #clock-cells = <0>;
28 compatible = "ti,keystone,pll-clock";
30 clock-output-names = "papllclk";
36 #clock-cells = <0>;
[all …]
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| D | exynos5420.dtsi | 14 #include <dt-bindings/clock/exynos5420.h>
15 #include <dt-bindings/clock/exynos-audss-clk.h>
52 clock-latency-ns = <140000>;
57 clock-latency-ns = <140000>;
62 clock-latency-ns = <140000>;
67 clock-latency-ns = <140000>;
72 clock-latency-ns = <140000>;
77 clock-latency-ns = <140000>;
82 clock-latency-ns = <140000>;
87 clock-latency-ns = <140000>;
[all …]
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| D | omap36xx-am35xx-omap3430es2plus-clocks.dtsi | 3 * Device Tree Source for OMAP36xx/AM35xx/OMAP34xx clock data
9 #clock-cells = <0>;
10 compatible = "fixed-factor-clock";
12 clock-mult = <1>;
13 clock-div = <3>;
17 #clock-cells = <0>;
18 compatible = "fixed-factor-clock";
20 clock-mult = <1>;
21 clock-div = <5>;
26 #clock-cells = <0>;
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| D | exynos5410.dtsi | 14 #include <dt-bindings/clock/exynos5410.h>
15 #include <dt-bindings/clock/exynos-audss-clk.h>
37 clock-frequency = <1600000000>;
44 clock-frequency = <1600000000>;
51 clock-frequency = <1600000000>;
58 clock-frequency = <1600000000>;
71 clock-names = "clkout16";
73 #clock-cells = <1>;
76 clock: clock-controller@10010000 { label
77 compatible = "samsung,exynos5410-clock";
[all …]
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| D | keystone-k2l-clocks.dtsi | 3 * Keystone 2 lamarr SoC clock nodes
10 #clock-cells = <0>;
11 compatible = "ti,keystone,pll-clock";
13 clock-output-names = "arm-pll-clk";
19 #clock-cells = <0>;
20 compatible = "ti,keystone,main-pll-clock";
27 #clock-cells = <0>;
28 compatible = "ti,keystone,pll-clock";
30 clock-output-names = "papllclk";
36 #clock-cells = <0>;
[all …]
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| /Linux-v5.10/drivers/net/ethernet/mellanox/mlx5/core/lib/ |
| D | clock.c | 92 struct mlx5_clock *clock = container_of(cc, struct mlx5_clock, cycles); in read_internal_timer() local
93 struct mlx5_core_dev *mdev = container_of(clock, struct mlx5_core_dev, in read_internal_timer()
94 clock); in read_internal_timer()
102 struct mlx5_clock *clock = &mdev->clock; in mlx5_update_clock_info_page() local
112 clock_info->cycles = clock->tc.cycle_last; in mlx5_update_clock_info_page()
113 clock_info->mult = clock->cycles.mult; in mlx5_update_clock_info_page()
114 clock_info->nsec = clock->tc.nsec; in mlx5_update_clock_info_page()
115 clock_info->frac = clock->tc.frac; in mlx5_update_clock_info_page()
125 struct mlx5_clock *clock = container_of(pps_info, struct mlx5_clock, in mlx5_pps_out() local
127 struct mlx5_core_dev *mdev = container_of(clock, struct mlx5_core_dev, in mlx5_pps_out()
[all …]
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| /Linux-v5.10/drivers/net/ipa/ |
| D | ipa_clock.c | 76 static int ipa_interconnect_init(struct ipa_clock *clock, struct device *dev) in ipa_interconnect_init() argument
83 clock->memory_path = path; in ipa_interconnect_init()
88 clock->imem_path = path; in ipa_interconnect_init()
93 clock->config_path = path; in ipa_interconnect_init()
98 icc_put(clock->imem_path); in ipa_interconnect_init()
100 icc_put(clock->memory_path); in ipa_interconnect_init()
106 static void ipa_interconnect_exit(struct ipa_clock *clock) in ipa_interconnect_exit() argument
108 icc_put(clock->config_path); in ipa_interconnect_exit()
109 icc_put(clock->imem_path); in ipa_interconnect_exit()
110 icc_put(clock->memory_path); in ipa_interconnect_exit()
[all …]
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| /Linux-v5.10/Documentation/devicetree/bindings/clock/ |
| D | mvebu-core-clock.txt | 3 Marvell MVEBU SoCs usually allow to determine core clock frequencies by
4 reading the Sample-At-Reset (SAR) register. The core clock consumer should
5 specify the desired clock by having the clock ID in its "clocks" phandle cell.
7 The following is a list of provided IDs and clock names on Armada 370/XP:
8 0 = tclk (Internal Bus clock)
9 1 = cpuclk (CPU clock)
10 2 = nbclk (L2 Cache clock)
11 3 = hclk (DRAM control clock)
12 4 = dramclk (DDR clock)
14 The following is a list of provided IDs and clock names on Armada 375:
[all …]
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| D | lpc1850-cgu.txt | 4 peripheral blocks of the LPC18xx. Each independent clock is called
5 a base clock and itself is one of the inputs to the two Clock
9 The CGU selects the inputs to the clock generators from multiple
10 clock sources, controls the clock generation, and routes the outputs
11 of the clock generators through the clock source bus to the output
12 stages. Each output stage provides an independent clock source and
18 This binding uses the common clock binding:
19 Documentation/devicetree/bindings/clock/clock-bindings.txt
26 containing clock control registers
27 - #clock-cells:
[all …]
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| D | ste-u300-syscon-clock.txt | 7 - #clock-cells: must be <0>
8 - clock-type: specifies the type of clock:
9 0 = slow clock
10 1 = fast clock
11 2 = rest/remaining clock
12 - clock-id: specifies the clock in the type range
15 - clocks: parent clock(s)
21 0 0 Slow peripheral bridge clock
22 0 1 UART0 clock
23 0 4 GPIO clock
[all …]
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| D | exynos5260-clock.txt | 3 Exynos5260 has 13 clock controllers which are instantiated
4 independently from the device-tree. These clock controllers
8 Each clock is assigned an identifier and client nodes can use
9 this identifier to specify the clock which they consume. All
11 dt-bindings/clock/exynos5260-clk.h header and can be used in
17 is expected that they are defined using standard clock bindings
18 with following clock-output-names:
20 - "fin_pll" - PLL input clock from XXTI
21 - "xrtcxti" - input clock from XRTCXTI
22 - "ioclk_pcm_extclk" - pcm external operation clock
[all …]
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| /Linux-v5.10/arch/arm64/boot/dts/amd/ |
| D | amd-seattle-clks.dtsi | 9 compatible = "fixed-clock";
10 #clock-cells = <0>;
11 clock-frequency = <100000000>;
12 clock-output-names = "adl3clk_100mhz";
16 compatible = "fixed-clock";
17 #clock-cells = <0>;
18 clock-frequency = <375000000>;
19 clock-output-names = "ccpclk_375mhz";
23 compatible = "fixed-clock";
24 #clock-cells = <0>;
[all …]
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| /Linux-v5.10/Documentation/devicetree/bindings/clock/ti/ |
| D | gate.txt | 1 Binding for Texas Instruments gate clock.
5 This binding uses the common clock binding[1]. This clock is
6 quite much similar to the basic gate-clock [2], however,
8 is provided for this clock, the code assumes that a clockdomain
12 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
13 [2] Documentation/devicetree/bindings/clock/gpio-gate-clock.txt
14 [3] Documentation/devicetree/bindings/clock/ti/clockdomain.txt
18 "ti,gate-clock" - basic gate clock
19 "ti,wait-gate-clock" - gate clock which waits until clock is active before
21 "ti,dss-gate-clock" - gate clock with DSS specific hardware handling
[all …]
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