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Searched refs:clk_type (Results 1 – 25 of 35) sorted by relevance

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/Linux-v5.10/drivers/gpu/drm/amd/display/dc/
Ddm_services_types.h82 #define DC_DECODE_PP_CLOCK_TYPE(clk_type) \ argument
83 (clk_type) == DM_PP_CLOCK_TYPE_DISPLAY_CLK ? "Display" : \
84 (clk_type) == DM_PP_CLOCK_TYPE_ENGINE_CLK ? "Engine" : \
85 (clk_type) == DM_PP_CLOCK_TYPE_MEMORY_CLK ? "Memory" : \
86 (clk_type) == DM_PP_CLOCK_TYPE_DCFCLK ? "DCF" : \
87 (clk_type) == DM_PP_CLOCK_TYPE_DCEFCLK ? "DCEF" : \
88 (clk_type) == DM_PP_CLOCK_TYPE_SOCCLK ? "SoC" : \
89 (clk_type) == DM_PP_CLOCK_TYPE_PIXELCLK ? "Pixel" : \
90 (clk_type) == DM_PP_CLOCK_TYPE_DISPLAYPHYCLK ? "Display PHY" : \
91 (clk_type) == DM_PP_CLOCK_TYPE_DPPCLK ? "DPP" : \
[all …]
Ddm_services.h210 enum dm_pp_clock_type clk_type,
215 enum dm_pp_clock_type clk_type,
220 enum dm_pp_clock_type clk_type,
/Linux-v5.10/sound/soc/intel/skylake/
Dskl-ssp-clk.c57 static int skl_get_vbus_id(u32 index, u8 clk_type) in skl_get_vbus_id() argument
59 switch (clk_type) { in skl_get_vbus_id()
74 static void skl_fill_clk_ipc(struct skl_clk_rate_cfg_table *rcfg, u8 clk_type) in skl_fill_clk_ipc() argument
84 if (clk_type == SKL_SCLK_FS) { in skl_fill_clk_ipc()
107 u32 vbus_id, u8 clk_type, in skl_send_clk_dma_control() argument
125 if (clk_type == SKL_SCLK_FS) { in skl_send_clk_dma_control()
132 if (clk_type == SKL_SCLK) in skl_send_clk_dma_control()
181 int vbus_id, clk_type; in skl_clk_change_status() local
183 clk_type = skl_get_clk_type(clkdev->id); in skl_clk_change_status()
184 if (clk_type < 0) in skl_clk_change_status()
[all …]
/Linux-v5.10/drivers/clk/imx/
Dclk-scu.h15 int num_parents, u32 rsrc_id, u8 clk_type);
18 u8 clk_type) in imx_clk_scu() argument
20 return __imx_clk_scu(name, NULL, 0, rsrc_id, clk_type); in imx_clk_scu()
24 int num_parents, u32 rsrc_id, u8 clk_type) in imx_clk_scu2() argument
26 return __imx_clk_scu(name, parents, num_parents, rsrc_id, clk_type); in imx_clk_scu2()
Dclk-scu.c29 u8 clk_type; member
158 msg.data.req.clk = clk->clk_type; in clk_scu_recalc_rate()
230 msg.clk = clk->clk_type; in clk_scu_set_rate()
248 msg.data.req.clk = clk->clk_type; in clk_scu_get_parent()
272 msg.clk = clk->clk_type; in clk_scu_set_parent()
308 clk->clk_type, true, false); in clk_scu_prepare()
323 clk->clk_type, false, false); in clk_scu_unprepare()
348 int num_parents, u32 rsrc_id, u8 clk_type) in __imx_clk_scu() argument
360 clk->clk_type = clk_type; in __imx_clk_scu()
/Linux-v5.10/drivers/gpu/drm/amd/pm/swsmu/smu12/
Drenoir_ppt.c177 static int renoir_get_dpm_clk_limited(struct smu_context *smu, enum smu_clk_type clk_type, in renoir_get_dpm_clk_limited() argument
182 if (!clk_table || clk_type >= SMU_CLK_COUNT) in renoir_get_dpm_clk_limited()
185 switch (clk_type) { in renoir_get_dpm_clk_limited()
244 enum smu_clk_type clk_type, in renoir_get_dpm_ultimate_freq() argument
252 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) { in renoir_get_dpm_ultimate_freq()
253 switch (clk_type) { in renoir_get_dpm_ultimate_freq()
288 switch (clk_type) { in renoir_get_dpm_ultimate_freq()
300 ret = renoir_get_dpm_clk_limited(smu, clk_type, mclk_mask, max); in renoir_get_dpm_ultimate_freq()
305 ret = renoir_get_dpm_clk_limited(smu, clk_type, soc_mask, max); in renoir_get_dpm_ultimate_freq()
316 switch (clk_type) { in renoir_get_dpm_ultimate_freq()
[all …]
Dsmu_v12_0.c204 int smu_v12_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_type clk_type, in smu_v12_0_set_soft_freq_limited_range() argument
209 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) in smu_v12_0_set_soft_freq_limited_range()
212 switch (clk_type) { in smu_v12_0_set_soft_freq_limited_range()
/Linux-v5.10/drivers/gpu/drm/amd/pm/inc/
Dsmu_v11_0.h232 int smu_v11_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,
235 int smu_v11_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_type clk_type,
239 enum smu_clk_type clk_type,
250 enum smu_clk_type clk_type,
255 enum smu_clk_type clk_type,
259 enum smu_clk_type clk_type,
263 enum smu_clk_type clk_type,
Damdgpu_smu.h471 int (*print_clk_levels)(struct smu_context *smu, enum smu_clk_type clk_type, char *buf);
472 int (*force_clk_levels)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t mask);
474 int (*get_od_percentage)(struct smu_context *smu, enum smu_clk_type clk_type);
476 enum smu_clk_type clk_type,
482 enum smu_clk_type clk_type,
593 …int (*get_dpm_ultimate_freq)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t *min, u…
594 …int (*set_soft_freq_limited_range)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t m…
685 int smu_print_clk_levels(struct smu_context *smu, enum smu_clk_type clk_type, char *buf);
718 enum smu_clk_type clk_type,
776 int smu_get_dpm_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
[all …]
Dsmu_v12_0.h58 int smu_v12_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_type clk_type,
/Linux-v5.10/drivers/gpu/drm/amd/display/amdgpu_dm/
Damdgpu_dm_pp_smu.c120 enum dm_pp_clock_type clk_type, in get_default_clock_levels() argument
129 switch (clk_type) { in get_default_clock_levels()
333 enum dm_pp_clock_type clk_type, in dm_pp_get_clock_levels_by_type() argument
344 dc_to_pp_clock_type(clk_type), &pp_clks)) { in dm_pp_get_clock_levels_by_type()
346 get_default_clock_levels(clk_type, dc_clks); in dm_pp_get_clock_levels_by_type()
351 dc_to_pp_clock_type(clk_type), in dm_pp_get_clock_levels_by_type()
353 get_default_clock_levels(clk_type, dc_clks); in dm_pp_get_clock_levels_by_type()
358 pp_to_dc_clock_levels(&pp_clks, dc_clks, clk_type); in dm_pp_get_clock_levels_by_type()
391 if (clk_type == DM_PP_CLOCK_TYPE_ENGINE_CLK) { in dm_pp_get_clock_levels_by_type()
403 } else if (clk_type == DM_PP_CLOCK_TYPE_MEMORY_CLK) { in dm_pp_get_clock_levels_by_type()
[all …]
/Linux-v5.10/drivers/gpu/drm/amd/pm/swsmu/smu11/
Dsmu_v11_0.c1015 enum amd_pp_clock_type clk_type = clock_req->clock_type; in smu_v11_0_display_clock_voltage_request() local
1022 switch (clk_type) { in smu_v11_0_display_clock_voltage_request()
1548 int smu_v11_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type, in smu_v11_0_get_dpm_ultimate_freq() argument
1555 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) { in smu_v11_0_get_dpm_ultimate_freq()
1556 switch (clk_type) { in smu_v11_0_get_dpm_ultimate_freq()
1584 clk_type); in smu_v11_0_get_dpm_ultimate_freq()
1608 enum smu_clk_type clk_type, in smu_v11_0_set_soft_freq_limited_range() argument
1616 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) in smu_v11_0_set_soft_freq_limited_range()
1621 clk_type); in smu_v11_0_set_soft_freq_limited_range()
1625 if (clk_type == SMU_GFXCLK) in smu_v11_0_set_soft_freq_limited_range()
[all …]
Dsienna_cichlid_ppt.c838 enum smu_clk_type clk_type, in sienna_cichlid_get_current_clk_freq_by_table() argument
846 clk_type); in sienna_cichlid_get_current_clk_freq_by_table()
888 …ool sienna_cichlid_is_support_fine_grained_dpm(struct smu_context *smu, enum smu_clk_type clk_type) in sienna_cichlid_is_support_fine_grained_dpm() argument
896 clk_type); in sienna_cichlid_is_support_fine_grained_dpm()
904 enum smu_clk_type clk_type, char *buf) in sienna_cichlid_print_clk_levels() argument
917 switch (clk_type) { in sienna_cichlid_print_clk_levels()
925 ret = sienna_cichlid_get_current_clk_freq_by_table(smu, clk_type, &cur_value); in sienna_cichlid_print_clk_levels()
930 if ((clk_type == SMU_GFXCLK) || (clk_type == SMU_SCLK)) in sienna_cichlid_print_clk_levels()
933 ret = smu_v11_0_get_dpm_level_count(smu, clk_type, &count); in sienna_cichlid_print_clk_levels()
937 if (!sienna_cichlid_is_support_fine_grained_dpm(smu, clk_type)) { in sienna_cichlid_print_clk_levels()
[all …]
Dnavi10_ppt.c848 enum smu_clk_type clk_type, in navi10_get_current_clk_freq_by_table() argument
856 clk_type); in navi10_get_current_clk_freq_by_table()
888 static bool navi10_is_support_fine_grained_dpm(struct smu_context *smu, enum smu_clk_type clk_type) in navi10_is_support_fine_grained_dpm() argument
896 clk_type); in navi10_is_support_fine_grained_dpm()
919 enum smu_clk_type clk_type, char *buf) in navi10_print_clk_levels() argument
936 switch (clk_type) { in navi10_print_clk_levels()
944 ret = navi10_get_current_clk_freq_by_table(smu, clk_type, &cur_value); in navi10_print_clk_levels()
948 ret = smu_v11_0_get_dpm_level_count(smu, clk_type, &count); in navi10_print_clk_levels()
952 if (!navi10_is_support_fine_grained_dpm(smu, clk_type)) { in navi10_print_clk_levels()
954 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, i, &value); in navi10_print_clk_levels()
[all …]
/Linux-v5.10/drivers/clk/
Dclk-u300.c878 u32 clk_type; in of_u300_syscon_clk_init() local
882 if (of_property_read_u32(np, "clock-type", &clk_type)) { in of_u300_syscon_clk_init()
894 switch (clk_type) { in of_u300_syscon_clk_init()
908 pr_err("unknown clock type %x specified\n", clk_type); in of_u300_syscon_clk_init()
915 if (u3clk->type == clk_type && u3clk->id == clk_id) in of_u300_syscon_clk_init()
931 if (clk_type == U300_CLK_TYPE_REST && clk_id == 5) in of_u300_syscon_clk_init()
933 if (clk_type == U300_CLK_TYPE_REST && clk_id == 9) in of_u300_syscon_clk_init()
935 if (clk_type == U300_CLK_TYPE_REST && clk_id == 12) in of_u300_syscon_clk_init()
/Linux-v5.10/drivers/gpu/drm/amd/display/dc/clk_mgr/dce120/
Ddce120_clk_mgr.c98 clock_voltage_req.clk_type = DM_PP_CLOCK_TYPE_DISPLAY_CLK; in dce12_update_clocks()
113 clock_voltage_req.clk_type = DM_PP_CLOCK_TYPE_DISPLAYPHYCLK; in dce12_update_clocks()
/Linux-v5.10/drivers/input/
Devdev.c49 enum input_clock_type clk_type; member
146 struct timespec64 ts = ktime_to_timespec64(ev_time[client->clk_type]); in __evdev_queue_syn_dropped()
177 enum input_clock_type clk_type; in evdev_set_clk_type() local
182 clk_type = INPUT_CLK_REAL; in evdev_set_clk_type()
185 clk_type = INPUT_CLK_MONO; in evdev_set_clk_type()
188 clk_type = INPUT_CLK_BOOT; in evdev_set_clk_type()
194 if (client->clk_type != clk_type) { in evdev_set_clk_type()
195 client->clk_type = clk_type; in evdev_set_clk_type()
256 ts = ktime_to_timespec64(ev_time[client->clk_type]); in evdev_pass_values()
/Linux-v5.10/drivers/phy/
Dphy-xgene.c534 enum clk_type_t clk_type; /* Input clock selection */ member
705 enum clk_type_t clk_type) in xgene_phy_cfg_cmu_clk_type() argument
718 if (clk_type == CLK_EXT_DIFF) { in xgene_phy_cfg_cmu_clk_type()
728 } else if (clk_type == CLK_INT_DIFF) { in xgene_phy_cfg_cmu_clk_type()
738 } else if (clk_type == CLK_INT_SING) { in xgene_phy_cfg_cmu_clk_type()
759 enum clk_type_t clk_type) in xgene_phy_sata_cfg_cmu_core() argument
805 if (clk_type == CLK_EXT_DIFF) in xgene_phy_sata_cfg_cmu_core()
1135 enum clk_type_t clk_type) in xgene_phy_cal_rdy_chk() argument
1235 enum clk_type_t clk_type) in xgene_phy_pdwn_force_vco() argument
1252 enum clk_type_t clk_type, int ssc_enable) in xgene_phy_hw_init_sata() argument
[all …]
/Linux-v5.10/drivers/nfc/s3fwrn5/
Dnci.h64 __u8 clk_type; member
Dnci.c101 fw_cfg.clk_type = 0x01; in s3fwrn5_nci_rf_configure()
/Linux-v5.10/drivers/gpu/drm/amd/amdgpu/
Datombios_crtc.h41 u32 freq, u8 clk_type, u8 clk_src);
/Linux-v5.10/drivers/gpu/drm/amd/pm/swsmu/
Dsmu_cmn.h49 enum smu_clk_type clk_type);
Damdgpu_smu.c94 enum smu_clk_type clk_type, in smu_set_soft_freq_range() argument
104 clk_type, in smu_set_soft_freq_range()
114 enum smu_clk_type clk_type, in smu_get_dpm_freq_range() argument
127 clk_type, in smu_get_dpm_freq_range()
1701 enum smu_clk_type clk_type, in smu_force_clk_levels() argument
1718 ret = smu->ppt_funcs->force_clk_levels(smu, clk_type, mask); in smu_force_clk_levels()
2019 int smu_print_clk_levels(struct smu_context *smu, enum smu_clk_type clk_type, char *buf) in smu_print_clk_levels() argument
2029 ret = smu->ppt_funcs->print_clk_levels(smu, clk_type, buf); in smu_print_clk_levels()
2348 enum smu_clk_type clk_type, in smu_get_clock_by_type_with_latency() argument
2359 ret = smu->ppt_funcs->get_clock_by_type_with_latency(smu, clk_type, clocks); in smu_get_clock_by_type_with_latency()
Dsmu_cmn.c293 enum smu_clk_type clk_type) in smu_cmn_clk_dpm_is_enabled() argument
297 switch (clk_type) { in smu_cmn_clk_dpm_is_enabled()
/Linux-v5.10/drivers/clk/zynqmp/
Dclkc.c42 enum clk_type { enum
73 enum clk_type type;

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