Searched refs:clk_pin_cntl (Results 1 – 2 of 2) sorted by relevance
963 union clk_pin_cntl_u clk_pin_cntl; member1204 w100_pwr_state.clk_pin_cntl.f.osc_en = 0x1; in w100_pwm_setup()1205 w100_pwr_state.clk_pin_cntl.f.osc_gain = 0x1f; in w100_pwm_setup()1206 w100_pwr_state.clk_pin_cntl.f.dont_use_xtalin = 0x0; in w100_pwm_setup()1207 w100_pwr_state.clk_pin_cntl.f.xtalin_pm_en = 0x0; in w100_pwm_setup()1208 w100_pwr_state.clk_pin_cntl.f.xtalin_dbl_en = par->mach->xtal_dbl ? 1 : 0; in w100_pwm_setup()1209 w100_pwr_state.clk_pin_cntl.f.cg_debug = 0x0; in w100_pwm_setup()1210 writel((u32) (w100_pwr_state.clk_pin_cntl.val), remapped_regs + mmCLK_PIN_CNTL); in w100_pwm_setup()
829 u32 clk_pin_cntl; in radeon_pm_setup_for_suspend() local947 clk_pin_cntl = INPLL( pllCLK_PIN_CNTL); in radeon_pm_setup_for_suspend()949 clk_pin_cntl &= ~CLK_PIN_CNTL__ACCESS_REGS_IN_SUSPEND; in radeon_pm_setup_for_suspend()978 clk_pin_cntl &= ~CLK_PIN_CNTL__CG_CLK_TO_OUTPIN; in radeon_pm_setup_for_suspend()979 clk_pin_cntl |= CLK_PIN_CNTL__XTALIN_ALWAYS_ONb; in radeon_pm_setup_for_suspend()980 OUTPLL( pllCLK_PIN_CNTL, clk_pin_cntl); in radeon_pm_setup_for_suspend()1034 clk_pin_cntl = INPLL( pllCLK_PIN_CNTL); in radeon_pm_setup_for_suspend()1041 clk_pin_cntl |= CLK_PIN_CNTL__XTALIN_ALWAYS_ONb; in radeon_pm_setup_for_suspend()1047 OUTPLL( pllCLK_PIN_CNTL, clk_pin_cntl); in radeon_pm_setup_for_suspend()
