c7 (reference) in projects: Linux-v5.10

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Searched refs:c7 (Results 1 – 25 of 81) sorted by relevance

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/Linux-v5.10/arch/arm/mm/
D	proc-arm1020.S	`85 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 86 mcr p15, 0, ip, c7, c10, 4 @ drain WB 88 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 103 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 118 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 141 mcr p15, 0, ip, c7, c10, 4 @ drain WB 144 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index 145 mcr p15, 0, ip, c7, c10, 4 @ drain WB 153 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 155 mcrne p15, 0, ip, c7, c10, 4 @ drain WB [all …]`
D	proc-mohawk.S	62 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 63 mcr p15, 0, ip, c7, c10, 4 @ drain WB 64 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 81 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer 82 mcr p15, 0, r0, c7, c0, 4 @ wait for interrupt 92 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 114 mcr p15, 0, ip, c7, c14, 0 @ clean & invalidate all D cache 116 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 117 mcrne p15, 0, ip, c7, c10, 0 @ drain write buffer 138 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry [all …]
D	proc-arm926.S	69 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 70 mcr p15, 0, ip, c7, c10, 4 @ drain WB 72 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 91 mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer 97 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 109 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 132 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache 134 1: mrc p15, 0, APSR_nzcv, c7, c14, 3 @ test,clean,invalidate 138 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 139 mcrne p15, 0, ip, c7, c10, 4 @ drain WB [all …]
D	cache-fa.S	45 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 66 mcr p15, 0, ip, c7, c14, 0 @ clean/invalidate D cache 68 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 69 mcrne p15, 0, ip, c7, c5, 6 @ invalidate BTB 70 mcrne p15, 0, ip, c7, c10, 4 @ drain write buffer 71 mcrne p15, 0, ip, c7, c5, 4 @ prefetch flush 91 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I line 92 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry 97 mcrne p15, 0, ip, c7, c5, 6 @ invalidate BTB 98 mcrne p15, 0, ip, c7, c10, 4 @ data write barrier [all …]
D	proc-arm925.S	109 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 110 mcr p15, 0, ip, c7, c10, 4 @ drain WB 112 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 129 mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer 132 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 143 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 166 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache 170 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index 175 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 176 mcrne p15, 0, ip, c7, c10, 4 @ drain WB [all …]
D	proc-arm920.S	77 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 78 mcr p15, 0, ip, c7, c10, 4 @ drain WB 80 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 95 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 108 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 132 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index 138 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 139 mcrne p15, 0, ip, c7, c10, 4 @ drain WB 158 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 160 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry [all …]
D	cache-v6.S	40 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache 41 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache 42 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache 43 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache 49 mcr p15, 0, r0, c7, c5, 0 @ invalidate I-cache 64 mcr p15, 0, r0, c7, c14, 0 @ D cache clean+invalidate 66 mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate 71 mcr p15, 0, r0, c7, c15, 0 @ Cache clean+invalidate 134 USER( mcr p15, 0, r0, c7, c10, 1 ) @ clean D line 141 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer [all …]
D	proc-arm922.S	79 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 80 mcr p15, 0, ip, c7, c10, 4 @ drain WB 82 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 97 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 110 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 134 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index 140 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 141 mcrne p15, 0, ip, c7, c10, 4 @ drain WB 160 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 162 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry [all …]
D	proc-arm1020e.S	85 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 86 mcr p15, 0, ip, c7, c10, 4 @ drain WB 88 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 103 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 118 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 141 mcr p15, 0, ip, c7, c10, 4 @ drain WB 144 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index 152 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 154 mcrne p15, 0, ip, c7, c10, 4 @ drain WB 174 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry [all …]
D	proc-arm946.S	`57 mcr p15, 0, ip, c7, c5, 0 @ flush I cache 58 mcr p15, 0, ip, c7, c6, 0 @ flush D cache 59 mcr p15, 0, ip, c7, c10, 4 @ drain WB 73 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 83 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 103 mcr p15, 0, ip, c7, c6, 0 @ flush D cache 107 2: mcr p15, 0, r3, c7, c14, 2 @ clean/flush D index 114 mcrne p15, 0, ip, c7, c5, 0 @ flush I cache 115 mcrne p15, 0, ip, c7, c10, 4 @ drain WB 137 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry [all …]`
D	proc-arm1022.S	85 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 86 mcr p15, 0, ip, c7, c10, 4 @ drain WB 88 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 103 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 118 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 143 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index 151 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 153 mcrne p15, 0, ip, c7, c10, 4 @ drain WB 173 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 180 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache [all …]
D	proc-arm1026.S	85 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 86 mcr p15, 0, ip, c7, c10, 4 @ drain WB 88 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 103 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 118 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 141 1: mrc p15, 0, APSR_nzcv, c7, c14, 3 @ test, clean, invalidate 146 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 148 mcrne p15, 0, ip, c7, c10, 4 @ drain WB 168 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 175 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache [all …]
D	proc-fa526.S	58 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 59 mcr p15, 0, ip, c7, c10, 4 @ drain WB 61 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 83 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 87 mcr p15, 0, r0, c7, c10, 4 @ drain WB 104 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache 106 mcr p15, 0, ip, c7, c14, 0 @ clean and invalidate whole D cache 108 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache 109 mcr p15, 0, ip, c7, c5, 6 @ invalidate BTB since mm changed 110 mcr p15, 0, ip, c7, c10, 4 @ data write barrier [all …]
D	proc-feroceon.S	69 mcr p15, 0, r0, c7, c10, 4 @ drain WB 91 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 92 mcr p15, 0, ip, c7, c10, 4 @ drain WB 94 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 112 mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer 113 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 123 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 149 2: mcr p15, 0, ip, c7, c14, 2 @ clean + invalidate D set/way 157 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 158 mcrne p15, 0, ip, c7, c10, 4 @ drain WB [all …]
D	proc-xsc3.S	68 1: mcr p15, 0, \rd, c7, c14, 2 @ clean/invalidate L1 D line 113 mcr p15, 0, ip, c7, c7, 0 @ invalidate L1 caches and BTB 118 mcr p15, 0, ip, c8, c7, 0 @ invalidate I and D TLBs 137 mcr p14, 0, r0, c7, c0, 0 @ go to idle 149 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 173 mcrne p15, 0, ip, c7, c5, 0 @ invalidate L1 I cache and BTB 174 mcrne p15, 0, ip, c7, c10, 4 @ data write barrier 175 mcrne p15, 0, ip, c7, c5, 4 @ prefetch flush 196 mcrne p15, 0, r0, c7, c5, 1 @ invalidate L1 I line 197 mcr p15, 0, r0, c7, c14, 1 @ clean/invalidate L1 D line [all …]
D	proc-xscale.S	91 1: mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line 93 mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line 95 mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line 97 mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line 156 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches & BTB 160 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 179 mcr p14, 0, r0, c7, c0, 0 @ Go to IDLE 191 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 215 mcrne p15, 0, ip, c7, c5, 0 @ Invalidate I cache & BTB 216 mcrne p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer [all …]
D	cache-v4wb.S	59 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 78 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache 95 mcr p15, 0, ip, c7, c10, 4 @ drain write buffer 112 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 117 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 118 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 123 mcrne p15, 0, ip, c7, c10, 4 @ drain write buffer 164 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 165 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 170 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache [all …]
D	proc-arm940.S	`50 mcr p15, 0, ip, c7, c5, 0 @ flush I cache 51 mcr p15, 0, ip, c7, c6, 0 @ flush D cache 52 mcr p15, 0, ip, c7, c10, 4 @ drain WB 66 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 76 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 108 mcr p15, 0, ip, c7, c6, 0 @ flush D cache 112 2: mcr p15, 0, r3, c7, c14, 2 @ clean/flush D index 119 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 120 mcrne p15, 0, ip, c7, c10, 4 @ drain WB 162 2: mcr p15, 0, r3, c7, c14, 2 @ clean/flush D index [all …]`
D	proc-arm720.S	`66 mcr p15, 0, r1, c7, c7, 0 @ invalidate cache 68 mcr p15, 0, r1, c8, c7, 0 @ flush TLB (v4) 93 mcr p15, 0, ip, c7, c7, 0 @ invalidate cache 95 mcr p15, 0, ip, c8, c7, 0 @ flush TLB (v4) 108 mcr p15, 0, r0, c7, c7, 0 @ invalidate caches 110 mcr p15, 0, r0, c8, c7, 0 @ flush TLB (v4) 136 mcr p15, 0, r0, c7, c7, 0 @ invalidate caches 138 mcr p15, 0, r0, c8, c7, 0 @ flush TLB (v4)`
D	tlb-fa.S	`40 mcr p15, 0, r3, c7, c10, 4 @ drain WB 43 1: mcr p15, 0, r0, c8, c7, 1 @ invalidate UTLB entry 47 mcr p15, 0, r3, c7, c10, 4 @ data write barrier 53 mcr p15, 0, r3, c7, c10, 4 @ drain WB 56 1: mcr p15, 0, r0, c8, c7, 1 @ invalidate UTLB entry 60 mcr p15, 0, r3, c7, c10, 4 @ data write barrier 61 mcr p15, 0, r3, c7, c5, 4 @ prefetch flush (isb)`
D	proc-sa110.S	65 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 66 mcr p15, 0, ip, c7, c10, 4 @ drain WB 68 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 117 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 138 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 154 mcr p15, 0, r0, c7, c10, 1 @ clean D entry 155 mcr p15, 0, r0, c7, c10, 4 @ drain WB 162 mcr p15, 0, r10, c7, c7 @ invalidate I,D caches on v4 163 mcr p15, 0, r10, c7, c10, 4 @ drain write buffer on v4 165 mcr p15, 0, r10, c8, c7 @ invalidate I,D TLBs on v4
D	proc-sa1100.S	73 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 74 mcr p15, 0, ip, c7, c10, 4 @ drain WB 76 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 127 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 149 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 165 mcr p15, 0, r0, c7, c10, 1 @ clean D entry 166 mcr p15, 0, r0, c7, c10, 4 @ drain WB 185 mcr p15, 0, ip, c8, c7, 0 @ flush I+D TLBs 186 mcr p15, 0, ip, c7, c7, 0 @ flush I&D cache 201 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4 [all …]
D	cache-v4.S	`40 mcr p15, 0, r0, c7, c7, 0 @ flush ID cache 59 mcr p15, 0, ip, c7, c7, 0 @ flush ID cache 115 mcr p15, 0, r0, c7, c7, 0 @ flush ID cache`
D	cache-v4wt.S	`48 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 70 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 71 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache 89 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 91 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry 122 1: mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry 140 mcr p15, 0, r2, c7, c5, 0 @ invalidate I cache 157 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry`
/Linux-v5.10/arch/arm/include/asm/hardware/
D	cp14.h	49 #define RCP14_DBGVCR() MRC14(0, c0, c7, 0) 64 #define RCP14_DBGBVR7() MRC14(0, c0, c7, 4) 80 #define RCP14_DBGBCR7() MRC14(0, c0, c7, 5) 96 #define RCP14_DBGWVR7() MRC14(0, c0, c7, 6) 112 #define RCP14_DBGWCR7() MRC14(0, c0, c7, 7) 129 #define RCP14_DBGBXVR7() MRC14(0, c1, c7, 1) 144 #define RCP14_DBGITCTRL() MRC14(0, c7, c0, 4) 145 #define RCP14_DBGCLAIMSET() MRC14(0, c7, c8, 6) 146 #define RCP14_DBGCLAIMCLR() MRC14(0, c7, c9, 6) 147 #define RCP14_DBGAUTHSTATUS() MRC14(0, c7, c14, 6) [all …]

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