| /Linux-v5.10/drivers/clk/imx/ |
| D | clk-gate2.c | 31 u8 bit_idx; member
56 reg &= ~(3 << gate->bit_idx); in clk_gate2_enable()
57 reg |= gate->cgr_val << gate->bit_idx; in clk_gate2_enable()
86 reg &= ~(3 << gate->bit_idx); in clk_gate2_disable()
94 static int clk_gate2_reg_is_enabled(void __iomem *reg, u8 bit_idx) in clk_gate2_reg_is_enabled() argument
98 if (((val >> bit_idx) & 1) == 1) in clk_gate2_reg_is_enabled()
111 return clk_gate2_reg_is_enabled(gate->reg, gate->bit_idx); in clk_gate2_is_enabled()
127 reg &= ~(3 << gate->bit_idx); in clk_gate2_disable_unused()
143 void __iomem *reg, u8 bit_idx, u8 cgr_val, in clk_hw_register_gate2() argument
158 gate->bit_idx = bit_idx; in clk_hw_register_gate2()
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| D | clk-lpcg-scu.c | 35 u8 bit_idx; member
50 reg &= ~(CLK_GATE_SCU_LPCG_MASK << clk->bit_idx); in clk_lpcg_scu_enable()
56 reg |= val << clk->bit_idx; in clk_lpcg_scu_enable()
73 reg &= ~(CLK_GATE_SCU_LPCG_MASK << clk->bit_idx); in clk_lpcg_scu_disable()
86 u8 bit_idx, bool hw_gate) in imx_clk_lpcg_scu() argument
98 clk->bit_idx = bit_idx; in imx_clk_lpcg_scu()
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| /Linux-v5.10/drivers/clk/ |
| D | clk-gate.c | 70 reg = BIT(gate->bit_idx + 16); in clk_gate_endisable()
72 reg |= BIT(gate->bit_idx); in clk_gate_endisable()
77 reg |= BIT(gate->bit_idx); in clk_gate_endisable()
79 reg &= ~BIT(gate->bit_idx); in clk_gate_endisable()
111 reg ^= BIT(gate->bit_idx); in clk_gate_is_enabled()
113 reg &= BIT(gate->bit_idx); in clk_gate_is_enabled()
131 void __iomem *reg, u8 bit_idx, in __clk_hw_register_gate() argument
140 if (bit_idx > 15) { in __clk_hw_register_gate()
164 gate->bit_idx = bit_idx; in __clk_hw_register_gate()
186 void __iomem *reg, u8 bit_idx, in clk_register_gate() argument
[all …]
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| D | clk-stm32f4.c | 49 u8 bit_idx; member
414 u8 bit_idx; member
424 if (readl(base + STM32F4_RCC_CFGR) & BIT(am->bit_idx)) in clk_apb_mul_recalc_rate()
436 if (readl(base + STM32F4_RCC_CFGR) & BIT(am->bit_idx)) in clk_apb_mul_round_rate()
468 unsigned long flags, u8 bit_idx) in clk_register_apb_mul() argument
478 am->bit_idx = bit_idx; in clk_register_apb_mul()
543 u8 bit_idx; member
815 pll->gate.bit_idx = vco->bit_idx; in stm32f4_rcc_register_pll()
821 pll->status = (readl(base + STM32F4_RCC_CR) >> vco->bit_idx) & 0x1; in stm32f4_rcc_register_pll()
963 void __iomem *reg, u8 bit_idx, u8 bit_rdy_idx, in clk_register_rgate() argument
[all …]
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| D | clk-stm32h7.c | 217 void __iomem *reg, u8 bit_idx, u8 bit_rdy, in clk_register_ready_gate() argument
238 rgate->gate.bit_idx = bit_idx; in clk_register_ready_gate()
253 u8 bit_idx; member
332 static struct clk_gate *_get_cgate(void __iomem *reg, u8 bit_idx, u32 flags, in _get_cgate() argument
342 gate->bit_idx = bit_idx; in _get_cgate()
402 cfg->gate->bit_idx, in get_cfg_composite_div()
593 u8 bit_idx; member
603 .bit_idx = _bit_idx,\
622 u8 bit_idx; member
637 .bit_idx = 24,
[all …]
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| /Linux-v5.10/drivers/xen/events/ |
| D | events_2l.c | 171 int word_idx, bit_idx; in evtchn_2l_handle_events() local
181 bit_idx = evtchn % BITS_PER_LONG; in evtchn_2l_handle_events()
182 if (active_evtchns(cpu, s, word_idx) & (1ULL << bit_idx)) in evtchn_2l_handle_events()
208 bit_idx = 0; in evtchn_2l_handle_events()
214 bit_idx = 0; /* usually scan entire word from start */ in evtchn_2l_handle_events()
229 bit_idx = start_bit_idx; in evtchn_2l_handle_events()
236 bits = MASK_LSBS(pending_bits, bit_idx); in evtchn_2l_handle_events()
242 bit_idx = EVTCHN_FIRST_BIT(bits); in evtchn_2l_handle_events()
245 port = (word_idx * BITS_PER_EVTCHN_WORD) + bit_idx; in evtchn_2l_handle_events()
248 bit_idx = (bit_idx + 1) % BITS_PER_EVTCHN_WORD; in evtchn_2l_handle_events()
[all …]
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| /Linux-v5.10/drivers/clk/hisilicon/ |
| D | clkgate-separated.c | 27 u8 bit_idx; /* bits in enable/disable register */ member
41 reg = BIT(sclk->bit_idx); in clkgate_separated_enable()
58 reg = BIT(sclk->bit_idx); in clkgate_separated_disable()
72 reg &= BIT(sclk->bit_idx); in clkgate_separated_is_enabled()
86 void __iomem *reg, u8 bit_idx, in hisi_register_clkgate_sep() argument
104 sclk->bit_idx = bit_idx; in hisi_register_clkgate_sep()
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| /Linux-v5.10/drivers/clk/actions/ |
| D | owl-gate.c | 27 reg |= BIT(gate_hw->bit_idx); in owl_gate_set()
29 reg &= ~BIT(gate_hw->bit_idx); in owl_gate_set()
60 reg ^= BIT(gate_hw->bit_idx); in owl_gate_clk_is_enabled()
62 return !!(reg & BIT(gate_hw->bit_idx)); in owl_gate_clk_is_enabled()
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| D | owl-gate.h | 18 u8 bit_idx; member
30 .bit_idx = _bit_idx, \
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| D | owl-pll.c | 119 return !!(reg & BIT(pll_hw->bit_idx)); in owl_pll_is_enabled()
130 reg |= BIT(pll_hw->bit_idx); in owl_pll_set()
132 reg &= ~BIT(pll_hw->bit_idx); in owl_pll_set()
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| D | owl-pll.h | 27 u8 bit_idx; member
46 .bit_idx = _bit_idx, \
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| /Linux-v5.10/drivers/clk/meson/ |
| D | meson8b.c | 287 .bit_idx = 27,
315 .bit_idx = 28,
343 .bit_idx = 29,
371 .bit_idx = 30,
399 .bit_idx = 31,
464 .bit_idx = 14,
509 .bit_idx = 14,
554 .bit_idx = 14,
611 .bit_idx = 7,
793 .bit_idx = 8,
[all …]
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| D | gxbb.c | 571 .bit_idx = 27,
598 .bit_idx = 28,
636 .bit_idx = 29,
662 .bit_idx = 30,
688 .bit_idx = 31,
746 .bit_idx = 14,
789 .bit_idx = 14,
832 .bit_idx = 14,
894 .bit_idx = 7,
945 .bit_idx = 8,
[all …]
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| D | g12a-aoclk.c | 47 .bit_idx = (_bit), \
79 .bit_idx = 14,
106 .bit_idx = 31,
179 .bit_idx = 30,
197 .bit_idx = 31,
270 .bit_idx = 30,
358 .bit_idx = 8,
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| D | axg-aoclk.c | 38 .bit_idx = (_bit), \
62 .bit_idx = 14,
77 .bit_idx = 31,
160 .bit_idx = 30,
248 .bit_idx = 8,
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| D | g12a.c | 219 .bit_idx = 24,
236 .bit_idx = 24,
292 .bit_idx = 24,
329 .bit_idx = 20,
1133 .bit_idx = 1,
1152 .bit_idx = 1,
1212 .bit_idx = 1,
1246 .bit_idx = 17,
1280 .bit_idx = 18,
1324 .bit_idx = 23,
[all …]
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| D | axg.c | 337 .bit_idx = 27,
364 .bit_idx = 28,
402 .bit_idx = 29,
428 .bit_idx = 30,
456 .bit_idx = 31,
522 .bit_idx = 14,
573 .bit_idx = 14,
629 .bit_idx = 14,
680 .bit_idx = 0,
830 .bit_idx = 4,
[all …]
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| D | clk-regmap.c | 18 return regmap_update_bits(clk->map, gate->offset, BIT(gate->bit_idx), in clk_regmap_gate_endisable()
19 set ? BIT(gate->bit_idx) : 0); in clk_regmap_gate_endisable()
40 val ^= BIT(gate->bit_idx); in clk_regmap_gate_is_enabled()
42 val &= BIT(gate->bit_idx); in clk_regmap_gate_is_enabled()
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| D | gxbb-aoclk.c | 27 .bit_idx = (_bit), \
50 .bit_idx = 6,
65 .bit_idx = 31,
144 .bit_idx = 30,
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| D | clk-regmap.h | 46 u8 bit_idx; member
121 .bit_idx = (_bit), \
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| /Linux-v5.10/drivers/clk/mvebu/ |
| D | cp110-system-controller.c | 116 u8 bit_idx; member
126 BIT(gate->bit_idx), BIT(gate->bit_idx)); in cp110_gate_enable()
136 BIT(gate->bit_idx), 0); in cp110_gate_disable()
146 return val & BIT(gate->bit_idx); in cp110_gate_is_enabled()
157 struct regmap *regmap, u8 bit_idx) in cp110_register_gate() argument
176 gate->bit_idx = bit_idx; in cp110_register_gate()
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| /Linux-v5.10/drivers/mmc/host/ |
| D | meson-mx-sdhc-clkc.c | 117 clkc_data->mod_clk_en.bit_idx = 15; in meson_mx_sdhc_register_clkc()
125 clkc_data->tx_clk_en.bit_idx = 14; in meson_mx_sdhc_register_clkc()
133 clkc_data->rx_clk_en.bit_idx = 13; in meson_mx_sdhc_register_clkc()
141 clkc_data->sd_clk_en.bit_idx = 12; in meson_mx_sdhc_register_clkc()
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| /Linux-v5.10/drivers/clk/keystone/ |
| D | syscon-clk.c | 22 u32 bit_idx; member
82 priv->idx = BIT(data->bit_idx); in ti_syscon_gate_clk_register()
139 .bit_idx = (_bit_idx), \
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| /Linux-v5.10/drivers/clk/ti/ |
| D | interface.c | 37 struct clk_omap_reg *reg, u8 bit_idx, in _register_interface() argument
51 clk_hw->enable_bit = bit_idx; in _register_interface()
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| /Linux-v5.10/drivers/clk/st/ |
| D | clk-flexgen.c | 164 reg &= ~BIT(config->bit_idx); in flexgen_set_rate()
233 fgxbar->pgate.bit_idx = xbar_shift + 6; in clk_register_flexgen()
243 fgxbar->fgate.bit_idx = 6; in clk_register_flexgen()
253 fgxbar->sync.bit_idx = 7; in clk_register_flexgen()
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