| /Linux-v5.10/drivers/clk/ux500/ |
| D | u8500_of_clk.c | 65 u32 bases[CLKRST_MAX]; in u8500_clk_init() local
68 for (i = 0; i < ARRAY_SIZE(bases); i++) { in u8500_clk_init()
75 bases[i] = r.start; in u8500_clk_init()
255 clk = clk_reg_prcc_pclk("p1_pclk0", "per1clk", bases[CLKRST1_INDEX], in u8500_clk_init()
259 clk = clk_reg_prcc_pclk("p1_pclk1", "per1clk", bases[CLKRST1_INDEX], in u8500_clk_init()
263 clk = clk_reg_prcc_pclk("p1_pclk2", "per1clk", bases[CLKRST1_INDEX], in u8500_clk_init()
267 clk = clk_reg_prcc_pclk("p1_pclk3", "per1clk", bases[CLKRST1_INDEX], in u8500_clk_init()
271 clk = clk_reg_prcc_pclk("p1_pclk4", "per1clk", bases[CLKRST1_INDEX], in u8500_clk_init()
275 clk = clk_reg_prcc_pclk("p1_pclk5", "per1clk", bases[CLKRST1_INDEX], in u8500_clk_init()
279 clk = clk_reg_prcc_pclk("p1_pclk6", "per1clk", bases[CLKRST1_INDEX], in u8500_clk_init()
[all …]
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| /Linux-v5.10/include/linux/ |
| D | posix-timers.h | 124 struct posix_cputimer_base bases[CPUCLOCK_MAX]; member
142 pct->bases[0].nextevt = U64_MAX; in posix_cputimers_init()
143 pct->bases[1].nextevt = U64_MAX; in posix_cputimers_init()
144 pct->bases[2].nextevt = U64_MAX; in posix_cputimers_init()
152 pct->bases[CPUCLOCK_SCHED].nextevt = runtime; in posix_cputimers_rt_watchdog()
168 .bases = INIT_CPU_TIMERBASES(s.posix_cputimers.bases), \
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| /Linux-v5.10/drivers/gpu/drm/nouveau/dispnv50/ |
| D | base.c | 33 } bases[] = { in nv50_base_new() local
46 cid = nvif_mclass(&disp->disp->object, bases); in nv50_base_new()
52 return bases[cid].new(drm, head, bases[cid].oclass, pwndw); in nv50_base_new()
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| /Linux-v5.10/drivers/gpu/host1x/ |
| D | syncpt.c | 25 struct host1x_syncpt_base *bases = host->bases; in host1x_syncpt_base_request() local
29 if (!bases[i].requested) in host1x_syncpt_base_request()
35 bases[i].requested = true; in host1x_syncpt_base_request()
36 return &bases[i]; in host1x_syncpt_base_request()
367 struct host1x_syncpt_base *bases; in host1x_syncpt_init() local
376 bases = devm_kcalloc(host->dev, host->info->nb_bases, sizeof(*bases), in host1x_syncpt_init()
378 if (!bases) in host1x_syncpt_init()
394 bases[i].id = i; in host1x_syncpt_init()
398 host->bases = bases; in host1x_syncpt_init()
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| D | dev.h | 112 struct host1x_syncpt_base *bases; member
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| /Linux-v5.10/drivers/iommu/ |
| D | rockchip-iommu.c | 101 void __iomem **bases; member
290 writel(command, iommu->bases[i] + RK_MMU_COMMAND); in rk_iommu_command()
310 rk_iommu_write(iommu->bases[i], RK_MMU_ZAP_ONE_LINE, iova); in rk_iommu_zap_lines()
320 active &= !!(rk_iommu_read(iommu->bases[i], RK_MMU_STATUS) & in rk_iommu_is_stall_active()
332 enable &= !!(rk_iommu_read(iommu->bases[i], RK_MMU_STATUS) & in rk_iommu_is_paging_enabled()
344 done &= rk_iommu_read(iommu->bases[i], RK_MMU_DTE_ADDR) == 0; in rk_iommu_is_reset_done()
369 rk_iommu_read(iommu->bases[i], RK_MMU_STATUS)); in rk_iommu_enable_stall()
390 rk_iommu_read(iommu->bases[i], RK_MMU_STATUS)); in rk_iommu_disable_stall()
411 rk_iommu_read(iommu->bases[i], RK_MMU_STATUS)); in rk_iommu_enable_paging()
432 rk_iommu_read(iommu->bases[i], RK_MMU_STATUS)); in rk_iommu_disable_paging()
[all …]
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| /Linux-v5.10/drivers/iommu/arm/arm-smmu/ |
| D | arm-smmu-nvidia.c | 27 void __iomem *bases[NUM_SMMU_INSTANCES]; member
36 return nvidia_smmu->bases[inst] + (page << smmu->pgshift); in nvidia_smmu_page()
258 nvidia_smmu->bases[0] = smmu->base; in nvidia_smmu_impl_init()
264 nvidia_smmu->bases[1] = devm_ioremap_resource(dev, res); in nvidia_smmu_impl_init()
265 if (IS_ERR(nvidia_smmu->bases[1])) in nvidia_smmu_impl_init()
266 return ERR_CAST(nvidia_smmu->bases[1]); in nvidia_smmu_impl_init()
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| /Linux-v5.10/kernel/time/ |
| D | posix-cpu-timers.c | 27 pct->bases[CPUCLOCK_PROF].nextevt = cpu_limit * NSEC_PER_SEC; in posix_cputimers_group_init()
147 return !(~pct->bases[CPUCLOCK_PROF].nextevt | in expiry_cache_is_inactive()
148 ~pct->bases[CPUCLOCK_VIRT].nextevt | in expiry_cache_is_inactive()
149 ~pct->bases[CPUCLOCK_SCHED].nextevt); in expiry_cache_is_inactive()
476 cleanup_timerqueue(&pct->bases[CPUCLOCK_PROF].tqhead); in cleanup_timers()
477 cleanup_timerqueue(&pct->bases[CPUCLOCK_VIRT].tqhead); in cleanup_timers()
478 cleanup_timerqueue(&pct->bases[CPUCLOCK_SCHED].tqhead); in cleanup_timers()
507 base = p->posix_cputimers.bases + clkidx; in arm_timer()
509 base = p->signal->posix_cputimers.bases + clkidx; in arm_timer()
795 struct posix_cputimer_base *base = pct->bases; in collect_posix_cputimers()
[all …]
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| /Linux-v5.10/arch/x86/boot/ |
| D | early_serial_console.c | 77 static const int bases[] = { 0x3f8, 0x2f8 }; in parse_earlyprintk() local
86 port = bases[idx]; in parse_earlyprintk()
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| /Linux-v5.10/drivers/gpu/drm/exynos/ |
| D | exynos_drm_scaler.c | 154 static unsigned int bases[] = { in scaler_set_src_base() local
162 scaler_write(src_buf->dma_addr[i], bases[i]); in scaler_set_src_base()
217 static unsigned int bases[] = { in scaler_set_dst_base() local
225 scaler_write(dst_buf->dma_addr[i], bases[i]); in scaler_set_dst_base()
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| /Linux-v5.10/arch/x86/kernel/ |
| D | early_printk.c | 162 static const int __initconst bases[] = { 0x3f8, 0x2f8 }; in early_serial_init() local
169 early_serial_base = bases[port]; in early_serial_init()
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| /Linux-v5.10/Documentation/devicetree/bindings/interrupt-controller/ |
| D | mediatek,sysirq.txt | 31 mapped region. Could be multiple bases here. Ex: mt6797 needs 2 reg, others
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| /Linux-v5.10/drivers/platform/mellanox/ |
| D | Kconfig | 33 are defined per system type bases and include the registers related
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| /Linux-v5.10/drivers/net/wireless/broadcom/b43/ |
| D | pio.c | 82 static const u16 bases[] = { in index_to_pioqueue_base() local
105 B43_WARN_ON(index >= ARRAY_SIZE(bases)); in index_to_pioqueue_base()
106 return bases[index]; in index_to_pioqueue_base()
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| /Linux-v5.10/Documentation/devicetree/bindings/pinctrl/ |
| D | pinctrl-mt6797.txt | 9 iocfgr and iocfgt register bases.
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| /Linux-v5.10/Documentation/devicetree/bindings/cpufreq/ |
| D | cpufreq-qcom-hw.txt | 26 Definition: Addresses and sizes for the memory of the HW bases in
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| /Linux-v5.10/drivers/gpu/drm/i915/gt/ |
| D | intel_engine_cs.c | 228 const struct engine_mmio_base *bases) in __engine_mmio_base() argument
233 if (INTEL_GEN(i915) >= bases[i].gen) in __engine_mmio_base()
237 GEM_BUG_ON(!bases[i].base); in __engine_mmio_base()
239 return bases[i].base; in __engine_mmio_base()
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| /Linux-v5.10/drivers/gpu/drm/msm/ |
| D | NOTES | 58 register interface is same, just different bases.)
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| /Linux-v5.10/sound/pci/hda/ |
| D | hda_proc.c | 249 static const char * const bases[7] = { in get_jack_location() local
266 return bases[cfg & 0x0f]; in get_jack_location()
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| /Linux-v5.10/Documentation/devicetree/bindings/arm/ |
| D | cci.txt | 49 addressing scheme to declare their register bases.
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| /Linux-v5.10/Documentation/devicetree/bindings/spi/ |
| D | brcm,spi-bcm-qspi.txt | 45 Define the bases and ranges of the associated I/O address spaces.
|
| /Linux-v5.10/Documentation/timers/ |
| D | highres.rst | 169 decision is made per timer base and synchronized across per-cpu timer bases in
171 clock event devices for the per-CPU timer bases, but currently only one
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| /Linux-v5.10/Documentation/driver-api/thermal/ |
| D | cpu-idle-cooling.rst | 89 The implementation of the cooling device bases the number of states on
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| /Linux-v5.10/Documentation/x86/ |
| D | intel_txt.rst | 68 static root of trust must be used. This bases trust in BIOS
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| /Linux-v5.10/Documentation/filesystems/ |
| D | vfat.rst | 204 **nostale_ro**: This option bases the *inode* number and filehandle
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