| /Linux-v5.10/drivers/gpu/drm/amd/amdgpu/ |
| D | amdgpu_device.c | 134 struct amdgpu_device *adev = drm_to_adev(ddev); in amdgpu_device_get_pcie_replay_count() local
135 uint64_t cnt = amdgpu_asic_get_pcie_replay_count(adev); in amdgpu_device_get_pcie_replay_count()
143 static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev);
159 struct amdgpu_device *adev = drm_to_adev(ddev); in amdgpu_device_get_product_name() local
161 return snprintf(buf, PAGE_SIZE, "%s\n", adev->product_name); in amdgpu_device_get_product_name()
181 struct amdgpu_device *adev = drm_to_adev(ddev); in amdgpu_device_get_product_number() local
183 return snprintf(buf, PAGE_SIZE, "%s\n", adev->product_number); in amdgpu_device_get_product_number()
203 struct amdgpu_device *adev = drm_to_adev(ddev); in amdgpu_device_get_serial_number() local
205 return snprintf(buf, PAGE_SIZE, "%s\n", adev->serial); in amdgpu_device_get_serial_number()
221 struct amdgpu_device *adev = drm_to_adev(dev); in amdgpu_device_supports_boco() local
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| D | soc15.c | 102 static u32 soc15_pcie_rreg(struct amdgpu_device *adev, u32 reg) in soc15_pcie_rreg() argument
105 address = adev->nbio.funcs->get_pcie_index_offset(adev); in soc15_pcie_rreg()
106 data = adev->nbio.funcs->get_pcie_data_offset(adev); in soc15_pcie_rreg()
108 return amdgpu_device_indirect_rreg(adev, address, data, reg); in soc15_pcie_rreg()
111 static void soc15_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v) in soc15_pcie_wreg() argument
115 address = adev->nbio.funcs->get_pcie_index_offset(adev); in soc15_pcie_wreg()
116 data = adev->nbio.funcs->get_pcie_data_offset(adev); in soc15_pcie_wreg()
118 amdgpu_device_indirect_wreg(adev, address, data, reg, v); in soc15_pcie_wreg()
121 static u64 soc15_pcie_rreg64(struct amdgpu_device *adev, u32 reg) in soc15_pcie_rreg64() argument
124 address = adev->nbio.funcs->get_pcie_index_offset(adev); in soc15_pcie_rreg64()
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| D | nv.c | 70 static u32 nv_pcie_rreg(struct amdgpu_device *adev, u32 reg) in nv_pcie_rreg() argument
73 address = adev->nbio.funcs->get_pcie_index_offset(adev); in nv_pcie_rreg()
74 data = adev->nbio.funcs->get_pcie_data_offset(adev); in nv_pcie_rreg()
76 return amdgpu_device_indirect_rreg(adev, address, data, reg); in nv_pcie_rreg()
79 static void nv_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v) in nv_pcie_wreg() argument
83 address = adev->nbio.funcs->get_pcie_index_offset(adev); in nv_pcie_wreg()
84 data = adev->nbio.funcs->get_pcie_data_offset(adev); in nv_pcie_wreg()
86 amdgpu_device_indirect_wreg(adev, address, data, reg, v); in nv_pcie_wreg()
89 static u64 nv_pcie_rreg64(struct amdgpu_device *adev, u32 reg) in nv_pcie_rreg64() argument
92 address = adev->nbio.funcs->get_pcie_index_offset(adev); in nv_pcie_rreg64()
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| D | gmc_v10_0.c | 59 static int gmc_v10_0_ecc_interrupt_state(struct amdgpu_device *adev, in gmc_v10_0_ecc_interrupt_state() argument
68 gmc_v10_0_vm_fault_interrupt_state(struct amdgpu_device *adev, in gmc_v10_0_vm_fault_interrupt_state() argument
75 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_MMHUB_0, false); in gmc_v10_0_vm_fault_interrupt_state()
77 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_GFXHUB_0, false); in gmc_v10_0_vm_fault_interrupt_state()
81 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_MMHUB_0, true); in gmc_v10_0_vm_fault_interrupt_state()
83 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_GFXHUB_0, true); in gmc_v10_0_vm_fault_interrupt_state()
92 static int gmc_v10_0_process_interrupt(struct amdgpu_device *adev, in gmc_v10_0_process_interrupt() argument
96 struct amdgpu_vmhub *hub = &adev->vmhub[entry->vmid_src]; in gmc_v10_0_process_interrupt()
103 if (!amdgpu_sriov_vf(adev)) { in gmc_v10_0_process_interrupt()
120 amdgpu_vm_get_task_info(adev, entry->pasid, &task_info); in gmc_v10_0_process_interrupt()
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| D | gmc_v9_0.c | 417 static int gmc_v9_0_ecc_interrupt_state(struct amdgpu_device *adev, in gmc_v9_0_ecc_interrupt_state() argument
426 if (adev->asic_type >= CHIP_VEGA20) in gmc_v9_0_ecc_interrupt_state()
467 static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev, in gmc_v9_0_vm_fault_interrupt_state() argument
485 for (j = 0; j < adev->num_vmhubs; j++) { in gmc_v9_0_vm_fault_interrupt_state()
486 hub = &adev->vmhub[j]; in gmc_v9_0_vm_fault_interrupt_state()
496 for (j = 0; j < adev->num_vmhubs; j++) { in gmc_v9_0_vm_fault_interrupt_state()
497 hub = &adev->vmhub[j]; in gmc_v9_0_vm_fault_interrupt_state()
512 static int gmc_v9_0_process_interrupt(struct amdgpu_device *adev, in gmc_v9_0_process_interrupt() argument
526 if (retry_fault && amdgpu_gmc_filter_faults(adev, addr, entry->pasid, in gmc_v9_0_process_interrupt()
532 hub = &adev->vmhub[AMDGPU_MMHUB_0]; in gmc_v9_0_process_interrupt()
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| D | vi.c | 85 static u32 vi_pcie_rreg(struct amdgpu_device *adev, u32 reg) in vi_pcie_rreg() argument
90 spin_lock_irqsave(&adev->pcie_idx_lock, flags); in vi_pcie_rreg()
94 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); in vi_pcie_rreg()
98 static void vi_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v) in vi_pcie_wreg() argument
102 spin_lock_irqsave(&adev->pcie_idx_lock, flags); in vi_pcie_wreg()
107 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); in vi_pcie_wreg()
110 static u32 vi_smc_rreg(struct amdgpu_device *adev, u32 reg) in vi_smc_rreg() argument
115 spin_lock_irqsave(&adev->smc_idx_lock, flags); in vi_smc_rreg()
118 spin_unlock_irqrestore(&adev->smc_idx_lock, flags); in vi_smc_rreg()
122 static void vi_smc_wreg(struct amdgpu_device *adev, u32 reg, u32 v) in vi_smc_wreg() argument
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| D | amdgpu_virt.c | 40 bool amdgpu_virt_mmio_blocked(struct amdgpu_device *adev) in amdgpu_virt_mmio_blocked() argument
48 void amdgpu_virt_init_setting(struct amdgpu_device *adev) in amdgpu_virt_init_setting() argument
51 if (adev->mode_info.num_crtc == 0) in amdgpu_virt_init_setting()
52 adev->mode_info.num_crtc = 1; in amdgpu_virt_init_setting()
53 adev->enable_virtual_display = true; in amdgpu_virt_init_setting()
54 adev_to_drm(adev)->driver->driver_features &= ~DRIVER_ATOMIC; in amdgpu_virt_init_setting()
55 adev->cg_flags = 0; in amdgpu_virt_init_setting()
56 adev->pg_flags = 0; in amdgpu_virt_init_setting()
59 void amdgpu_virt_kiq_reg_write_reg_wait(struct amdgpu_device *adev, in amdgpu_virt_kiq_reg_write_reg_wait() argument
63 struct amdgpu_kiq *kiq = &adev->gfx.kiq; in amdgpu_virt_kiq_reg_write_reg_wait()
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| D | amdgpu_gfx.c | 38 int amdgpu_gfx_mec_queue_to_bit(struct amdgpu_device *adev, int mec, in amdgpu_gfx_mec_queue_to_bit() argument
43 bit += mec * adev->gfx.mec.num_pipe_per_mec in amdgpu_gfx_mec_queue_to_bit()
44 * adev->gfx.mec.num_queue_per_pipe; in amdgpu_gfx_mec_queue_to_bit()
45 bit += pipe * adev->gfx.mec.num_queue_per_pipe; in amdgpu_gfx_mec_queue_to_bit()
51 void amdgpu_queue_mask_bit_to_mec_queue(struct amdgpu_device *adev, int bit, in amdgpu_queue_mask_bit_to_mec_queue() argument
54 *queue = bit % adev->gfx.mec.num_queue_per_pipe; in amdgpu_queue_mask_bit_to_mec_queue()
55 *pipe = (bit / adev->gfx.mec.num_queue_per_pipe) in amdgpu_queue_mask_bit_to_mec_queue()
56 % adev->gfx.mec.num_pipe_per_mec; in amdgpu_queue_mask_bit_to_mec_queue()
57 *mec = (bit / adev->gfx.mec.num_queue_per_pipe) in amdgpu_queue_mask_bit_to_mec_queue()
58 / adev->gfx.mec.num_pipe_per_mec; in amdgpu_queue_mask_bit_to_mec_queue()
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| D | amdgpu_acp.c | 98 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in acp_sw_init() local
100 adev->acp.parent = adev->dev; in acp_sw_init()
102 adev->acp.cgs_device = in acp_sw_init()
103 amdgpu_cgs_create_device(adev); in acp_sw_init()
104 if (!adev->acp.cgs_device) in acp_sw_init()
112 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in acp_sw_fini() local
114 if (adev->acp.cgs_device) in acp_sw_fini()
115 amdgpu_cgs_destroy_device(adev->acp.cgs_device); in acp_sw_fini()
121 void *adev; member
128 struct amdgpu_device *adev; in acp_poweroff() local
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| D | amdgpu_rlc.c | 37 void amdgpu_gfx_rlc_enter_safe_mode(struct amdgpu_device *adev) in amdgpu_gfx_rlc_enter_safe_mode() argument
39 if (adev->gfx.rlc.in_safe_mode) in amdgpu_gfx_rlc_enter_safe_mode()
43 if (!adev->gfx.rlc.funcs->is_rlc_enabled(adev)) in amdgpu_gfx_rlc_enter_safe_mode()
46 if (adev->cg_flags & in amdgpu_gfx_rlc_enter_safe_mode()
49 adev->gfx.rlc.funcs->set_safe_mode(adev); in amdgpu_gfx_rlc_enter_safe_mode()
50 adev->gfx.rlc.in_safe_mode = true; in amdgpu_gfx_rlc_enter_safe_mode()
61 void amdgpu_gfx_rlc_exit_safe_mode(struct amdgpu_device *adev) in amdgpu_gfx_rlc_exit_safe_mode() argument
63 if (!(adev->gfx.rlc.in_safe_mode)) in amdgpu_gfx_rlc_exit_safe_mode()
67 if (!adev->gfx.rlc.funcs->is_rlc_enabled(adev)) in amdgpu_gfx_rlc_exit_safe_mode()
70 if (adev->cg_flags & in amdgpu_gfx_rlc_exit_safe_mode()
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| D | amdgpu_gart.c | 72 static int amdgpu_gart_dummy_page_init(struct amdgpu_device *adev) in amdgpu_gart_dummy_page_init() argument
76 if (adev->dummy_page_addr) in amdgpu_gart_dummy_page_init()
78 adev->dummy_page_addr = pci_map_page(adev->pdev, dummy_page, 0, in amdgpu_gart_dummy_page_init()
80 if (pci_dma_mapping_error(adev->pdev, adev->dummy_page_addr)) { in amdgpu_gart_dummy_page_init()
81 dev_err(&adev->pdev->dev, "Failed to DMA MAP the dummy page\n"); in amdgpu_gart_dummy_page_init()
82 adev->dummy_page_addr = 0; in amdgpu_gart_dummy_page_init()
95 static void amdgpu_gart_dummy_page_fini(struct amdgpu_device *adev) in amdgpu_gart_dummy_page_fini() argument
97 if (!adev->dummy_page_addr) in amdgpu_gart_dummy_page_fini()
99 pci_unmap_page(adev->pdev, adev->dummy_page_addr, in amdgpu_gart_dummy_page_fini()
101 adev->dummy_page_addr = 0; in amdgpu_gart_dummy_page_fini()
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| D | mxgpu_nv.c | 34 static void xgpu_nv_mailbox_send_ack(struct amdgpu_device *adev) in xgpu_nv_mailbox_send_ack() argument
39 static void xgpu_nv_mailbox_set_valid(struct amdgpu_device *adev, bool val) in xgpu_nv_mailbox_set_valid() argument
53 static enum idh_event xgpu_nv_mailbox_peek_msg(struct amdgpu_device *adev) in xgpu_nv_mailbox_peek_msg() argument
59 static int xgpu_nv_mailbox_rcv_msg(struct amdgpu_device *adev, in xgpu_nv_mailbox_rcv_msg() argument
68 xgpu_nv_mailbox_send_ack(adev); in xgpu_nv_mailbox_rcv_msg()
73 static uint8_t xgpu_nv_peek_ack(struct amdgpu_device *adev) in xgpu_nv_peek_ack() argument
78 static int xgpu_nv_poll_ack(struct amdgpu_device *adev) in xgpu_nv_poll_ack() argument
97 static int xgpu_nv_poll_msg(struct amdgpu_device *adev, enum idh_event event) in xgpu_nv_poll_msg() argument
102 r = xgpu_nv_mailbox_rcv_msg(adev, event); in xgpu_nv_poll_msg()
114 static void xgpu_nv_mailbox_trans_msg (struct amdgpu_device *adev, in xgpu_nv_mailbox_trans_msg() argument
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| D | amdgpu_amdkfd.c | 69 void amdgpu_amdkfd_device_probe(struct amdgpu_device *adev) in amdgpu_amdkfd_device_probe() argument
71 bool vf = amdgpu_sriov_vf(adev); in amdgpu_amdkfd_device_probe()
76 adev->kfd.dev = kgd2kfd_probe((struct kgd_dev *)adev, in amdgpu_amdkfd_device_probe()
77 adev->pdev, adev->asic_type, vf); in amdgpu_amdkfd_device_probe()
79 if (adev->kfd.dev) in amdgpu_amdkfd_device_probe()
80 amdgpu_amdkfd_total_mem_size += adev->gmc.real_vram_size; in amdgpu_amdkfd_device_probe()
96 static void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev, in amdgpu_doorbell_get_kfd_info() argument
105 if (adev->doorbell.size > adev->doorbell.num_doorbells * sizeof(u32)) { in amdgpu_doorbell_get_kfd_info()
106 *aperture_base = adev->doorbell.base; in amdgpu_doorbell_get_kfd_info()
107 *aperture_size = adev->doorbell.size; in amdgpu_doorbell_get_kfd_info()
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| D | amdgpu_irq.c | 86 struct amdgpu_device *adev = container_of(work, struct amdgpu_device, in amdgpu_hotplug_work_func() local
88 struct drm_device *dev = adev_to_drm(adev); in amdgpu_hotplug_work_func()
110 void amdgpu_irq_disable_all(struct amdgpu_device *adev) in amdgpu_irq_disable_all() argument
116 spin_lock_irqsave(&adev->irq.lock, irqflags); in amdgpu_irq_disable_all()
118 if (!adev->irq.client[i].sources) in amdgpu_irq_disable_all()
122 struct amdgpu_irq_src *src = adev->irq.client[i].sources[j]; in amdgpu_irq_disable_all()
129 r = src->funcs->set(adev, src, k, in amdgpu_irq_disable_all()
137 spin_unlock_irqrestore(&adev->irq.lock, irqflags); in amdgpu_irq_disable_all()
154 struct amdgpu_device *adev = drm_to_adev(dev); in amdgpu_irq_handler() local
157 ret = amdgpu_ih_process(adev, &adev->irq.ih); in amdgpu_irq_handler()
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| D | vega20_reg_init.c | 29 int vega20_reg_base_init(struct amdgpu_device *adev) in vega20_reg_base_init() argument
34 adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); in vega20_reg_base_init()
35 adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i])); in vega20_reg_base_init()
36 adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i])); in vega20_reg_base_init()
37 adev->reg_offset[ATHUB_HWIP][i] = (uint32_t *)(&(ATHUB_BASE.instance[i])); in vega20_reg_base_init()
38 adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i])); in vega20_reg_base_init()
39 adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i])); in vega20_reg_base_init()
40 adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i])); in vega20_reg_base_init()
41 adev->reg_offset[UVD_HWIP][i] = (uint32_t *)(&(UVD_BASE.instance[i])); in vega20_reg_base_init()
42 adev->reg_offset[VCE_HWIP][i] = (uint32_t *)(&(VCE_BASE.instance[i])); in vega20_reg_base_init()
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| D | amdgpu_debugfs.c | 47 int amdgpu_debugfs_add_files(struct amdgpu_device *adev, in amdgpu_debugfs_add_files() argument
53 for (i = 0; i < adev->debugfs_count; i++) { in amdgpu_debugfs_add_files()
54 if (adev->debugfs[i].files == files) { in amdgpu_debugfs_add_files()
60 i = adev->debugfs_count + 1; in amdgpu_debugfs_add_files()
67 adev->debugfs[adev->debugfs_count].files = files; in amdgpu_debugfs_add_files()
68 adev->debugfs[adev->debugfs_count].num_files = nfiles; in amdgpu_debugfs_add_files()
69 adev->debugfs_count = i; in amdgpu_debugfs_add_files()
72 adev_to_drm(adev)->primary->debugfs_root, in amdgpu_debugfs_add_files()
73 adev_to_drm(adev)->primary); in amdgpu_debugfs_add_files()
78 int amdgpu_debugfs_wait_dump(struct amdgpu_device *adev) in amdgpu_debugfs_wait_dump() argument
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| D | gmc_v6_0.c | 44 static void gmc_v6_0_set_gmc_funcs(struct amdgpu_device *adev);
45 static void gmc_v6_0_set_irq_funcs(struct amdgpu_device *adev);
64 static void gmc_v6_0_mc_stop(struct amdgpu_device *adev) in gmc_v6_0_mc_stop() argument
68 gmc_v6_0_wait_for_idle((void *)adev); in gmc_v6_0_mc_stop()
84 static void gmc_v6_0_mc_resume(struct amdgpu_device *adev) in gmc_v6_0_mc_resume() argument
98 static int gmc_v6_0_init_microcode(struct amdgpu_device *adev) in gmc_v6_0_init_microcode() argument
107 switch (adev->asic_type) { in gmc_v6_0_init_microcode()
134 err = request_firmware(&adev->gmc.fw, fw_name, adev->dev); in gmc_v6_0_init_microcode()
138 err = amdgpu_ucode_validate(adev->gmc.fw); in gmc_v6_0_init_microcode()
142 dev_err(adev->dev, in gmc_v6_0_init_microcode()
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| D | amdgpu_bios.c | 90 static bool igp_read_bios_from_vram(struct amdgpu_device *adev) in igp_read_bios_from_vram() argument
96 if (!(adev->flags & AMD_IS_APU)) in igp_read_bios_from_vram()
97 if (amdgpu_device_need_post(adev)) in igp_read_bios_from_vram()
100 adev->bios = NULL; in igp_read_bios_from_vram()
101 vram_base = pci_resource_start(adev->pdev, 0); in igp_read_bios_from_vram()
107 adev->bios = kmalloc(size, GFP_KERNEL); in igp_read_bios_from_vram()
108 if (!adev->bios) { in igp_read_bios_from_vram()
112 adev->bios_size = size; in igp_read_bios_from_vram()
113 memcpy_fromio(adev->bios, bios, size); in igp_read_bios_from_vram()
116 if (!check_atom_bios(adev->bios, size)) { in igp_read_bios_from_vram()
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| D | amdgpu_cgs.c | 36 struct amdgpu_device *adev; member
40 struct amdgpu_device *adev = \
41 ((struct amdgpu_cgs_device *)cgs_device)->adev
142 if (adev->asic_type >= CHIP_TOPAZ) in fw_type_convert()
167 fw_version = adev->sdma.instance[0].fw_version; in amdgpu_get_firmware_version()
170 fw_version = adev->sdma.instance[1].fw_version; in amdgpu_get_firmware_version()
173 fw_version = adev->gfx.ce_fw_version; in amdgpu_get_firmware_version()
176 fw_version = adev->gfx.pfp_fw_version; in amdgpu_get_firmware_version()
179 fw_version = adev->gfx.me_fw_version; in amdgpu_get_firmware_version()
182 fw_version = adev->gfx.mec_fw_version; in amdgpu_get_firmware_version()
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| D | amdgpu_umc.c | 26 int amdgpu_umc_ras_late_init(struct amdgpu_device *adev) in amdgpu_umc_ras_late_init() argument
36 if (!adev->umc.ras_if) { in amdgpu_umc_ras_late_init()
37 adev->umc.ras_if = in amdgpu_umc_ras_late_init()
39 if (!adev->umc.ras_if) in amdgpu_umc_ras_late_init()
41 adev->umc.ras_if->block = AMDGPU_RAS_BLOCK__UMC; in amdgpu_umc_ras_late_init()
42 adev->umc.ras_if->type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE; in amdgpu_umc_ras_late_init()
43 adev->umc.ras_if->sub_block_index = 0; in amdgpu_umc_ras_late_init()
44 strcpy(adev->umc.ras_if->name, "umc"); in amdgpu_umc_ras_late_init()
46 ih_info.head = fs_info.head = *adev->umc.ras_if; in amdgpu_umc_ras_late_init()
48 r = amdgpu_ras_late_init(adev, adev->umc.ras_if, in amdgpu_umc_ras_late_init()
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| D | vega10_reg_init.c | 29 int vega10_reg_base_init(struct amdgpu_device *adev) in vega10_reg_base_init() argument
34 adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); in vega10_reg_base_init()
35 adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i])); in vega10_reg_base_init()
36 adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i])); in vega10_reg_base_init()
37 adev->reg_offset[ATHUB_HWIP][i] = (uint32_t *)(&(ATHUB_BASE.instance[i])); in vega10_reg_base_init()
38 adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i])); in vega10_reg_base_init()
39 adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i])); in vega10_reg_base_init()
40 adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i])); in vega10_reg_base_init()
41 adev->reg_offset[UVD_HWIP][i] = (uint32_t *)(&(UVD_BASE.instance[i])); in vega10_reg_base_init()
42 adev->reg_offset[VCE_HWIP][i] = (uint32_t *)(&(VCE_BASE.instance[i])); in vega10_reg_base_init()
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| D | mxgpu_ai.c | 35 static void xgpu_ai_mailbox_send_ack(struct amdgpu_device *adev) in xgpu_ai_mailbox_send_ack() argument
40 static void xgpu_ai_mailbox_set_valid(struct amdgpu_device *adev, bool val) in xgpu_ai_mailbox_set_valid() argument
54 static enum idh_event xgpu_ai_mailbox_peek_msg(struct amdgpu_device *adev) in xgpu_ai_mailbox_peek_msg() argument
61 static int xgpu_ai_mailbox_rcv_msg(struct amdgpu_device *adev, in xgpu_ai_mailbox_rcv_msg() argument
71 xgpu_ai_mailbox_send_ack(adev); in xgpu_ai_mailbox_rcv_msg()
76 static uint8_t xgpu_ai_peek_ack(struct amdgpu_device *adev) { in xgpu_ai_peek_ack() argument
80 static int xgpu_ai_poll_ack(struct amdgpu_device *adev) in xgpu_ai_poll_ack() argument
99 static int xgpu_ai_poll_msg(struct amdgpu_device *adev, enum idh_event event) in xgpu_ai_poll_msg() argument
104 r = xgpu_ai_mailbox_rcv_msg(adev, event); in xgpu_ai_poll_msg()
117 static void xgpu_ai_mailbox_trans_msg (struct amdgpu_device *adev, in xgpu_ai_mailbox_trans_msg() argument
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| /Linux-v5.10/drivers/gpu/drm/amd/pm/inc/ |
| D | amdgpu_dpm.h | 256 #define amdgpu_dpm_pre_set_power_state(adev) \ argument
257 ((adev)->powerplay.pp_funcs->pre_set_power_state((adev)->powerplay.pp_handle))
259 #define amdgpu_dpm_set_power_state(adev) \ argument
260 ((adev)->powerplay.pp_funcs->set_power_state((adev)->powerplay.pp_handle))
262 #define amdgpu_dpm_post_set_power_state(adev) \ argument
263 ((adev)->powerplay.pp_funcs->post_set_power_state((adev)->powerplay.pp_handle))
265 #define amdgpu_dpm_display_configuration_changed(adev) \ argument
266 ((adev)->powerplay.pp_funcs->display_configuration_changed((adev)->powerplay.pp_handle))
268 #define amdgpu_dpm_print_power_state(adev, ps) \ argument
269 ((adev)->powerplay.pp_funcs->print_power_state((adev)->powerplay.pp_handle, (ps)))
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| /Linux-v5.10/drivers/gpu/drm/amd/pm/ |
| D | amdgpu_dpm.c | 110 void amdgpu_dpm_print_ps_status(struct amdgpu_device *adev, in amdgpu_dpm_print_ps_status() argument
114 if (rps == adev->pm.dpm.current_ps) in amdgpu_dpm_print_ps_status()
116 if (rps == adev->pm.dpm.requested_ps) in amdgpu_dpm_print_ps_status()
118 if (rps == adev->pm.dpm.boot_ps) in amdgpu_dpm_print_ps_status()
123 void amdgpu_dpm_get_active_displays(struct amdgpu_device *adev) in amdgpu_dpm_get_active_displays() argument
125 struct drm_device *ddev = adev_to_drm(adev); in amdgpu_dpm_get_active_displays()
129 adev->pm.dpm.new_active_crtcs = 0; in amdgpu_dpm_get_active_displays()
130 adev->pm.dpm.new_active_crtc_count = 0; in amdgpu_dpm_get_active_displays()
131 if (adev->mode_info.num_crtc && adev->mode_info.mode_config_initialized) { in amdgpu_dpm_get_active_displays()
136 adev->pm.dpm.new_active_crtcs |= (1 << amdgpu_crtc->crtc_id); in amdgpu_dpm_get_active_displays()
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| /Linux-v5.10/drivers/gpu/drm/amd/pm/powerplay/ |
| D | kv_dpm.c | 46 static void kv_dpm_set_irq_funcs(struct amdgpu_device *adev);
47 static int kv_enable_nb_dpm(struct amdgpu_device *adev,
49 static void kv_init_graphics_levels(struct amdgpu_device *adev);
50 static int kv_calculate_ds_divider(struct amdgpu_device *adev);
51 static int kv_calculate_nbps_level_settings(struct amdgpu_device *adev);
52 static int kv_calculate_dpm_settings(struct amdgpu_device *adev);
53 static void kv_enable_new_levels(struct amdgpu_device *adev);
54 static void kv_program_nbps_index_settings(struct amdgpu_device *adev,
56 static int kv_set_enabled_level(struct amdgpu_device *adev, u32 level);
57 static int kv_set_enabled_levels(struct amdgpu_device *adev);
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