1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 #ifndef _ASM_POWERPC_IO_H
3 #define _ASM_POWERPC_IO_H
4 #ifdef __KERNEL__
5
6 #define ARCH_HAS_IOREMAP_WC
7 #ifdef CONFIG_PPC32
8 #define ARCH_HAS_IOREMAP_WT
9 #endif
10
11 /*
12 */
13
14 /* Check of existence of legacy devices */
15 extern int check_legacy_ioport(unsigned long base_port);
16 #define I8042_DATA_REG 0x60
17 #define FDC_BASE 0x3f0
18
19 #if defined(CONFIG_PPC64) && defined(CONFIG_PCI)
20 extern struct pci_dev *isa_bridge_pcidev;
21 /*
22 * has legacy ISA devices ?
23 */
24 #define arch_has_dev_port() (isa_bridge_pcidev != NULL || isa_io_special)
25 #endif
26
27 #include <linux/device.h>
28 #include <linux/compiler.h>
29 #include <linux/mm.h>
30 #include <asm/page.h>
31 #include <asm/byteorder.h>
32 #include <asm/synch.h>
33 #include <asm/delay.h>
34 #include <asm/mmiowb.h>
35 #include <asm/mmu.h>
36 #include <asm/ppc_asm.h>
37
38 #define SIO_CONFIG_RA 0x398
39 #define SIO_CONFIG_RD 0x399
40
41 #define SLOW_DOWN_IO
42
43 /* 32 bits uses slightly different variables for the various IO
44 * bases. Most of this file only uses _IO_BASE though which we
45 * define properly based on the platform
46 */
47 #ifndef CONFIG_PCI
48 #define _IO_BASE 0
49 #define _ISA_MEM_BASE 0
50 #define PCI_DRAM_OFFSET 0
51 #elif defined(CONFIG_PPC32)
52 #define _IO_BASE isa_io_base
53 #define _ISA_MEM_BASE isa_mem_base
54 #define PCI_DRAM_OFFSET pci_dram_offset
55 #else
56 #define _IO_BASE pci_io_base
57 #define _ISA_MEM_BASE isa_mem_base
58 #define PCI_DRAM_OFFSET 0
59 #endif
60
61 extern unsigned long isa_io_base;
62 extern unsigned long pci_io_base;
63 extern unsigned long pci_dram_offset;
64
65 extern resource_size_t isa_mem_base;
66
67 /* Boolean set by platform if PIO accesses are suppored while _IO_BASE
68 * is not set or addresses cannot be translated to MMIO. This is typically
69 * set when the platform supports "special" PIO accesses via a non memory
70 * mapped mechanism, and allows things like the early udbg UART code to
71 * function.
72 */
73 extern bool isa_io_special;
74
75 #ifdef CONFIG_PPC32
76 #if defined(CONFIG_PPC_INDIRECT_PIO) || defined(CONFIG_PPC_INDIRECT_MMIO)
77 #error CONFIG_PPC_INDIRECT_{PIO,MMIO} are not yet supported on 32 bits
78 #endif
79 #endif
80
81 /*
82 *
83 * Low level MMIO accessors
84 *
85 * This provides the non-bus specific accessors to MMIO. Those are PowerPC
86 * specific and thus shouldn't be used in generic code. The accessors
87 * provided here are:
88 *
89 * in_8, in_le16, in_be16, in_le32, in_be32, in_le64, in_be64
90 * out_8, out_le16, out_be16, out_le32, out_be32, out_le64, out_be64
91 * _insb, _insw_ns, _insl_ns, _outsb, _outsw_ns, _outsl_ns
92 *
93 * Those operate directly on a kernel virtual address. Note that the prototype
94 * for the out_* accessors has the arguments in opposite order from the usual
95 * linux PCI accessors. Unlike those, they take the address first and the value
96 * next.
97 *
98 * Note: I might drop the _ns suffix on the stream operations soon as it is
99 * simply normal for stream operations to not swap in the first place.
100 *
101 */
102
103 #define DEF_MMIO_IN_X(name, size, insn) \
104 static inline u##size name(const volatile u##size __iomem *addr) \
105 { \
106 u##size ret; \
107 __asm__ __volatile__("sync;"#insn" %0,%y1;twi 0,%0,0;isync" \
108 : "=r" (ret) : "Z" (*addr) : "memory"); \
109 return ret; \
110 }
111
112 #define DEF_MMIO_OUT_X(name, size, insn) \
113 static inline void name(volatile u##size __iomem *addr, u##size val) \
114 { \
115 __asm__ __volatile__("sync;"#insn" %1,%y0" \
116 : "=Z" (*addr) : "r" (val) : "memory"); \
117 mmiowb_set_pending(); \
118 }
119
120 #define DEF_MMIO_IN_D(name, size, insn) \
121 static inline u##size name(const volatile u##size __iomem *addr) \
122 { \
123 u##size ret; \
124 __asm__ __volatile__("sync;"#insn"%U1%X1 %0,%1;twi 0,%0,0;isync"\
125 : "=r" (ret) : "m" (*addr) : "memory"); \
126 return ret; \
127 }
128
129 #define DEF_MMIO_OUT_D(name, size, insn) \
130 static inline void name(volatile u##size __iomem *addr, u##size val) \
131 { \
132 __asm__ __volatile__("sync;"#insn"%U0%X0 %1,%0" \
133 : "=m" (*addr) : "r" (val) : "memory"); \
134 mmiowb_set_pending(); \
135 }
136
137 DEF_MMIO_IN_D(in_8, 8, lbz);
138 DEF_MMIO_OUT_D(out_8, 8, stb);
139
140 #ifdef __BIG_ENDIAN__
141 DEF_MMIO_IN_D(in_be16, 16, lhz);
142 DEF_MMIO_IN_D(in_be32, 32, lwz);
143 DEF_MMIO_IN_X(in_le16, 16, lhbrx);
144 DEF_MMIO_IN_X(in_le32, 32, lwbrx);
145
146 DEF_MMIO_OUT_D(out_be16, 16, sth);
147 DEF_MMIO_OUT_D(out_be32, 32, stw);
148 DEF_MMIO_OUT_X(out_le16, 16, sthbrx);
149 DEF_MMIO_OUT_X(out_le32, 32, stwbrx);
150 #else
151 DEF_MMIO_IN_X(in_be16, 16, lhbrx);
152 DEF_MMIO_IN_X(in_be32, 32, lwbrx);
153 DEF_MMIO_IN_D(in_le16, 16, lhz);
154 DEF_MMIO_IN_D(in_le32, 32, lwz);
155
156 DEF_MMIO_OUT_X(out_be16, 16, sthbrx);
157 DEF_MMIO_OUT_X(out_be32, 32, stwbrx);
158 DEF_MMIO_OUT_D(out_le16, 16, sth);
159 DEF_MMIO_OUT_D(out_le32, 32, stw);
160
161 #endif /* __BIG_ENDIAN */
162
163 #ifdef __powerpc64__
164
165 #ifdef __BIG_ENDIAN__
166 DEF_MMIO_OUT_D(out_be64, 64, std);
167 DEF_MMIO_IN_D(in_be64, 64, ld);
168
169 /* There is no asm instructions for 64 bits reverse loads and stores */
in_le64(const volatile u64 __iomem * addr)170 static inline u64 in_le64(const volatile u64 __iomem *addr)
171 {
172 return swab64(in_be64(addr));
173 }
174
out_le64(volatile u64 __iomem * addr,u64 val)175 static inline void out_le64(volatile u64 __iomem *addr, u64 val)
176 {
177 out_be64(addr, swab64(val));
178 }
179 #else
180 DEF_MMIO_OUT_D(out_le64, 64, std);
181 DEF_MMIO_IN_D(in_le64, 64, ld);
182
183 /* There is no asm instructions for 64 bits reverse loads and stores */
in_be64(const volatile u64 __iomem * addr)184 static inline u64 in_be64(const volatile u64 __iomem *addr)
185 {
186 return swab64(in_le64(addr));
187 }
188
out_be64(volatile u64 __iomem * addr,u64 val)189 static inline void out_be64(volatile u64 __iomem *addr, u64 val)
190 {
191 out_le64(addr, swab64(val));
192 }
193
194 #endif
195 #endif /* __powerpc64__ */
196
197 /*
198 * Low level IO stream instructions are defined out of line for now
199 */
200 extern void _insb(const volatile u8 __iomem *addr, void *buf, long count);
201 extern void _outsb(volatile u8 __iomem *addr,const void *buf,long count);
202 extern void _insw_ns(const volatile u16 __iomem *addr, void *buf, long count);
203 extern void _outsw_ns(volatile u16 __iomem *addr, const void *buf, long count);
204 extern void _insl_ns(const volatile u32 __iomem *addr, void *buf, long count);
205 extern void _outsl_ns(volatile u32 __iomem *addr, const void *buf, long count);
206
207 /* The _ns naming is historical and will be removed. For now, just #define
208 * the non _ns equivalent names
209 */
210 #define _insw _insw_ns
211 #define _insl _insl_ns
212 #define _outsw _outsw_ns
213 #define _outsl _outsl_ns
214
215
216 /*
217 * memset_io, memcpy_toio, memcpy_fromio base implementations are out of line
218 */
219
220 extern void _memset_io(volatile void __iomem *addr, int c, unsigned long n);
221 extern void _memcpy_fromio(void *dest, const volatile void __iomem *src,
222 unsigned long n);
223 extern void _memcpy_toio(volatile void __iomem *dest, const void *src,
224 unsigned long n);
225
226 /*
227 *
228 * PCI and standard ISA accessors
229 *
230 * Those are globally defined linux accessors for devices on PCI or ISA
231 * busses. They follow the Linux defined semantics. The current implementation
232 * for PowerPC is as close as possible to the x86 version of these, and thus
233 * provides fairly heavy weight barriers for the non-raw versions
234 *
235 * In addition, they support a hook mechanism when CONFIG_PPC_INDIRECT_MMIO
236 * or CONFIG_PPC_INDIRECT_PIO are set allowing the platform to provide its
237 * own implementation of some or all of the accessors.
238 */
239
240 /*
241 * Include the EEH definitions when EEH is enabled only so they don't get
242 * in the way when building for 32 bits
243 */
244 #ifdef CONFIG_EEH
245 #include <asm/eeh.h>
246 #endif
247
248 /* Shortcut to the MMIO argument pointer */
249 #define PCI_IO_ADDR volatile void __iomem *
250
251 /* Indirect IO address tokens:
252 *
253 * When CONFIG_PPC_INDIRECT_MMIO is set, the platform can provide hooks
254 * on all MMIOs. (Note that this is all 64 bits only for now)
255 *
256 * To help platforms who may need to differentiate MMIO addresses in
257 * their hooks, a bitfield is reserved for use by the platform near the
258 * top of MMIO addresses (not PIO, those have to cope the hard way).
259 *
260 * The highest address in the kernel virtual space are:
261 *
262 * d0003fffffffffff # with Hash MMU
263 * c00fffffffffffff # with Radix MMU
264 *
265 * The top 4 bits are reserved as the region ID on hash, leaving us 8 bits
266 * that can be used for the field.
267 *
268 * The direct IO mapping operations will then mask off those bits
269 * before doing the actual access, though that only happen when
270 * CONFIG_PPC_INDIRECT_MMIO is set, thus be careful when you use that
271 * mechanism
272 *
273 * For PIO, there is a separate CONFIG_PPC_INDIRECT_PIO which makes
274 * all PIO functions call through a hook.
275 */
276
277 #ifdef CONFIG_PPC_INDIRECT_MMIO
278 #define PCI_IO_IND_TOKEN_SHIFT 52
279 #define PCI_IO_IND_TOKEN_MASK (0xfful << PCI_IO_IND_TOKEN_SHIFT)
280 #define PCI_FIX_ADDR(addr) \
281 ((PCI_IO_ADDR)(((unsigned long)(addr)) & ~PCI_IO_IND_TOKEN_MASK))
282 #define PCI_GET_ADDR_TOKEN(addr) \
283 (((unsigned long)(addr) & PCI_IO_IND_TOKEN_MASK) >> \
284 PCI_IO_IND_TOKEN_SHIFT)
285 #define PCI_SET_ADDR_TOKEN(addr, token) \
286 do { \
287 unsigned long __a = (unsigned long)(addr); \
288 __a &= ~PCI_IO_IND_TOKEN_MASK; \
289 __a |= ((unsigned long)(token)) << PCI_IO_IND_TOKEN_SHIFT; \
290 (addr) = (void __iomem *)__a; \
291 } while(0)
292 #else
293 #define PCI_FIX_ADDR(addr) (addr)
294 #endif
295
296
297 /*
298 * Non ordered and non-swapping "raw" accessors
299 */
300
__raw_readb(const volatile void __iomem * addr)301 static inline unsigned char __raw_readb(const volatile void __iomem *addr)
302 {
303 return *(volatile unsigned char __force *)PCI_FIX_ADDR(addr);
304 }
__raw_readw(const volatile void __iomem * addr)305 static inline unsigned short __raw_readw(const volatile void __iomem *addr)
306 {
307 return *(volatile unsigned short __force *)PCI_FIX_ADDR(addr);
308 }
__raw_readl(const volatile void __iomem * addr)309 static inline unsigned int __raw_readl(const volatile void __iomem *addr)
310 {
311 return *(volatile unsigned int __force *)PCI_FIX_ADDR(addr);
312 }
__raw_writeb(unsigned char v,volatile void __iomem * addr)313 static inline void __raw_writeb(unsigned char v, volatile void __iomem *addr)
314 {
315 *(volatile unsigned char __force *)PCI_FIX_ADDR(addr) = v;
316 }
__raw_writew(unsigned short v,volatile void __iomem * addr)317 static inline void __raw_writew(unsigned short v, volatile void __iomem *addr)
318 {
319 *(volatile unsigned short __force *)PCI_FIX_ADDR(addr) = v;
320 }
__raw_writel(unsigned int v,volatile void __iomem * addr)321 static inline void __raw_writel(unsigned int v, volatile void __iomem *addr)
322 {
323 *(volatile unsigned int __force *)PCI_FIX_ADDR(addr) = v;
324 }
325
326 #ifdef __powerpc64__
__raw_readq(const volatile void __iomem * addr)327 static inline unsigned long __raw_readq(const volatile void __iomem *addr)
328 {
329 return *(volatile unsigned long __force *)PCI_FIX_ADDR(addr);
330 }
__raw_writeq(unsigned long v,volatile void __iomem * addr)331 static inline void __raw_writeq(unsigned long v, volatile void __iomem *addr)
332 {
333 *(volatile unsigned long __force *)PCI_FIX_ADDR(addr) = v;
334 }
335
__raw_writeq_be(unsigned long v,volatile void __iomem * addr)336 static inline void __raw_writeq_be(unsigned long v, volatile void __iomem *addr)
337 {
338 __raw_writeq((__force unsigned long)cpu_to_be64(v), addr);
339 }
340
341 /*
342 * Real mode versions of the above. Those instructions are only supposed
343 * to be used in hypervisor real mode as per the architecture spec.
344 */
__raw_rm_writeb(u8 val,volatile void __iomem * paddr)345 static inline void __raw_rm_writeb(u8 val, volatile void __iomem *paddr)
346 {
347 __asm__ __volatile__("stbcix %0,0,%1"
348 : : "r" (val), "r" (paddr) : "memory");
349 }
350
__raw_rm_writew(u16 val,volatile void __iomem * paddr)351 static inline void __raw_rm_writew(u16 val, volatile void __iomem *paddr)
352 {
353 __asm__ __volatile__("sthcix %0,0,%1"
354 : : "r" (val), "r" (paddr) : "memory");
355 }
356
__raw_rm_writel(u32 val,volatile void __iomem * paddr)357 static inline void __raw_rm_writel(u32 val, volatile void __iomem *paddr)
358 {
359 __asm__ __volatile__("stwcix %0,0,%1"
360 : : "r" (val), "r" (paddr) : "memory");
361 }
362
__raw_rm_writeq(u64 val,volatile void __iomem * paddr)363 static inline void __raw_rm_writeq(u64 val, volatile void __iomem *paddr)
364 {
365 __asm__ __volatile__("stdcix %0,0,%1"
366 : : "r" (val), "r" (paddr) : "memory");
367 }
368
__raw_rm_writeq_be(u64 val,volatile void __iomem * paddr)369 static inline void __raw_rm_writeq_be(u64 val, volatile void __iomem *paddr)
370 {
371 __raw_rm_writeq((__force u64)cpu_to_be64(val), paddr);
372 }
373
__raw_rm_readb(volatile void __iomem * paddr)374 static inline u8 __raw_rm_readb(volatile void __iomem *paddr)
375 {
376 u8 ret;
377 __asm__ __volatile__("lbzcix %0,0, %1"
378 : "=r" (ret) : "r" (paddr) : "memory");
379 return ret;
380 }
381
__raw_rm_readw(volatile void __iomem * paddr)382 static inline u16 __raw_rm_readw(volatile void __iomem *paddr)
383 {
384 u16 ret;
385 __asm__ __volatile__("lhzcix %0,0, %1"
386 : "=r" (ret) : "r" (paddr) : "memory");
387 return ret;
388 }
389
__raw_rm_readl(volatile void __iomem * paddr)390 static inline u32 __raw_rm_readl(volatile void __iomem *paddr)
391 {
392 u32 ret;
393 __asm__ __volatile__("lwzcix %0,0, %1"
394 : "=r" (ret) : "r" (paddr) : "memory");
395 return ret;
396 }
397
__raw_rm_readq(volatile void __iomem * paddr)398 static inline u64 __raw_rm_readq(volatile void __iomem *paddr)
399 {
400 u64 ret;
401 __asm__ __volatile__("ldcix %0,0, %1"
402 : "=r" (ret) : "r" (paddr) : "memory");
403 return ret;
404 }
405 #endif /* __powerpc64__ */
406
407 /*
408 *
409 * PCI PIO and MMIO accessors.
410 *
411 *
412 * On 32 bits, PIO operations have a recovery mechanism in case they trigger
413 * machine checks (which they occasionally do when probing non existing
414 * IO ports on some platforms, like PowerMac and 8xx).
415 * I always found it to be of dubious reliability and I am tempted to get
416 * rid of it one of these days. So if you think it's important to keep it,
417 * please voice up asap. We never had it for 64 bits and I do not intend
418 * to port it over
419 */
420
421 #ifdef CONFIG_PPC32
422
423 #define __do_in_asm(name, op) \
424 static inline unsigned int name(unsigned int port) \
425 { \
426 unsigned int x; \
427 __asm__ __volatile__( \
428 "sync\n" \
429 "0:" op " %0,0,%1\n" \
430 "1: twi 0,%0,0\n" \
431 "2: isync\n" \
432 "3: nop\n" \
433 "4:\n" \
434 ".section .fixup,\"ax\"\n" \
435 "5: li %0,-1\n" \
436 " b 4b\n" \
437 ".previous\n" \
438 EX_TABLE(0b, 5b) \
439 EX_TABLE(1b, 5b) \
440 EX_TABLE(2b, 5b) \
441 EX_TABLE(3b, 5b) \
442 : "=&r" (x) \
443 : "r" (port + _IO_BASE) \
444 : "memory"); \
445 return x; \
446 }
447
448 #define __do_out_asm(name, op) \
449 static inline void name(unsigned int val, unsigned int port) \
450 { \
451 __asm__ __volatile__( \
452 "sync\n" \
453 "0:" op " %0,0,%1\n" \
454 "1: sync\n" \
455 "2:\n" \
456 EX_TABLE(0b, 2b) \
457 EX_TABLE(1b, 2b) \
458 : : "r" (val), "r" (port + _IO_BASE) \
459 : "memory"); \
460 }
461
462 __do_in_asm(_rec_inb, "lbzx")
463 __do_in_asm(_rec_inw, "lhbrx")
464 __do_in_asm(_rec_inl, "lwbrx")
465 __do_out_asm(_rec_outb, "stbx")
466 __do_out_asm(_rec_outw, "sthbrx")
467 __do_out_asm(_rec_outl, "stwbrx")
468
469 #endif /* CONFIG_PPC32 */
470
471 /* The "__do_*" operations below provide the actual "base" implementation
472 * for each of the defined accessors. Some of them use the out_* functions
473 * directly, some of them still use EEH, though we might change that in the
474 * future. Those macros below provide the necessary argument swapping and
475 * handling of the IO base for PIO.
476 *
477 * They are themselves used by the macros that define the actual accessors
478 * and can be used by the hooks if any.
479 *
480 * Note that PIO operations are always defined in terms of their corresonding
481 * MMIO operations. That allows platforms like iSeries who want to modify the
482 * behaviour of both to only hook on the MMIO version and get both. It's also
483 * possible to hook directly at the toplevel PIO operation if they have to
484 * be handled differently
485 */
486 #define __do_writeb(val, addr) out_8(PCI_FIX_ADDR(addr), val)
487 #define __do_writew(val, addr) out_le16(PCI_FIX_ADDR(addr), val)
488 #define __do_writel(val, addr) out_le32(PCI_FIX_ADDR(addr), val)
489 #define __do_writeq(val, addr) out_le64(PCI_FIX_ADDR(addr), val)
490 #define __do_writew_be(val, addr) out_be16(PCI_FIX_ADDR(addr), val)
491 #define __do_writel_be(val, addr) out_be32(PCI_FIX_ADDR(addr), val)
492 #define __do_writeq_be(val, addr) out_be64(PCI_FIX_ADDR(addr), val)
493
494 #ifdef CONFIG_EEH
495 #define __do_readb(addr) eeh_readb(PCI_FIX_ADDR(addr))
496 #define __do_readw(addr) eeh_readw(PCI_FIX_ADDR(addr))
497 #define __do_readl(addr) eeh_readl(PCI_FIX_ADDR(addr))
498 #define __do_readq(addr) eeh_readq(PCI_FIX_ADDR(addr))
499 #define __do_readw_be(addr) eeh_readw_be(PCI_FIX_ADDR(addr))
500 #define __do_readl_be(addr) eeh_readl_be(PCI_FIX_ADDR(addr))
501 #define __do_readq_be(addr) eeh_readq_be(PCI_FIX_ADDR(addr))
502 #else /* CONFIG_EEH */
503 #define __do_readb(addr) in_8(PCI_FIX_ADDR(addr))
504 #define __do_readw(addr) in_le16(PCI_FIX_ADDR(addr))
505 #define __do_readl(addr) in_le32(PCI_FIX_ADDR(addr))
506 #define __do_readq(addr) in_le64(PCI_FIX_ADDR(addr))
507 #define __do_readw_be(addr) in_be16(PCI_FIX_ADDR(addr))
508 #define __do_readl_be(addr) in_be32(PCI_FIX_ADDR(addr))
509 #define __do_readq_be(addr) in_be64(PCI_FIX_ADDR(addr))
510 #endif /* !defined(CONFIG_EEH) */
511
512 #ifdef CONFIG_PPC32
513 #define __do_outb(val, port) _rec_outb(val, port)
514 #define __do_outw(val, port) _rec_outw(val, port)
515 #define __do_outl(val, port) _rec_outl(val, port)
516 #define __do_inb(port) _rec_inb(port)
517 #define __do_inw(port) _rec_inw(port)
518 #define __do_inl(port) _rec_inl(port)
519 #else /* CONFIG_PPC32 */
520 #define __do_outb(val, port) writeb(val,(PCI_IO_ADDR)_IO_BASE+port);
521 #define __do_outw(val, port) writew(val,(PCI_IO_ADDR)_IO_BASE+port);
522 #define __do_outl(val, port) writel(val,(PCI_IO_ADDR)_IO_BASE+port);
523 #define __do_inb(port) readb((PCI_IO_ADDR)_IO_BASE + port);
524 #define __do_inw(port) readw((PCI_IO_ADDR)_IO_BASE + port);
525 #define __do_inl(port) readl((PCI_IO_ADDR)_IO_BASE + port);
526 #endif /* !CONFIG_PPC32 */
527
528 #ifdef CONFIG_EEH
529 #define __do_readsb(a, b, n) eeh_readsb(PCI_FIX_ADDR(a), (b), (n))
530 #define __do_readsw(a, b, n) eeh_readsw(PCI_FIX_ADDR(a), (b), (n))
531 #define __do_readsl(a, b, n) eeh_readsl(PCI_FIX_ADDR(a), (b), (n))
532 #else /* CONFIG_EEH */
533 #define __do_readsb(a, b, n) _insb(PCI_FIX_ADDR(a), (b), (n))
534 #define __do_readsw(a, b, n) _insw(PCI_FIX_ADDR(a), (b), (n))
535 #define __do_readsl(a, b, n) _insl(PCI_FIX_ADDR(a), (b), (n))
536 #endif /* !CONFIG_EEH */
537 #define __do_writesb(a, b, n) _outsb(PCI_FIX_ADDR(a),(b),(n))
538 #define __do_writesw(a, b, n) _outsw(PCI_FIX_ADDR(a),(b),(n))
539 #define __do_writesl(a, b, n) _outsl(PCI_FIX_ADDR(a),(b),(n))
540
541 #define __do_insb(p, b, n) readsb((PCI_IO_ADDR)_IO_BASE+(p), (b), (n))
542 #define __do_insw(p, b, n) readsw((PCI_IO_ADDR)_IO_BASE+(p), (b), (n))
543 #define __do_insl(p, b, n) readsl((PCI_IO_ADDR)_IO_BASE+(p), (b), (n))
544 #define __do_outsb(p, b, n) writesb((PCI_IO_ADDR)_IO_BASE+(p),(b),(n))
545 #define __do_outsw(p, b, n) writesw((PCI_IO_ADDR)_IO_BASE+(p),(b),(n))
546 #define __do_outsl(p, b, n) writesl((PCI_IO_ADDR)_IO_BASE+(p),(b),(n))
547
548 #define __do_memset_io(addr, c, n) \
549 _memset_io(PCI_FIX_ADDR(addr), c, n)
550 #define __do_memcpy_toio(dst, src, n) \
551 _memcpy_toio(PCI_FIX_ADDR(dst), src, n)
552
553 #ifdef CONFIG_EEH
554 #define __do_memcpy_fromio(dst, src, n) \
555 eeh_memcpy_fromio(dst, PCI_FIX_ADDR(src), n)
556 #else /* CONFIG_EEH */
557 #define __do_memcpy_fromio(dst, src, n) \
558 _memcpy_fromio(dst,PCI_FIX_ADDR(src),n)
559 #endif /* !CONFIG_EEH */
560
561 #ifdef CONFIG_PPC_INDIRECT_PIO
562 #define DEF_PCI_HOOK_pio(x) x
563 #else
564 #define DEF_PCI_HOOK_pio(x) NULL
565 #endif
566
567 #ifdef CONFIG_PPC_INDIRECT_MMIO
568 #define DEF_PCI_HOOK_mem(x) x
569 #else
570 #define DEF_PCI_HOOK_mem(x) NULL
571 #endif
572
573 /* Structure containing all the hooks */
574 extern struct ppc_pci_io {
575
576 #define DEF_PCI_AC_RET(name, ret, at, al, space, aa) ret (*name) at;
577 #define DEF_PCI_AC_NORET(name, at, al, space, aa) void (*name) at;
578
579 #include <asm/io-defs.h>
580
581 #undef DEF_PCI_AC_RET
582 #undef DEF_PCI_AC_NORET
583
584 } ppc_pci_io;
585
586 /* The inline wrappers */
587 #define DEF_PCI_AC_RET(name, ret, at, al, space, aa) \
588 static inline ret name at \
589 { \
590 if (DEF_PCI_HOOK_##space(ppc_pci_io.name) != NULL) \
591 return ppc_pci_io.name al; \
592 return __do_##name al; \
593 }
594
595 #define DEF_PCI_AC_NORET(name, at, al, space, aa) \
596 static inline void name at \
597 { \
598 if (DEF_PCI_HOOK_##space(ppc_pci_io.name) != NULL) \
599 ppc_pci_io.name al; \
600 else \
601 __do_##name al; \
602 }
603
604 #include <asm/io-defs.h>
605
606 #undef DEF_PCI_AC_RET
607 #undef DEF_PCI_AC_NORET
608
609 /* Some drivers check for the presence of readq & writeq with
610 * a #ifdef, so we make them happy here.
611 */
612 #ifdef __powerpc64__
613 #define readq readq
614 #define writeq writeq
615 #endif
616
617 /*
618 * Convert a physical pointer to a virtual kernel pointer for /dev/mem
619 * access
620 */
621 #define xlate_dev_mem_ptr(p) __va(p)
622
623 /*
624 * Convert a virtual cached pointer to an uncached pointer
625 */
626 #define xlate_dev_kmem_ptr(p) p
627
628 /*
629 * We don't do relaxed operations yet, at least not with this semantic
630 */
631 #define readb_relaxed(addr) readb(addr)
632 #define readw_relaxed(addr) readw(addr)
633 #define readl_relaxed(addr) readl(addr)
634 #define readq_relaxed(addr) readq(addr)
635 #define writeb_relaxed(v, addr) writeb(v, addr)
636 #define writew_relaxed(v, addr) writew(v, addr)
637 #define writel_relaxed(v, addr) writel(v, addr)
638 #define writeq_relaxed(v, addr) writeq(v, addr)
639
640 #include <asm-generic/iomap.h>
641
iosync(void)642 static inline void iosync(void)
643 {
644 __asm__ __volatile__ ("sync" : : : "memory");
645 }
646
647 /* Enforce in-order execution of data I/O.
648 * No distinction between read/write on PPC; use eieio for all three.
649 * Those are fairly week though. They don't provide a barrier between
650 * MMIO and cacheable storage nor do they provide a barrier vs. locks,
651 * they only provide barriers between 2 __raw MMIO operations and
652 * possibly break write combining.
653 */
654 #define iobarrier_rw() eieio()
655 #define iobarrier_r() eieio()
656 #define iobarrier_w() eieio()
657
658
659 /*
660 * output pause versions need a delay at least for the
661 * w83c105 ide controller in a p610.
662 */
663 #define inb_p(port) inb(port)
664 #define outb_p(val, port) (udelay(1), outb((val), (port)))
665 #define inw_p(port) inw(port)
666 #define outw_p(val, port) (udelay(1), outw((val), (port)))
667 #define inl_p(port) inl(port)
668 #define outl_p(val, port) (udelay(1), outl((val), (port)))
669
670
671 #define IO_SPACE_LIMIT ~(0UL)
672
673
674 /**
675 * ioremap - map bus memory into CPU space
676 * @address: bus address of the memory
677 * @size: size of the resource to map
678 *
679 * ioremap performs a platform specific sequence of operations to
680 * make bus memory CPU accessible via the readb/readw/readl/writeb/
681 * writew/writel functions and the other mmio helpers. The returned
682 * address is not guaranteed to be usable directly as a virtual
683 * address.
684 *
685 * We provide a few variations of it:
686 *
687 * * ioremap is the standard one and provides non-cacheable guarded mappings
688 * and can be hooked by the platform via ppc_md
689 *
690 * * ioremap_prot allows to specify the page flags as an argument and can
691 * also be hooked by the platform via ppc_md.
692 *
693 * * ioremap_wc enables write combining
694 *
695 * * ioremap_wt enables write through
696 *
697 * * ioremap_coherent maps coherent cached memory
698 *
699 * * iounmap undoes such a mapping and can be hooked
700 *
701 * * __ioremap_caller is the same as above but takes an explicit caller
702 * reference rather than using __builtin_return_address(0)
703 *
704 */
705 extern void __iomem *ioremap(phys_addr_t address, unsigned long size);
706 extern void __iomem *ioremap_prot(phys_addr_t address, unsigned long size,
707 unsigned long flags);
708 extern void __iomem *ioremap_wc(phys_addr_t address, unsigned long size);
709 void __iomem *ioremap_wt(phys_addr_t address, unsigned long size);
710 void __iomem *ioremap_coherent(phys_addr_t address, unsigned long size);
711 #define ioremap_uc(addr, size) ioremap((addr), (size))
712 #define ioremap_cache(addr, size) \
713 ioremap_prot((addr), (size), pgprot_val(PAGE_KERNEL))
714
715 extern void iounmap(volatile void __iomem *addr);
716
717 void __iomem *ioremap_phb(phys_addr_t paddr, unsigned long size);
718
719 int early_ioremap_range(unsigned long ea, phys_addr_t pa,
720 unsigned long size, pgprot_t prot);
721 void __iomem *do_ioremap(phys_addr_t pa, phys_addr_t offset, unsigned long size,
722 pgprot_t prot, void *caller);
723
724 extern void __iomem *__ioremap_caller(phys_addr_t, unsigned long size,
725 pgprot_t prot, void *caller);
726
727 /*
728 * When CONFIG_PPC_INDIRECT_PIO is set, we use the generic iomap implementation
729 * which needs some additional definitions here. They basically allow PIO
730 * space overall to be 1GB. This will work as long as we never try to use
731 * iomap to map MMIO below 1GB which should be fine on ppc64
732 */
733 #define HAVE_ARCH_PIO_SIZE 1
734 #define PIO_OFFSET 0x00000000UL
735 #define PIO_MASK (FULL_IO_SIZE - 1)
736 #define PIO_RESERVED (FULL_IO_SIZE)
737
738 #define mmio_read16be(addr) readw_be(addr)
739 #define mmio_read32be(addr) readl_be(addr)
740 #define mmio_read64be(addr) readq_be(addr)
741 #define mmio_write16be(val, addr) writew_be(val, addr)
742 #define mmio_write32be(val, addr) writel_be(val, addr)
743 #define mmio_write64be(val, addr) writeq_be(val, addr)
744 #define mmio_insb(addr, dst, count) readsb(addr, dst, count)
745 #define mmio_insw(addr, dst, count) readsw(addr, dst, count)
746 #define mmio_insl(addr, dst, count) readsl(addr, dst, count)
747 #define mmio_outsb(addr, src, count) writesb(addr, src, count)
748 #define mmio_outsw(addr, src, count) writesw(addr, src, count)
749 #define mmio_outsl(addr, src, count) writesl(addr, src, count)
750
751 /**
752 * virt_to_phys - map virtual addresses to physical
753 * @address: address to remap
754 *
755 * The returned physical address is the physical (CPU) mapping for
756 * the memory address given. It is only valid to use this function on
757 * addresses directly mapped or allocated via kmalloc.
758 *
759 * This function does not give bus mappings for DMA transfers. In
760 * almost all conceivable cases a device driver should not be using
761 * this function
762 */
virt_to_phys(volatile void * address)763 static inline unsigned long virt_to_phys(volatile void * address)
764 {
765 WARN_ON(IS_ENABLED(CONFIG_DEBUG_VIRTUAL) && !virt_addr_valid(address));
766
767 return __pa((unsigned long)address);
768 }
769
770 /**
771 * phys_to_virt - map physical address to virtual
772 * @address: address to remap
773 *
774 * The returned virtual address is a current CPU mapping for
775 * the memory address given. It is only valid to use this function on
776 * addresses that have a kernel mapping
777 *
778 * This function does not handle bus mappings for DMA transfers. In
779 * almost all conceivable cases a device driver should not be using
780 * this function
781 */
phys_to_virt(unsigned long address)782 static inline void * phys_to_virt(unsigned long address)
783 {
784 return (void *)__va(address);
785 }
786
787 /*
788 * Change "struct page" to physical address.
789 */
page_to_phys(struct page * page)790 static inline phys_addr_t page_to_phys(struct page *page)
791 {
792 unsigned long pfn = page_to_pfn(page);
793
794 WARN_ON(IS_ENABLED(CONFIG_DEBUG_VIRTUAL) && !pfn_valid(pfn));
795
796 return PFN_PHYS(pfn);
797 }
798
799 /*
800 * 32 bits still uses virt_to_bus() for it's implementation of DMA
801 * mappings se we have to keep it defined here. We also have some old
802 * drivers (shame shame shame) that use bus_to_virt() and haven't been
803 * fixed yet so I need to define it here.
804 */
805 #ifdef CONFIG_PPC32
806
virt_to_bus(volatile void * address)807 static inline unsigned long virt_to_bus(volatile void * address)
808 {
809 if (address == NULL)
810 return 0;
811 return __pa(address) + PCI_DRAM_OFFSET;
812 }
813
bus_to_virt(unsigned long address)814 static inline void * bus_to_virt(unsigned long address)
815 {
816 if (address == 0)
817 return NULL;
818 return __va(address - PCI_DRAM_OFFSET);
819 }
820
821 #define page_to_bus(page) (page_to_phys(page) + PCI_DRAM_OFFSET)
822
823 #endif /* CONFIG_PPC32 */
824
825 /* access ports */
826 #define setbits32(_addr, _v) out_be32((_addr), in_be32(_addr) | (_v))
827 #define clrbits32(_addr, _v) out_be32((_addr), in_be32(_addr) & ~(_v))
828
829 #define setbits16(_addr, _v) out_be16((_addr), in_be16(_addr) | (_v))
830 #define clrbits16(_addr, _v) out_be16((_addr), in_be16(_addr) & ~(_v))
831
832 #define setbits8(_addr, _v) out_8((_addr), in_8(_addr) | (_v))
833 #define clrbits8(_addr, _v) out_8((_addr), in_8(_addr) & ~(_v))
834
835 /* Clear and set bits in one shot. These macros can be used to clear and
836 * set multiple bits in a register using a single read-modify-write. These
837 * macros can also be used to set a multiple-bit bit pattern using a mask,
838 * by specifying the mask in the 'clear' parameter and the new bit pattern
839 * in the 'set' parameter.
840 */
841
842 #define clrsetbits(type, addr, clear, set) \
843 out_##type((addr), (in_##type(addr) & ~(clear)) | (set))
844
845 #ifdef __powerpc64__
846 #define clrsetbits_be64(addr, clear, set) clrsetbits(be64, addr, clear, set)
847 #define clrsetbits_le64(addr, clear, set) clrsetbits(le64, addr, clear, set)
848 #endif
849
850 #define clrsetbits_be32(addr, clear, set) clrsetbits(be32, addr, clear, set)
851 #define clrsetbits_le32(addr, clear, set) clrsetbits(le32, addr, clear, set)
852
853 #define clrsetbits_be16(addr, clear, set) clrsetbits(be16, addr, clear, set)
854 #define clrsetbits_le16(addr, clear, set) clrsetbits(le16, addr, clear, set)
855
856 #define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set)
857
858 #endif /* __KERNEL__ */
859
860 #endif /* _ASM_POWERPC_IO_H */
861
