Searched refs:__MASK (Results 1 – 6 of 6) sorted by relevance
65 #define __MASK(X) (1<<(X)) macro67 #define __MASK(X) (1UL<<(X)) macro71 #define MSR_SF __MASK(MSR_SF_LG) /* Enable 64 bit mode */72 #define MSR_ISF __MASK(MSR_ISF_LG) /* Interrupt 64b mode valid on 630 */73 #define MSR_HV __MASK(MSR_HV_LG) /* Hypervisor state */74 #define MSR_S __MASK(MSR_S_LG) /* Secure state */91 #define MSR_VEC __MASK(MSR_VEC_LG) /* Enable AltiVec */92 #define MSR_VSX __MASK(MSR_VSX_LG) /* Enable VSX */93 #define MSR_POW __MASK(MSR_POW_LG) /* Enable Power Management */94 #define MSR_WE __MASK(MSR_WE_LG) /* Wait State Enable */[all …]
28 #define MSR_GS __MASK(MSR_GS_LG)29 #define MSR_UCLE __MASK(MSR_UCLE_LG)30 #define MSR_SPE __MASK(MSR_SPE_LG)31 #define MSR_DWE __MASK(MSR_DWE_LG)32 #define MSR_UBLE __MASK(MSR_UBLE_LG)33 #define MSR_IS __MASK(MSR_IS_LG)34 #define MSR_DS __MASK(MSR_DS_LG)35 #define MSR_PMM __MASK(MSR_PMM_LG)36 #define MSR_CM __MASK(MSR_CM_LG)
90 #define __MASK(X) (1UL<<(X)) macro93 #define MSR_TS_S __MASK(MSR_TS_S_LG) /* Transaction Suspended */94 #define MSR_TS_T __MASK(MSR_TS_T_LG) /* Transaction Transactional */
13 #define EXTRACT(val, field) (((val) & field##__MASK) >> field##__SHIFT)
172 (((val) & field##__MASK) >> field##__SHIFT)
533 #define FIELD(val, name) (((val) & name ## __MASK) >> name ## __SHIFT)
