1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright 2000-2020 Broadcom Inc. All rights reserved. 4 * 5 * 6 * Name: mpi2_cnfg.h 7 * Title: MPI Configuration messages and pages 8 * Creation Date: November 10, 2006 9 * 10 * mpi2_cnfg.h Version: 02.00.47 11 * 12 * NOTE: Names (typedefs, defines, etc.) beginning with an MPI25 or Mpi25 13 * prefix are for use only on MPI v2.5 products, and must not be used 14 * with MPI v2.0 products. Unless otherwise noted, names beginning with 15 * MPI2 or Mpi2 are for use with both MPI v2.0 and MPI v2.5 products. 16 * 17 * Version History 18 * --------------- 19 * 20 * Date Version Description 21 * -------- -------- ------------------------------------------------------ 22 * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A. 23 * 06-04-07 02.00.01 Added defines for SAS IO Unit Page 2 PhyFlags. 24 * Added Manufacturing Page 11. 25 * Added MPI2_SAS_EXPANDER0_FLAGS_CONNECTOR_END_DEVICE 26 * define. 27 * 06-26-07 02.00.02 Adding generic structure for product-specific 28 * Manufacturing pages: MPI2_CONFIG_PAGE_MANUFACTURING_PS. 29 * Rework of BIOS Page 2 configuration page. 30 * Fixed MPI2_BIOSPAGE2_BOOT_DEVICE to be a union of the 31 * forms. 32 * Added configuration pages IOC Page 8 and Driver 33 * Persistent Mapping Page 0. 34 * 08-31-07 02.00.03 Modified configuration pages dealing with Integrated 35 * RAID (Manufacturing Page 4, RAID Volume Pages 0 and 1, 36 * RAID Physical Disk Pages 0 and 1, RAID Configuration 37 * Page 0). 38 * Added new value for AccessStatus field of SAS Device 39 * Page 0 (_SATA_NEEDS_INITIALIZATION). 40 * 10-31-07 02.00.04 Added missing SEPDevHandle field to 41 * MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0. 42 * 12-18-07 02.00.05 Modified IO Unit Page 0 to use 32-bit version fields for 43 * NVDATA. 44 * Modified IOC Page 7 to use masks and added field for 45 * SASBroadcastPrimitiveMasks. 46 * Added MPI2_CONFIG_PAGE_BIOS_4. 47 * Added MPI2_CONFIG_PAGE_LOG_0. 48 * 02-29-08 02.00.06 Modified various names to make them 32-character unique. 49 * Added SAS Device IDs. 50 * Updated Integrated RAID configuration pages including 51 * Manufacturing Page 4, IOC Page 6, and RAID Configuration 52 * Page 0. 53 * 05-21-08 02.00.07 Added define MPI2_MANPAGE4_MIX_SSD_SAS_SATA. 54 * Added define MPI2_MANPAGE4_PHYSDISK_128MB_COERCION. 55 * Fixed define MPI2_IOCPAGE8_FLAGS_ENCLOSURE_SLOT_MAPPING. 56 * Added missing MaxNumRoutedSasAddresses field to 57 * MPI2_CONFIG_PAGE_EXPANDER_0. 58 * Added SAS Port Page 0. 59 * Modified structure layout for 60 * MPI2_CONFIG_PAGE_DRIVER_MAPPING_0. 61 * 06-27-08 02.00.08 Changed MPI2_CONFIG_PAGE_RD_PDISK_1 to use 62 * MPI2_RAID_PHYS_DISK1_PATH_MAX to size the array. 63 * 10-02-08 02.00.09 Changed MPI2_RAID_PGAD_CONFIGNUM_MASK from 0x0000FFFF 64 * to 0x000000FF. 65 * Added two new values for the Physical Disk Coercion Size 66 * bits in the Flags field of Manufacturing Page 4. 67 * Added product-specific Manufacturing pages 16 to 31. 68 * Modified Flags bits for controlling write cache on SATA 69 * drives in IO Unit Page 1. 70 * Added new bit to AdditionalControlFlags of SAS IO Unit 71 * Page 1 to control Invalid Topology Correction. 72 * Added additional defines for RAID Volume Page 0 73 * VolumeStatusFlags field. 74 * Modified meaning of RAID Volume Page 0 VolumeSettings 75 * define for auto-configure of hot-swap drives. 76 * Added SupportedPhysDisks field to RAID Volume Page 1 and 77 * added related defines. 78 * Added PhysDiskAttributes field (and related defines) to 79 * RAID Physical Disk Page 0. 80 * Added MPI2_SAS_PHYINFO_PHY_VACANT define. 81 * Added three new DiscoveryStatus bits for SAS IO Unit 82 * Page 0 and SAS Expander Page 0. 83 * Removed multiplexing information from SAS IO Unit pages. 84 * Added BootDeviceWaitTime field to SAS IO Unit Page 4. 85 * Removed Zone Address Resolved bit from PhyInfo and from 86 * Expander Page 0 Flags field. 87 * Added two new AccessStatus values to SAS Device Page 0 88 * for indicating routing problems. Added 3 reserved words 89 * to this page. 90 * 01-19-09 02.00.10 Fixed defines for GPIOVal field of IO Unit Page 3. 91 * Inserted missing reserved field into structure for IOC 92 * Page 6. 93 * Added more pending task bits to RAID Volume Page 0 94 * VolumeStatusFlags defines. 95 * Added MPI2_PHYSDISK0_STATUS_FLAG_NOT_CERTIFIED define. 96 * Added a new DiscoveryStatus bit for SAS IO Unit Page 0 97 * and SAS Expander Page 0 to flag a downstream initiator 98 * when in simplified routing mode. 99 * Removed SATA Init Failure defines for DiscoveryStatus 100 * fields of SAS IO Unit Page 0 and SAS Expander Page 0. 101 * Added MPI2_SAS_DEVICE0_ASTATUS_DEVICE_BLOCKED define. 102 * Added PortGroups, DmaGroup, and ControlGroup fields to 103 * SAS Device Page 0. 104 * 05-06-09 02.00.11 Added structures and defines for IO Unit Page 5 and IO 105 * Unit Page 6. 106 * Added expander reduced functionality data to SAS 107 * Expander Page 0. 108 * Added SAS PHY Page 2 and SAS PHY Page 3. 109 * 07-30-09 02.00.12 Added IO Unit Page 7. 110 * Added new device ids. 111 * Added SAS IO Unit Page 5. 112 * Added partial and slumber power management capable flags 113 * to SAS Device Page 0 Flags field. 114 * Added PhyInfo defines for power condition. 115 * Added Ethernet configuration pages. 116 * 10-28-09 02.00.13 Added MPI2_IOUNITPAGE1_ENABLE_HOST_BASED_DISCOVERY. 117 * Added SAS PHY Page 4 structure and defines. 118 * 02-10-10 02.00.14 Modified the comments for the configuration page 119 * structures that contain an array of data. The host 120 * should use the "count" field in the page data (e.g. the 121 * NumPhys field) to determine the number of valid elements 122 * in the array. 123 * Added/modified some MPI2_MFGPAGE_DEVID_SAS defines. 124 * Added PowerManagementCapabilities to IO Unit Page 7. 125 * Added PortWidthModGroup field to 126 * MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS. 127 * Added MPI2_CONFIG_PAGE_SASIOUNIT_6 and related defines. 128 * Added MPI2_CONFIG_PAGE_SASIOUNIT_7 and related defines. 129 * Added MPI2_CONFIG_PAGE_SASIOUNIT_8 and related defines. 130 * 05-12-10 02.00.15 Added MPI2_RAIDVOL0_STATUS_FLAG_VOL_NOT_CONSISTENT 131 * define. 132 * Added MPI2_PHYSDISK0_INCOMPATIBLE_MEDIA_TYPE define. 133 * Added MPI2_SAS_NEG_LINK_RATE_UNSUPPORTED_PHY define. 134 * 08-11-10 02.00.16 Removed IO Unit Page 1 device path (multi-pathing) 135 * defines. 136 * 11-10-10 02.00.17 Added ReceptacleID field (replacing Reserved1) to 137 * MPI2_MANPAGE7_CONNECTOR_INFO and reworked defines for 138 * the Pinout field. 139 * Added BoardTemperature and BoardTemperatureUnits fields 140 * to MPI2_CONFIG_PAGE_IO_UNIT_7. 141 * Added MPI2_CONFIG_EXTPAGETYPE_EXT_MANUFACTURING define 142 * and MPI2_CONFIG_PAGE_EXT_MAN_PS structure. 143 * 02-23-11 02.00.18 Added ProxyVF_ID field to MPI2_CONFIG_REQUEST. 144 * Added IO Unit Page 8, IO Unit Page 9, 145 * and IO Unit Page 10. 146 * Added SASNotifyPrimitiveMasks field to 147 * MPI2_CONFIG_PAGE_IOC_7. 148 * 03-09-11 02.00.19 Fixed IO Unit Page 10 (to match the spec). 149 * 05-25-11 02.00.20 Cleaned up a few comments. 150 * 08-24-11 02.00.21 Marked the IO Unit Page 7 PowerManagementCapabilities 151 * for PCIe link as obsolete. 152 * Added SpinupFlags field containing a Disable Spin-up bit 153 * to the MPI2_SAS_IOUNIT4_SPINUP_GROUP fields of SAS IO 154 * Unit Page 4. 155 * 11-18-11 02.00.22 Added define MPI2_IOCPAGE6_CAP_FLAGS_4K_SECTORS_SUPPORT. 156 * Added UEFIVersion field to BIOS Page 1 and defined new 157 * BiosOptions bits. 158 * Incorporating additions for MPI v2.5. 159 * 11-27-12 02.00.23 Added MPI2_MANPAGE7_FLAG_EVENTREPLAY_SLOT_ORDER. 160 * Added MPI2_BIOSPAGE1_OPTIONS_MASK_OEM_ID. 161 * 12-20-12 02.00.24 Marked MPI2_SASIOUNIT1_CONTROL_CLEAR_AFFILIATION as 162 * obsolete for MPI v2.5 and later. 163 * Added some defines for 12G SAS speeds. 164 * 04-09-13 02.00.25 Added MPI2_IOUNITPAGE1_ATA_SECURITY_FREEZE_LOCK. 165 * Fixed MPI2_IOUNITPAGE5_DMA_CAP_MASK_MAX_REQUESTS to 166 * match the specification. 167 * 08-19-13 02.00.26 Added reserved words to MPI2_CONFIG_PAGE_IO_UNIT_7 for 168 * future use. 169 * 12-05-13 02.00.27 Added MPI2_MANPAGE7_FLAG_BASE_ENCLOSURE_LEVEL for 170 * MPI2_CONFIG_PAGE_MAN_7. 171 * Added EnclosureLevel and ConnectorName fields to 172 * MPI2_CONFIG_PAGE_SAS_DEV_0. 173 * Added MPI2_SAS_DEVICE0_FLAGS_ENCL_LEVEL_VALID for 174 * MPI2_CONFIG_PAGE_SAS_DEV_0. 175 * Added EnclosureLevel field to 176 * MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0. 177 * Added MPI2_SAS_ENCLS0_FLAGS_ENCL_LEVEL_VALID for 178 * MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0. 179 * 01-08-14 02.00.28 Added more defines for the BiosOptions field of 180 * MPI2_CONFIG_PAGE_BIOS_1. 181 * 06-13-14 02.00.29 Added SSUTimeout field to MPI2_CONFIG_PAGE_BIOS_1, and 182 * more defines for the BiosOptions field. 183 * 11-18-14 02.00.30 Updated copyright information. 184 * Added MPI2_BIOSPAGE1_OPTIONS_ADVANCED_CONFIG. 185 * Added AdapterOrderAux fields to BIOS Page 3. 186 * 03-16-15 02.00.31 Updated for MPI v2.6. 187 * Added Flags field to IO Unit Page 7. 188 * Added new SAS Phy Event codes 189 * 05-25-15 02.00.33 Added more defines for the BiosOptions field of 190 * MPI2_CONFIG_PAGE_BIOS_1. 191 * 08-25-15 02.00.34 Bumped Header Version. 192 * 12-18-15 02.00.35 Added SATADeviceWaitTime to SAS IO Unit Page 4. 193 * 01-21-16 02.00.36 Added/modified MPI2_MFGPAGE_DEVID_SAS defines. 194 * Added Link field to PCIe Link Pages 195 * Added EnclosureLevel and ConnectorName to PCIe 196 * Device Page 0. 197 * Added define for PCIE IoUnit page 1 max rate shift. 198 * Added comment for reserved ExtPageTypes. 199 * Added SAS 4 22.5 gbs speed support. 200 * Added PCIe 4 16.0 GT/sec speec support. 201 * Removed AHCI support. 202 * Removed SOP support. 203 * Added NegotiatedLinkRate and NegotiatedPortWidth to 204 * PCIe device page 0. 205 * 04-10-16 02.00.37 Fixed MPI2_MFGPAGE_DEVID_SAS3616/3708 defines 206 * 07-01-16 02.00.38 Added Manufacturing page 7 Connector types. 207 * Changed declaration of ConnectorName in PCIe DevicePage0 208 * to match SAS DevicePage 0. 209 * Added SATADeviceWaitTime to IO Unit Page 11. 210 * Added MPI26_MFGPAGE_DEVID_SAS4008 211 * Added x16 PCIe width to IO Unit Page 7 212 * Added LINKFLAGS to control SRIS in PCIe IO Unit page 1 213 * phy data. 214 * Added InitStatus to PCIe IO Unit Page 1 header. 215 * 09-01-16 02.00.39 Added MPI26_CONFIG_PAGE_ENCLOSURE_0 and related defines. 216 * Added MPI26_ENCLOS_PGAD_FORM_GET_NEXT_HANDLE and 217 * MPI26_ENCLOS_PGAD_FORM_HANDLE page address formats. 218 * 02-02-17 02.00.40 Added MPI2_MANPAGE7_SLOT_UNKNOWN. 219 * Added ChassisSlot field to SAS Enclosure Page 0. 220 * Added ChassisSlot Valid bit (bit 5) to the Flags field 221 * in SAS Enclosure Page 0. 222 * 06-13-17 02.00.41 Added MPI26_MFGPAGE_DEVID_SAS3816 and 223 * MPI26_MFGPAGE_DEVID_SAS3916 defines. 224 * Removed MPI26_MFGPAGE_DEVID_SAS4008 define. 225 * Added MPI26_PCIEIOUNIT1_LINKFLAGS_SRNS_EN define. 226 * Renamed PI26_PCIEIOUNIT1_LINKFLAGS_EN_SRIS to 227 * PI26_PCIEIOUNIT1_LINKFLAGS_SRIS_EN. 228 * Renamed MPI26_PCIEIOUNIT1_LINKFLAGS_DIS_SRIS to 229 * MPI26_PCIEIOUNIT1_LINKFLAGS_DIS_SEPARATE_REFCLK. 230 * 09-29-17 02.00.42 Added ControllerResetTO field to PCIe Device Page 2. 231 * Added NOIOB field to PCIe Device Page 2. 232 * Added MPI26_PCIEDEV2_CAP_DATA_BLK_ALIGN_AND_GRAN to 233 * the Capabilities field of PCIe Device Page 2. 234 * 07-22-18 02.00.43 Added defines for SAS3916 and SAS3816. 235 * Added WRiteCache defines to IO Unit Page 1. 236 * Added MaxEnclosureLevel to BIOS Page 1. 237 * Added OEMRD to SAS Enclosure Page 1. 238 * Added DMDReportPCIe to PCIe IO Unit Page 1. 239 * Added Flags field and flags for Retimers to 240 * PCIe Switch Page 1. 241 * 08-02-18 02.00.44 Added Slotx2, Slotx4 to ManPage 7. 242 * 08-15-18 02.00.45 Added ProductSpecific field at end of IOC Page 1 243 * 08-28-18 02.00.46 Added NVMs Write Cache flag to IOUnitPage1 244 * Added DMDReport Delay Time defines to 245 * PCIeIOUnitPage1 246 * -------------------------------------------------------------------------- 247 * 08-02-18 02.00.44 Added Slotx2, Slotx4 to ManPage 7. 248 * 08-15-18 02.00.45 Added ProductSpecific field at end of IOC Page 1 249 * 08-28-18 02.00.46 Added NVMs Write Cache flag to IOUnitPage1 250 * Added DMDReport Delay Time defines to PCIeIOUnitPage1 251 * 12-17-18 02.00.47 Swap locations of Slotx2 and Slotx4 in ManPage 7. 252 * 08-01-19 02.00.49 Add MPI26_MANPAGE7_FLAG_X2_X4_SLOT_INFO_VALID 253 * Add MPI26_IOUNITPAGE1_NVME_WRCACHE_SHIFT 254 */ 255 256 #ifndef MPI2_CNFG_H 257 #define MPI2_CNFG_H 258 259 /***************************************************************************** 260 * Configuration Page Header and defines 261 *****************************************************************************/ 262 263 /*Config Page Header */ 264 typedef struct _MPI2_CONFIG_PAGE_HEADER { 265 U8 PageVersion; /*0x00 */ 266 U8 PageLength; /*0x01 */ 267 U8 PageNumber; /*0x02 */ 268 U8 PageType; /*0x03 */ 269 } MPI2_CONFIG_PAGE_HEADER, *PTR_MPI2_CONFIG_PAGE_HEADER, 270 Mpi2ConfigPageHeader_t, *pMpi2ConfigPageHeader_t; 271 272 typedef union _MPI2_CONFIG_PAGE_HEADER_UNION { 273 MPI2_CONFIG_PAGE_HEADER Struct; 274 U8 Bytes[4]; 275 U16 Word16[2]; 276 U32 Word32; 277 } MPI2_CONFIG_PAGE_HEADER_UNION, *PTR_MPI2_CONFIG_PAGE_HEADER_UNION, 278 Mpi2ConfigPageHeaderUnion, *pMpi2ConfigPageHeaderUnion; 279 280 /*Extended Config Page Header */ 281 typedef struct _MPI2_CONFIG_EXTENDED_PAGE_HEADER { 282 U8 PageVersion; /*0x00 */ 283 U8 Reserved1; /*0x01 */ 284 U8 PageNumber; /*0x02 */ 285 U8 PageType; /*0x03 */ 286 U16 ExtPageLength; /*0x04 */ 287 U8 ExtPageType; /*0x06 */ 288 U8 Reserved2; /*0x07 */ 289 } MPI2_CONFIG_EXTENDED_PAGE_HEADER, 290 *PTR_MPI2_CONFIG_EXTENDED_PAGE_HEADER, 291 Mpi2ConfigExtendedPageHeader_t, 292 *pMpi2ConfigExtendedPageHeader_t; 293 294 typedef union _MPI2_CONFIG_EXT_PAGE_HEADER_UNION { 295 MPI2_CONFIG_PAGE_HEADER Struct; 296 MPI2_CONFIG_EXTENDED_PAGE_HEADER Ext; 297 U8 Bytes[8]; 298 U16 Word16[4]; 299 U32 Word32[2]; 300 } MPI2_CONFIG_EXT_PAGE_HEADER_UNION, 301 *PTR_MPI2_CONFIG_EXT_PAGE_HEADER_UNION, 302 Mpi2ConfigPageExtendedHeaderUnion, 303 *pMpi2ConfigPageExtendedHeaderUnion; 304 305 306 /*PageType field values */ 307 #define MPI2_CONFIG_PAGEATTR_READ_ONLY (0x00) 308 #define MPI2_CONFIG_PAGEATTR_CHANGEABLE (0x10) 309 #define MPI2_CONFIG_PAGEATTR_PERSISTENT (0x20) 310 #define MPI2_CONFIG_PAGEATTR_MASK (0xF0) 311 312 #define MPI2_CONFIG_PAGETYPE_IO_UNIT (0x00) 313 #define MPI2_CONFIG_PAGETYPE_IOC (0x01) 314 #define MPI2_CONFIG_PAGETYPE_BIOS (0x02) 315 #define MPI2_CONFIG_PAGETYPE_RAID_VOLUME (0x08) 316 #define MPI2_CONFIG_PAGETYPE_MANUFACTURING (0x09) 317 #define MPI2_CONFIG_PAGETYPE_RAID_PHYSDISK (0x0A) 318 #define MPI2_CONFIG_PAGETYPE_EXTENDED (0x0F) 319 #define MPI2_CONFIG_PAGETYPE_MASK (0x0F) 320 321 #define MPI2_CONFIG_TYPENUM_MASK (0x0FFF) 322 323 324 /*ExtPageType field values */ 325 #define MPI2_CONFIG_EXTPAGETYPE_SAS_IO_UNIT (0x10) 326 #define MPI2_CONFIG_EXTPAGETYPE_SAS_EXPANDER (0x11) 327 #define MPI2_CONFIG_EXTPAGETYPE_SAS_DEVICE (0x12) 328 #define MPI2_CONFIG_EXTPAGETYPE_SAS_PHY (0x13) 329 #define MPI2_CONFIG_EXTPAGETYPE_LOG (0x14) 330 #define MPI2_CONFIG_EXTPAGETYPE_ENCLOSURE (0x15) 331 #define MPI2_CONFIG_EXTPAGETYPE_RAID_CONFIG (0x16) 332 #define MPI2_CONFIG_EXTPAGETYPE_DRIVER_MAPPING (0x17) 333 #define MPI2_CONFIG_EXTPAGETYPE_SAS_PORT (0x18) 334 #define MPI2_CONFIG_EXTPAGETYPE_ETHERNET (0x19) 335 #define MPI2_CONFIG_EXTPAGETYPE_EXT_MANUFACTURING (0x1A) 336 #define MPI2_CONFIG_EXTPAGETYPE_PCIE_IO_UNIT (0x1B) 337 #define MPI2_CONFIG_EXTPAGETYPE_PCIE_SWITCH (0x1C) 338 #define MPI2_CONFIG_EXTPAGETYPE_PCIE_DEVICE (0x1D) 339 #define MPI2_CONFIG_EXTPAGETYPE_PCIE_LINK (0x1E) 340 341 342 /***************************************************************************** 343 * PageAddress defines 344 *****************************************************************************/ 345 346 /*RAID Volume PageAddress format */ 347 #define MPI2_RAID_VOLUME_PGAD_FORM_MASK (0xF0000000) 348 #define MPI2_RAID_VOLUME_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) 349 #define MPI2_RAID_VOLUME_PGAD_FORM_HANDLE (0x10000000) 350 351 #define MPI2_RAID_VOLUME_PGAD_HANDLE_MASK (0x0000FFFF) 352 353 354 /*RAID Physical Disk PageAddress format */ 355 #define MPI2_PHYSDISK_PGAD_FORM_MASK (0xF0000000) 356 #define MPI2_PHYSDISK_PGAD_FORM_GET_NEXT_PHYSDISKNUM (0x00000000) 357 #define MPI2_PHYSDISK_PGAD_FORM_PHYSDISKNUM (0x10000000) 358 #define MPI2_PHYSDISK_PGAD_FORM_DEVHANDLE (0x20000000) 359 360 #define MPI2_PHYSDISK_PGAD_PHYSDISKNUM_MASK (0x000000FF) 361 #define MPI2_PHYSDISK_PGAD_DEVHANDLE_MASK (0x0000FFFF) 362 363 364 /*SAS Expander PageAddress format */ 365 #define MPI2_SAS_EXPAND_PGAD_FORM_MASK (0xF0000000) 366 #define MPI2_SAS_EXPAND_PGAD_FORM_GET_NEXT_HNDL (0x00000000) 367 #define MPI2_SAS_EXPAND_PGAD_FORM_HNDL_PHY_NUM (0x10000000) 368 #define MPI2_SAS_EXPAND_PGAD_FORM_HNDL (0x20000000) 369 370 #define MPI2_SAS_EXPAND_PGAD_HANDLE_MASK (0x0000FFFF) 371 #define MPI2_SAS_EXPAND_PGAD_PHYNUM_MASK (0x00FF0000) 372 #define MPI2_SAS_EXPAND_PGAD_PHYNUM_SHIFT (16) 373 374 375 /*SAS Device PageAddress format */ 376 #define MPI2_SAS_DEVICE_PGAD_FORM_MASK (0xF0000000) 377 #define MPI2_SAS_DEVICE_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) 378 #define MPI2_SAS_DEVICE_PGAD_FORM_HANDLE (0x20000000) 379 380 #define MPI2_SAS_DEVICE_PGAD_HANDLE_MASK (0x0000FFFF) 381 382 383 /*SAS PHY PageAddress format */ 384 #define MPI2_SAS_PHY_PGAD_FORM_MASK (0xF0000000) 385 #define MPI2_SAS_PHY_PGAD_FORM_PHY_NUMBER (0x00000000) 386 #define MPI2_SAS_PHY_PGAD_FORM_PHY_TBL_INDEX (0x10000000) 387 388 #define MPI2_SAS_PHY_PGAD_PHY_NUMBER_MASK (0x000000FF) 389 #define MPI2_SAS_PHY_PGAD_PHY_TBL_INDEX_MASK (0x0000FFFF) 390 391 392 /*SAS Port PageAddress format */ 393 #define MPI2_SASPORT_PGAD_FORM_MASK (0xF0000000) 394 #define MPI2_SASPORT_PGAD_FORM_GET_NEXT_PORT (0x00000000) 395 #define MPI2_SASPORT_PGAD_FORM_PORT_NUM (0x10000000) 396 397 #define MPI2_SASPORT_PGAD_PORTNUMBER_MASK (0x00000FFF) 398 399 400 /*SAS Enclosure PageAddress format */ 401 #define MPI2_SAS_ENCLOS_PGAD_FORM_MASK (0xF0000000) 402 #define MPI2_SAS_ENCLOS_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) 403 #define MPI2_SAS_ENCLOS_PGAD_FORM_HANDLE (0x10000000) 404 405 #define MPI2_SAS_ENCLOS_PGAD_HANDLE_MASK (0x0000FFFF) 406 407 /*Enclosure PageAddress format */ 408 #define MPI26_ENCLOS_PGAD_FORM_MASK (0xF0000000) 409 #define MPI26_ENCLOS_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) 410 #define MPI26_ENCLOS_PGAD_FORM_HANDLE (0x10000000) 411 412 #define MPI26_ENCLOS_PGAD_HANDLE_MASK (0x0000FFFF) 413 414 /*RAID Configuration PageAddress format */ 415 #define MPI2_RAID_PGAD_FORM_MASK (0xF0000000) 416 #define MPI2_RAID_PGAD_FORM_GET_NEXT_CONFIGNUM (0x00000000) 417 #define MPI2_RAID_PGAD_FORM_CONFIGNUM (0x10000000) 418 #define MPI2_RAID_PGAD_FORM_ACTIVE_CONFIG (0x20000000) 419 420 #define MPI2_RAID_PGAD_CONFIGNUM_MASK (0x000000FF) 421 422 423 /*Driver Persistent Mapping PageAddress format */ 424 #define MPI2_DPM_PGAD_FORM_MASK (0xF0000000) 425 #define MPI2_DPM_PGAD_FORM_ENTRY_RANGE (0x00000000) 426 427 #define MPI2_DPM_PGAD_ENTRY_COUNT_MASK (0x0FFF0000) 428 #define MPI2_DPM_PGAD_ENTRY_COUNT_SHIFT (16) 429 #define MPI2_DPM_PGAD_START_ENTRY_MASK (0x0000FFFF) 430 431 432 /*Ethernet PageAddress format */ 433 #define MPI2_ETHERNET_PGAD_FORM_MASK (0xF0000000) 434 #define MPI2_ETHERNET_PGAD_FORM_IF_NUM (0x00000000) 435 436 #define MPI2_ETHERNET_PGAD_IF_NUMBER_MASK (0x000000FF) 437 438 439 /*PCIe Switch PageAddress format */ 440 #define MPI26_PCIE_SWITCH_PGAD_FORM_MASK (0xF0000000) 441 #define MPI26_PCIE_SWITCH_PGAD_FORM_GET_NEXT_HNDL (0x00000000) 442 #define MPI26_PCIE_SWITCH_PGAD_FORM_HNDL_PORTNUM (0x10000000) 443 #define MPI26_PCIE_SWITCH_EXPAND_PGAD_FORM_HNDL (0x20000000) 444 445 #define MPI26_PCIE_SWITCH_PGAD_HANDLE_MASK (0x0000FFFF) 446 #define MPI26_PCIE_SWITCH_PGAD_PORTNUM_MASK (0x00FF0000) 447 #define MPI26_PCIE_SWITCH_PGAD_PORTNUM_SHIFT (16) 448 449 450 /*PCIe Device PageAddress format */ 451 #define MPI26_PCIE_DEVICE_PGAD_FORM_MASK (0xF0000000) 452 #define MPI26_PCIE_DEVICE_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) 453 #define MPI26_PCIE_DEVICE_PGAD_FORM_HANDLE (0x20000000) 454 455 #define MPI26_PCIE_DEVICE_PGAD_HANDLE_MASK (0x0000FFFF) 456 457 /*PCIe Link PageAddress format */ 458 #define MPI26_PCIE_LINK_PGAD_FORM_MASK (0xF0000000) 459 #define MPI26_PCIE_LINK_PGAD_FORM_GET_NEXT_LINK (0x00000000) 460 #define MPI26_PCIE_LINK_PGAD_FORM_LINK_NUM (0x10000000) 461 462 #define MPI26_PCIE_DEVICE_PGAD_LINKNUM_MASK (0x000000FF) 463 464 465 466 /**************************************************************************** 467 * Configuration messages 468 ****************************************************************************/ 469 470 /*Configuration Request Message */ 471 typedef struct _MPI2_CONFIG_REQUEST { 472 U8 Action; /*0x00 */ 473 U8 SGLFlags; /*0x01 */ 474 U8 ChainOffset; /*0x02 */ 475 U8 Function; /*0x03 */ 476 U16 ExtPageLength; /*0x04 */ 477 U8 ExtPageType; /*0x06 */ 478 U8 MsgFlags; /*0x07 */ 479 U8 VP_ID; /*0x08 */ 480 U8 VF_ID; /*0x09 */ 481 U16 Reserved1; /*0x0A */ 482 U8 Reserved2; /*0x0C */ 483 U8 ProxyVF_ID; /*0x0D */ 484 U16 Reserved4; /*0x0E */ 485 U32 Reserved3; /*0x10 */ 486 MPI2_CONFIG_PAGE_HEADER Header; /*0x14 */ 487 U32 PageAddress; /*0x18 */ 488 MPI2_SGE_IO_UNION PageBufferSGE; /*0x1C */ 489 } MPI2_CONFIG_REQUEST, *PTR_MPI2_CONFIG_REQUEST, 490 Mpi2ConfigRequest_t, *pMpi2ConfigRequest_t; 491 492 /*values for the Action field */ 493 #define MPI2_CONFIG_ACTION_PAGE_HEADER (0x00) 494 #define MPI2_CONFIG_ACTION_PAGE_READ_CURRENT (0x01) 495 #define MPI2_CONFIG_ACTION_PAGE_WRITE_CURRENT (0x02) 496 #define MPI2_CONFIG_ACTION_PAGE_DEFAULT (0x03) 497 #define MPI2_CONFIG_ACTION_PAGE_WRITE_NVRAM (0x04) 498 #define MPI2_CONFIG_ACTION_PAGE_READ_DEFAULT (0x05) 499 #define MPI2_CONFIG_ACTION_PAGE_READ_NVRAM (0x06) 500 #define MPI2_CONFIG_ACTION_PAGE_GET_CHANGEABLE (0x07) 501 502 /*use MPI2_SGLFLAGS_ defines from mpi2.h for the SGLFlags field */ 503 504 505 /*Config Reply Message */ 506 typedef struct _MPI2_CONFIG_REPLY { 507 U8 Action; /*0x00 */ 508 U8 SGLFlags; /*0x01 */ 509 U8 MsgLength; /*0x02 */ 510 U8 Function; /*0x03 */ 511 U16 ExtPageLength; /*0x04 */ 512 U8 ExtPageType; /*0x06 */ 513 U8 MsgFlags; /*0x07 */ 514 U8 VP_ID; /*0x08 */ 515 U8 VF_ID; /*0x09 */ 516 U16 Reserved1; /*0x0A */ 517 U16 Reserved2; /*0x0C */ 518 U16 IOCStatus; /*0x0E */ 519 U32 IOCLogInfo; /*0x10 */ 520 MPI2_CONFIG_PAGE_HEADER Header; /*0x14 */ 521 } MPI2_CONFIG_REPLY, *PTR_MPI2_CONFIG_REPLY, 522 Mpi2ConfigReply_t, *pMpi2ConfigReply_t; 523 524 525 526 /***************************************************************************** 527 * 528 * C o n f i g u r a t i o n P a g e s 529 * 530 *****************************************************************************/ 531 532 /**************************************************************************** 533 * Manufacturing Config pages 534 ****************************************************************************/ 535 536 #define MPI2_MFGPAGE_VENDORID_LSI (0x1000) 537 538 /*MPI v2.0 SAS products */ 539 #define MPI2_MFGPAGE_DEVID_SAS2004 (0x0070) 540 #define MPI2_MFGPAGE_DEVID_SAS2008 (0x0072) 541 #define MPI2_MFGPAGE_DEVID_SAS2108_1 (0x0074) 542 #define MPI2_MFGPAGE_DEVID_SAS2108_2 (0x0076) 543 #define MPI2_MFGPAGE_DEVID_SAS2108_3 (0x0077) 544 #define MPI2_MFGPAGE_DEVID_SAS2116_1 (0x0064) 545 #define MPI2_MFGPAGE_DEVID_SAS2116_2 (0x0065) 546 547 #define MPI2_MFGPAGE_DEVID_SSS6200 (0x007E) 548 549 #define MPI2_MFGPAGE_DEVID_SAS2208_1 (0x0080) 550 #define MPI2_MFGPAGE_DEVID_SAS2208_2 (0x0081) 551 #define MPI2_MFGPAGE_DEVID_SAS2208_3 (0x0082) 552 #define MPI2_MFGPAGE_DEVID_SAS2208_4 (0x0083) 553 #define MPI2_MFGPAGE_DEVID_SAS2208_5 (0x0084) 554 #define MPI2_MFGPAGE_DEVID_SAS2208_6 (0x0085) 555 #define MPI2_MFGPAGE_DEVID_SAS2308_1 (0x0086) 556 #define MPI2_MFGPAGE_DEVID_SAS2308_2 (0x0087) 557 #define MPI2_MFGPAGE_DEVID_SAS2308_3 (0x006E) 558 #define MPI2_MFGPAGE_DEVID_SWITCH_MPI_EP (0x02B0) 559 #define MPI2_MFGPAGE_DEVID_SWITCH_MPI_EP_1 (0x02B1) 560 561 /*MPI v2.5 SAS products */ 562 #define MPI25_MFGPAGE_DEVID_SAS3004 (0x0096) 563 #define MPI25_MFGPAGE_DEVID_SAS3008 (0x0097) 564 #define MPI25_MFGPAGE_DEVID_SAS3108_1 (0x0090) 565 #define MPI25_MFGPAGE_DEVID_SAS3108_2 (0x0091) 566 #define MPI25_MFGPAGE_DEVID_SAS3108_5 (0x0094) 567 #define MPI25_MFGPAGE_DEVID_SAS3108_6 (0x0095) 568 569 /* MPI v2.6 SAS Products */ 570 #define MPI26_MFGPAGE_DEVID_SAS3216 (0x00C9) 571 #define MPI26_MFGPAGE_DEVID_SAS3224 (0x00C4) 572 #define MPI26_MFGPAGE_DEVID_SAS3316_1 (0x00C5) 573 #define MPI26_MFGPAGE_DEVID_SAS3316_2 (0x00C6) 574 #define MPI26_MFGPAGE_DEVID_SAS3316_3 (0x00C7) 575 #define MPI26_MFGPAGE_DEVID_SAS3316_4 (0x00C8) 576 #define MPI26_MFGPAGE_DEVID_SAS3324_1 (0x00C0) 577 #define MPI26_MFGPAGE_DEVID_SAS3324_2 (0x00C1) 578 #define MPI26_MFGPAGE_DEVID_SAS3324_3 (0x00C2) 579 #define MPI26_MFGPAGE_DEVID_SAS3324_4 (0x00C3) 580 581 #define MPI26_MFGPAGE_DEVID_SAS3516 (0x00AA) 582 #define MPI26_MFGPAGE_DEVID_SAS3516_1 (0x00AB) 583 #define MPI26_MFGPAGE_DEVID_SAS3416 (0x00AC) 584 #define MPI26_MFGPAGE_DEVID_SAS3508 (0x00AD) 585 #define MPI26_MFGPAGE_DEVID_SAS3508_1 (0x00AE) 586 #define MPI26_MFGPAGE_DEVID_SAS3408 (0x00AF) 587 #define MPI26_MFGPAGE_DEVID_SAS3716 (0x00D0) 588 #define MPI26_MFGPAGE_DEVID_SAS3616 (0x00D1) 589 #define MPI26_MFGPAGE_DEVID_SAS3708 (0x00D2) 590 591 #define MPI26_MFGPAGE_DEVID_SEC_MASK_3916 (0x0003) 592 #define MPI26_MFGPAGE_DEVID_INVALID0_3916 (0x00E0) 593 #define MPI26_MFGPAGE_DEVID_CFG_SEC_3916 (0x00E1) 594 #define MPI26_MFGPAGE_DEVID_HARD_SEC_3916 (0x00E2) 595 #define MPI26_MFGPAGE_DEVID_INVALID1_3916 (0x00E3) 596 597 #define MPI26_MFGPAGE_DEVID_SEC_MASK_3816 (0x0003) 598 #define MPI26_MFGPAGE_DEVID_INVALID0_3816 (0x00E4) 599 #define MPI26_MFGPAGE_DEVID_CFG_SEC_3816 (0x00E5) 600 #define MPI26_MFGPAGE_DEVID_HARD_SEC_3816 (0x00E6) 601 #define MPI26_MFGPAGE_DEVID_INVALID1_3816 (0x00E7) 602 603 604 /*Manufacturing Page 0 */ 605 606 typedef struct _MPI2_CONFIG_PAGE_MAN_0 { 607 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 608 U8 ChipName[16]; /*0x04 */ 609 U8 ChipRevision[8]; /*0x14 */ 610 U8 BoardName[16]; /*0x1C */ 611 U8 BoardAssembly[16]; /*0x2C */ 612 U8 BoardTracerNumber[16]; /*0x3C */ 613 } MPI2_CONFIG_PAGE_MAN_0, 614 *PTR_MPI2_CONFIG_PAGE_MAN_0, 615 Mpi2ManufacturingPage0_t, 616 *pMpi2ManufacturingPage0_t; 617 618 #define MPI2_MANUFACTURING0_PAGEVERSION (0x00) 619 620 621 /*Manufacturing Page 1 */ 622 623 typedef struct _MPI2_CONFIG_PAGE_MAN_1 { 624 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 625 U8 VPD[256]; /*0x04 */ 626 } MPI2_CONFIG_PAGE_MAN_1, 627 *PTR_MPI2_CONFIG_PAGE_MAN_1, 628 Mpi2ManufacturingPage1_t, 629 *pMpi2ManufacturingPage1_t; 630 631 #define MPI2_MANUFACTURING1_PAGEVERSION (0x00) 632 633 634 typedef struct _MPI2_CHIP_REVISION_ID { 635 U16 DeviceID; /*0x00 */ 636 U8 PCIRevisionID; /*0x02 */ 637 U8 Reserved; /*0x03 */ 638 } MPI2_CHIP_REVISION_ID, *PTR_MPI2_CHIP_REVISION_ID, 639 Mpi2ChipRevisionId_t, *pMpi2ChipRevisionId_t; 640 641 642 /*Manufacturing Page 2 */ 643 644 /* 645 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 646 *one and check Header.PageLength at runtime. 647 */ 648 #ifndef MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS 649 #define MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS (1) 650 #endif 651 652 typedef struct _MPI2_CONFIG_PAGE_MAN_2 { 653 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 654 MPI2_CHIP_REVISION_ID ChipId; /*0x04 */ 655 U32 656 HwSettings[MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS];/*0x08 */ 657 } MPI2_CONFIG_PAGE_MAN_2, 658 *PTR_MPI2_CONFIG_PAGE_MAN_2, 659 Mpi2ManufacturingPage2_t, 660 *pMpi2ManufacturingPage2_t; 661 662 #define MPI2_MANUFACTURING2_PAGEVERSION (0x00) 663 664 665 /*Manufacturing Page 3 */ 666 667 /* 668 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 669 *one and check Header.PageLength at runtime. 670 */ 671 #ifndef MPI2_MAN_PAGE_3_INFO_WORDS 672 #define MPI2_MAN_PAGE_3_INFO_WORDS (1) 673 #endif 674 675 typedef struct _MPI2_CONFIG_PAGE_MAN_3 { 676 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 677 MPI2_CHIP_REVISION_ID ChipId; /*0x04 */ 678 U32 679 Info[MPI2_MAN_PAGE_3_INFO_WORDS];/*0x08 */ 680 } MPI2_CONFIG_PAGE_MAN_3, 681 *PTR_MPI2_CONFIG_PAGE_MAN_3, 682 Mpi2ManufacturingPage3_t, 683 *pMpi2ManufacturingPage3_t; 684 685 #define MPI2_MANUFACTURING3_PAGEVERSION (0x00) 686 687 688 /*Manufacturing Page 4 */ 689 690 typedef struct _MPI2_MANPAGE4_PWR_SAVE_SETTINGS { 691 U8 PowerSaveFlags; /*0x00 */ 692 U8 InternalOperationsSleepTime; /*0x01 */ 693 U8 InternalOperationsRunTime; /*0x02 */ 694 U8 HostIdleTime; /*0x03 */ 695 } MPI2_MANPAGE4_PWR_SAVE_SETTINGS, 696 *PTR_MPI2_MANPAGE4_PWR_SAVE_SETTINGS, 697 Mpi2ManPage4PwrSaveSettings_t, 698 *pMpi2ManPage4PwrSaveSettings_t; 699 700 /*defines for the PowerSaveFlags field */ 701 #define MPI2_MANPAGE4_MASK_POWERSAVE_MODE (0x03) 702 #define MPI2_MANPAGE4_POWERSAVE_MODE_DISABLED (0x00) 703 #define MPI2_MANPAGE4_CUSTOM_POWERSAVE_MODE (0x01) 704 #define MPI2_MANPAGE4_FULL_POWERSAVE_MODE (0x02) 705 706 typedef struct _MPI2_CONFIG_PAGE_MAN_4 { 707 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 708 U32 Reserved1; /*0x04 */ 709 U32 Flags; /*0x08 */ 710 U8 InquirySize; /*0x0C */ 711 U8 Reserved2; /*0x0D */ 712 U16 Reserved3; /*0x0E */ 713 U8 InquiryData[56]; /*0x10 */ 714 U32 RAID0VolumeSettings; /*0x48 */ 715 U32 RAID1EVolumeSettings; /*0x4C */ 716 U32 RAID1VolumeSettings; /*0x50 */ 717 U32 RAID10VolumeSettings; /*0x54 */ 718 U32 Reserved4; /*0x58 */ 719 U32 Reserved5; /*0x5C */ 720 MPI2_MANPAGE4_PWR_SAVE_SETTINGS PowerSaveSettings; /*0x60 */ 721 U8 MaxOCEDisks; /*0x64 */ 722 U8 ResyncRate; /*0x65 */ 723 U16 DataScrubDuration; /*0x66 */ 724 U8 MaxHotSpares; /*0x68 */ 725 U8 MaxPhysDisksPerVol; /*0x69 */ 726 U8 MaxPhysDisks; /*0x6A */ 727 U8 MaxVolumes; /*0x6B */ 728 } MPI2_CONFIG_PAGE_MAN_4, 729 *PTR_MPI2_CONFIG_PAGE_MAN_4, 730 Mpi2ManufacturingPage4_t, 731 *pMpi2ManufacturingPage4_t; 732 733 #define MPI2_MANUFACTURING4_PAGEVERSION (0x0A) 734 735 /*Manufacturing Page 4 Flags field */ 736 #define MPI2_MANPAGE4_METADATA_SIZE_MASK (0x00030000) 737 #define MPI2_MANPAGE4_METADATA_512MB (0x00000000) 738 739 #define MPI2_MANPAGE4_MIX_SSD_SAS_SATA (0x00008000) 740 #define MPI2_MANPAGE4_MIX_SSD_AND_NON_SSD (0x00004000) 741 #define MPI2_MANPAGE4_HIDE_PHYSDISK_NON_IR (0x00002000) 742 743 #define MPI2_MANPAGE4_MASK_PHYSDISK_COERCION (0x00001C00) 744 #define MPI2_MANPAGE4_PHYSDISK_COERCION_1GB (0x00000000) 745 #define MPI2_MANPAGE4_PHYSDISK_128MB_COERCION (0x00000400) 746 #define MPI2_MANPAGE4_PHYSDISK_ADAPTIVE_COERCION (0x00000800) 747 #define MPI2_MANPAGE4_PHYSDISK_ZERO_COERCION (0x00000C00) 748 749 #define MPI2_MANPAGE4_MASK_BAD_BLOCK_MARKING (0x00000300) 750 #define MPI2_MANPAGE4_DEFAULT_BAD_BLOCK_MARKING (0x00000000) 751 #define MPI2_MANPAGE4_TABLE_BAD_BLOCK_MARKING (0x00000100) 752 #define MPI2_MANPAGE4_WRITE_LONG_BAD_BLOCK_MARKING (0x00000200) 753 754 #define MPI2_MANPAGE4_FORCE_OFFLINE_FAILOVER (0x00000080) 755 #define MPI2_MANPAGE4_RAID10_DISABLE (0x00000040) 756 #define MPI2_MANPAGE4_RAID1E_DISABLE (0x00000020) 757 #define MPI2_MANPAGE4_RAID1_DISABLE (0x00000010) 758 #define MPI2_MANPAGE4_RAID0_DISABLE (0x00000008) 759 #define MPI2_MANPAGE4_IR_MODEPAGE8_DISABLE (0x00000004) 760 #define MPI2_MANPAGE4_IM_RESYNC_CACHE_ENABLE (0x00000002) 761 #define MPI2_MANPAGE4_IR_NO_MIX_SAS_SATA (0x00000001) 762 763 764 /*Manufacturing Page 5 */ 765 766 /* 767 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 768 *one and check the value returned for NumPhys at runtime. 769 */ 770 #ifndef MPI2_MAN_PAGE_5_PHY_ENTRIES 771 #define MPI2_MAN_PAGE_5_PHY_ENTRIES (1) 772 #endif 773 774 typedef struct _MPI2_MANUFACTURING5_ENTRY { 775 U64 WWID; /*0x00 */ 776 U64 DeviceName; /*0x08 */ 777 } MPI2_MANUFACTURING5_ENTRY, 778 *PTR_MPI2_MANUFACTURING5_ENTRY, 779 Mpi2Manufacturing5Entry_t, 780 *pMpi2Manufacturing5Entry_t; 781 782 typedef struct _MPI2_CONFIG_PAGE_MAN_5 { 783 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 784 U8 NumPhys; /*0x04 */ 785 U8 Reserved1; /*0x05 */ 786 U16 Reserved2; /*0x06 */ 787 U32 Reserved3; /*0x08 */ 788 U32 Reserved4; /*0x0C */ 789 MPI2_MANUFACTURING5_ENTRY 790 Phy[MPI2_MAN_PAGE_5_PHY_ENTRIES];/*0x08 */ 791 } MPI2_CONFIG_PAGE_MAN_5, 792 *PTR_MPI2_CONFIG_PAGE_MAN_5, 793 Mpi2ManufacturingPage5_t, 794 *pMpi2ManufacturingPage5_t; 795 796 #define MPI2_MANUFACTURING5_PAGEVERSION (0x03) 797 798 799 /*Manufacturing Page 6 */ 800 801 typedef struct _MPI2_CONFIG_PAGE_MAN_6 { 802 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 803 U32 ProductSpecificInfo;/*0x04 */ 804 } MPI2_CONFIG_PAGE_MAN_6, 805 *PTR_MPI2_CONFIG_PAGE_MAN_6, 806 Mpi2ManufacturingPage6_t, 807 *pMpi2ManufacturingPage6_t; 808 809 #define MPI2_MANUFACTURING6_PAGEVERSION (0x00) 810 811 812 /*Manufacturing Page 7 */ 813 814 typedef struct _MPI2_MANPAGE7_CONNECTOR_INFO { 815 U32 Pinout; /*0x00 */ 816 U8 Connector[16]; /*0x04 */ 817 U8 Location; /*0x14 */ 818 U8 ReceptacleID; /*0x15 */ 819 U16 Slot; /*0x16 */ 820 U16 Slotx2; /*0x18 */ 821 U16 Slotx4; /*0x1A */ 822 } MPI2_MANPAGE7_CONNECTOR_INFO, 823 *PTR_MPI2_MANPAGE7_CONNECTOR_INFO, 824 Mpi2ManPage7ConnectorInfo_t, 825 *pMpi2ManPage7ConnectorInfo_t; 826 827 /*defines for the Pinout field */ 828 #define MPI2_MANPAGE7_PINOUT_LANE_MASK (0x0000FF00) 829 #define MPI2_MANPAGE7_PINOUT_LANE_SHIFT (8) 830 831 #define MPI2_MANPAGE7_PINOUT_TYPE_MASK (0x000000FF) 832 #define MPI2_MANPAGE7_PINOUT_TYPE_UNKNOWN (0x00) 833 #define MPI2_MANPAGE7_PINOUT_SATA_SINGLE (0x01) 834 #define MPI2_MANPAGE7_PINOUT_SFF_8482 (0x02) 835 #define MPI2_MANPAGE7_PINOUT_SFF_8486 (0x03) 836 #define MPI2_MANPAGE7_PINOUT_SFF_8484 (0x04) 837 #define MPI2_MANPAGE7_PINOUT_SFF_8087 (0x05) 838 #define MPI2_MANPAGE7_PINOUT_SFF_8643_4I (0x06) 839 #define MPI2_MANPAGE7_PINOUT_SFF_8643_8I (0x07) 840 #define MPI2_MANPAGE7_PINOUT_SFF_8470 (0x08) 841 #define MPI2_MANPAGE7_PINOUT_SFF_8088 (0x09) 842 #define MPI2_MANPAGE7_PINOUT_SFF_8644_4X (0x0A) 843 #define MPI2_MANPAGE7_PINOUT_SFF_8644_8X (0x0B) 844 #define MPI2_MANPAGE7_PINOUT_SFF_8644_16X (0x0C) 845 #define MPI2_MANPAGE7_PINOUT_SFF_8436 (0x0D) 846 #define MPI2_MANPAGE7_PINOUT_SFF_8088_A (0x0E) 847 #define MPI2_MANPAGE7_PINOUT_SFF_8643_16i (0x0F) 848 #define MPI2_MANPAGE7_PINOUT_SFF_8654_4i (0x10) 849 #define MPI2_MANPAGE7_PINOUT_SFF_8654_8i (0x11) 850 #define MPI2_MANPAGE7_PINOUT_SFF_8611_4i (0x12) 851 #define MPI2_MANPAGE7_PINOUT_SFF_8611_8i (0x13) 852 853 /*defines for the Location field */ 854 #define MPI2_MANPAGE7_LOCATION_UNKNOWN (0x01) 855 #define MPI2_MANPAGE7_LOCATION_INTERNAL (0x02) 856 #define MPI2_MANPAGE7_LOCATION_EXTERNAL (0x04) 857 #define MPI2_MANPAGE7_LOCATION_SWITCHABLE (0x08) 858 #define MPI2_MANPAGE7_LOCATION_AUTO (0x10) 859 #define MPI2_MANPAGE7_LOCATION_NOT_PRESENT (0x20) 860 #define MPI2_MANPAGE7_LOCATION_NOT_CONNECTED (0x80) 861 862 /*defines for the Slot field */ 863 #define MPI2_MANPAGE7_SLOT_UNKNOWN (0xFFFF) 864 865 /* 866 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 867 *one and check the value returned for NumPhys at runtime. 868 */ 869 #ifndef MPI2_MANPAGE7_CONNECTOR_INFO_MAX 870 #define MPI2_MANPAGE7_CONNECTOR_INFO_MAX (1) 871 #endif 872 873 typedef struct _MPI2_CONFIG_PAGE_MAN_7 { 874 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 875 U32 Reserved1; /*0x04 */ 876 U32 Reserved2; /*0x08 */ 877 U32 Flags; /*0x0C */ 878 U8 EnclosureName[16]; /*0x10 */ 879 U8 NumPhys; /*0x20 */ 880 U8 Reserved3; /*0x21 */ 881 U16 Reserved4; /*0x22 */ 882 MPI2_MANPAGE7_CONNECTOR_INFO 883 ConnectorInfo[MPI2_MANPAGE7_CONNECTOR_INFO_MAX]; /*0x24 */ 884 } MPI2_CONFIG_PAGE_MAN_7, 885 *PTR_MPI2_CONFIG_PAGE_MAN_7, 886 Mpi2ManufacturingPage7_t, 887 *pMpi2ManufacturingPage7_t; 888 889 #define MPI2_MANUFACTURING7_PAGEVERSION (0x01) 890 891 /*defines for the Flags field */ 892 #define MPI2_MANPAGE7_FLAG_BASE_ENCLOSURE_LEVEL (0x00000008) 893 #define MPI2_MANPAGE7_FLAG_EVENTREPLAY_SLOT_ORDER (0x00000002) 894 #define MPI2_MANPAGE7_FLAG_USE_SLOT_INFO (0x00000001) 895 896 #define MPI26_MANPAGE7_FLAG_CONN_LANE_USE_PINOUT (0x00000020) 897 #define MPI26_MANPAGE7_FLAG_X2_X4_SLOT_INFO_VALID (0x00000010) 898 899 /* 900 *Generic structure to use for product-specific manufacturing pages 901 *(currently Manufacturing Page 8 through Manufacturing Page 31). 902 */ 903 904 typedef struct _MPI2_CONFIG_PAGE_MAN_PS { 905 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 906 U32 ProductSpecificInfo;/*0x04 */ 907 } MPI2_CONFIG_PAGE_MAN_PS, 908 *PTR_MPI2_CONFIG_PAGE_MAN_PS, 909 Mpi2ManufacturingPagePS_t, 910 *pMpi2ManufacturingPagePS_t; 911 912 #define MPI2_MANUFACTURING8_PAGEVERSION (0x00) 913 #define MPI2_MANUFACTURING9_PAGEVERSION (0x00) 914 #define MPI2_MANUFACTURING10_PAGEVERSION (0x00) 915 #define MPI2_MANUFACTURING11_PAGEVERSION (0x00) 916 #define MPI2_MANUFACTURING12_PAGEVERSION (0x00) 917 #define MPI2_MANUFACTURING13_PAGEVERSION (0x00) 918 #define MPI2_MANUFACTURING14_PAGEVERSION (0x00) 919 #define MPI2_MANUFACTURING15_PAGEVERSION (0x00) 920 #define MPI2_MANUFACTURING16_PAGEVERSION (0x00) 921 #define MPI2_MANUFACTURING17_PAGEVERSION (0x00) 922 #define MPI2_MANUFACTURING18_PAGEVERSION (0x00) 923 #define MPI2_MANUFACTURING19_PAGEVERSION (0x00) 924 #define MPI2_MANUFACTURING20_PAGEVERSION (0x00) 925 #define MPI2_MANUFACTURING21_PAGEVERSION (0x00) 926 #define MPI2_MANUFACTURING22_PAGEVERSION (0x00) 927 #define MPI2_MANUFACTURING23_PAGEVERSION (0x00) 928 #define MPI2_MANUFACTURING24_PAGEVERSION (0x00) 929 #define MPI2_MANUFACTURING25_PAGEVERSION (0x00) 930 #define MPI2_MANUFACTURING26_PAGEVERSION (0x00) 931 #define MPI2_MANUFACTURING27_PAGEVERSION (0x00) 932 #define MPI2_MANUFACTURING28_PAGEVERSION (0x00) 933 #define MPI2_MANUFACTURING29_PAGEVERSION (0x00) 934 #define MPI2_MANUFACTURING30_PAGEVERSION (0x00) 935 #define MPI2_MANUFACTURING31_PAGEVERSION (0x00) 936 937 938 /**************************************************************************** 939 * IO Unit Config Pages 940 ****************************************************************************/ 941 942 /*IO Unit Page 0 */ 943 944 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_0 { 945 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 946 U64 UniqueValue; /*0x04 */ 947 MPI2_VERSION_UNION NvdataVersionDefault; /*0x08 */ 948 MPI2_VERSION_UNION NvdataVersionPersistent; /*0x0A */ 949 } MPI2_CONFIG_PAGE_IO_UNIT_0, 950 *PTR_MPI2_CONFIG_PAGE_IO_UNIT_0, 951 Mpi2IOUnitPage0_t, *pMpi2IOUnitPage0_t; 952 953 #define MPI2_IOUNITPAGE0_PAGEVERSION (0x02) 954 955 956 /*IO Unit Page 1 */ 957 958 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_1 { 959 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 960 U32 Flags; /*0x04 */ 961 } MPI2_CONFIG_PAGE_IO_UNIT_1, 962 *PTR_MPI2_CONFIG_PAGE_IO_UNIT_1, 963 Mpi2IOUnitPage1_t, *pMpi2IOUnitPage1_t; 964 965 #define MPI2_IOUNITPAGE1_PAGEVERSION (0x04) 966 967 /* IO Unit Page 1 Flags defines */ 968 #define MPI26_IOUNITPAGE1_NVME_WRCACHE_MASK (0x00030000) 969 #define MPI26_IOUNITPAGE1_NVME_WRCACHE_SHIFT (16) 970 #define MPI26_IOUNITPAGE1_NVME_WRCACHE_NO_CHANGE (0x00000000) 971 #define MPI26_IOUNITPAGE1_NVME_WRCACHE_ENABLE (0x00010000) 972 #define MPI26_IOUNITPAGE1_NVME_WRCACHE_DISABLE (0x00020000) 973 #define MPI2_IOUNITPAGE1_ATA_SECURITY_FREEZE_LOCK (0x00004000) 974 #define MPI25_IOUNITPAGE1_NEW_DEVICE_FAST_PATH_DISABLE (0x00002000) 975 #define MPI25_IOUNITPAGE1_DISABLE_FAST_PATH (0x00001000) 976 #define MPI2_IOUNITPAGE1_ENABLE_HOST_BASED_DISCOVERY (0x00000800) 977 #define MPI2_IOUNITPAGE1_MASK_SATA_WRITE_CACHE (0x00000600) 978 #define MPI2_IOUNITPAGE1_SATA_WRITE_CACHE_SHIFT (9) 979 #define MPI2_IOUNITPAGE1_ENABLE_SATA_WRITE_CACHE (0x00000000) 980 #define MPI2_IOUNITPAGE1_DISABLE_SATA_WRITE_CACHE (0x00000200) 981 #define MPI2_IOUNITPAGE1_UNCHANGED_SATA_WRITE_CACHE (0x00000400) 982 #define MPI2_IOUNITPAGE1_NATIVE_COMMAND_Q_DISABLE (0x00000100) 983 #define MPI2_IOUNITPAGE1_DISABLE_IR (0x00000040) 984 #define MPI2_IOUNITPAGE1_DISABLE_TASK_SET_FULL_HANDLING (0x00000020) 985 #define MPI2_IOUNITPAGE1_IR_USE_STATIC_VOLUME_ID (0x00000004) 986 987 988 /*IO Unit Page 3 */ 989 990 /* 991 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 992 *one and check the value returned for GPIOCount at runtime. 993 */ 994 #ifndef MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX 995 #define MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX (1) 996 #endif 997 998 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_3 { 999 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1000 U8 GPIOCount; /*0x04 */ 1001 U8 Reserved1; /*0x05 */ 1002 U16 Reserved2; /*0x06 */ 1003 U16 1004 GPIOVal[MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX];/*0x08 */ 1005 } MPI2_CONFIG_PAGE_IO_UNIT_3, 1006 *PTR_MPI2_CONFIG_PAGE_IO_UNIT_3, 1007 Mpi2IOUnitPage3_t, *pMpi2IOUnitPage3_t; 1008 1009 #define MPI2_IOUNITPAGE3_PAGEVERSION (0x01) 1010 1011 /*defines for IO Unit Page 3 GPIOVal field */ 1012 #define MPI2_IOUNITPAGE3_GPIO_FUNCTION_MASK (0xFFFC) 1013 #define MPI2_IOUNITPAGE3_GPIO_FUNCTION_SHIFT (2) 1014 #define MPI2_IOUNITPAGE3_GPIO_SETTING_OFF (0x0000) 1015 #define MPI2_IOUNITPAGE3_GPIO_SETTING_ON (0x0001) 1016 1017 1018 /*IO Unit Page 5 */ 1019 1020 /* 1021 *Upper layer code (drivers, utilities, etc.) should leave this define set to 1022 *one and check the value returned for NumDmaEngines at runtime. 1023 */ 1024 #ifndef MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES 1025 #define MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES (1) 1026 #endif 1027 1028 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_5 { 1029 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1030 U64 1031 RaidAcceleratorBufferBaseAddress; /*0x04 */ 1032 U64 1033 RaidAcceleratorBufferSize; /*0x0C */ 1034 U64 1035 RaidAcceleratorControlBaseAddress; /*0x14 */ 1036 U8 RAControlSize; /*0x1C */ 1037 U8 NumDmaEngines; /*0x1D */ 1038 U8 RAMinControlSize; /*0x1E */ 1039 U8 RAMaxControlSize; /*0x1F */ 1040 U32 Reserved1; /*0x20 */ 1041 U32 Reserved2; /*0x24 */ 1042 U32 Reserved3; /*0x28 */ 1043 U32 1044 DmaEngineCapabilities[MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES]; /*0x2C */ 1045 } MPI2_CONFIG_PAGE_IO_UNIT_5, 1046 *PTR_MPI2_CONFIG_PAGE_IO_UNIT_5, 1047 Mpi2IOUnitPage5_t, *pMpi2IOUnitPage5_t; 1048 1049 #define MPI2_IOUNITPAGE5_PAGEVERSION (0x00) 1050 1051 /*defines for IO Unit Page 5 DmaEngineCapabilities field */ 1052 #define MPI2_IOUNITPAGE5_DMA_CAP_MASK_MAX_REQUESTS (0xFFFF0000) 1053 #define MPI2_IOUNITPAGE5_DMA_CAP_SHIFT_MAX_REQUESTS (16) 1054 1055 #define MPI2_IOUNITPAGE5_DMA_CAP_EEDP (0x0008) 1056 #define MPI2_IOUNITPAGE5_DMA_CAP_PARITY_GENERATION (0x0004) 1057 #define MPI2_IOUNITPAGE5_DMA_CAP_HASHING (0x0002) 1058 #define MPI2_IOUNITPAGE5_DMA_CAP_ENCRYPTION (0x0001) 1059 1060 1061 /*IO Unit Page 6 */ 1062 1063 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_6 { 1064 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1065 U16 Flags; /*0x04 */ 1066 U8 RAHostControlSize; /*0x06 */ 1067 U8 Reserved0; /*0x07 */ 1068 U64 1069 RaidAcceleratorHostControlBaseAddress; /*0x08 */ 1070 U32 Reserved1; /*0x10 */ 1071 U32 Reserved2; /*0x14 */ 1072 U32 Reserved3; /*0x18 */ 1073 } MPI2_CONFIG_PAGE_IO_UNIT_6, 1074 *PTR_MPI2_CONFIG_PAGE_IO_UNIT_6, 1075 Mpi2IOUnitPage6_t, *pMpi2IOUnitPage6_t; 1076 1077 #define MPI2_IOUNITPAGE6_PAGEVERSION (0x00) 1078 1079 /*defines for IO Unit Page 6 Flags field */ 1080 #define MPI2_IOUNITPAGE6_FLAGS_ENABLE_RAID_ACCELERATOR (0x0001) 1081 1082 1083 /*IO Unit Page 7 */ 1084 1085 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_7 { 1086 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1087 U8 CurrentPowerMode; /*0x04 */ 1088 U8 PreviousPowerMode; /*0x05 */ 1089 U8 PCIeWidth; /*0x06 */ 1090 U8 PCIeSpeed; /*0x07 */ 1091 U32 ProcessorState; /*0x08 */ 1092 U32 1093 PowerManagementCapabilities; /*0x0C */ 1094 U16 IOCTemperature; /*0x10 */ 1095 U8 1096 IOCTemperatureUnits; /*0x12 */ 1097 U8 IOCSpeed; /*0x13 */ 1098 U16 BoardTemperature; /*0x14 */ 1099 U8 1100 BoardTemperatureUnits; /*0x16 */ 1101 U8 Reserved3; /*0x17 */ 1102 U32 BoardPowerRequirement; /*0x18 */ 1103 U32 PCISlotPowerAllocation; /*0x1C */ 1104 /* reserved prior to MPI v2.6 */ 1105 U8 Flags; /* 0x20 */ 1106 U8 Reserved6; /* 0x21 */ 1107 U16 Reserved7; /* 0x22 */ 1108 U32 Reserved8; /* 0x24 */ 1109 } MPI2_CONFIG_PAGE_IO_UNIT_7, 1110 *PTR_MPI2_CONFIG_PAGE_IO_UNIT_7, 1111 Mpi2IOUnitPage7_t, *pMpi2IOUnitPage7_t; 1112 1113 #define MPI2_IOUNITPAGE7_PAGEVERSION (0x05) 1114 1115 /*defines for IO Unit Page 7 CurrentPowerMode and PreviousPowerMode fields */ 1116 #define MPI25_IOUNITPAGE7_PM_INIT_MASK (0xC0) 1117 #define MPI25_IOUNITPAGE7_PM_INIT_UNAVAILABLE (0x00) 1118 #define MPI25_IOUNITPAGE7_PM_INIT_HOST (0x40) 1119 #define MPI25_IOUNITPAGE7_PM_INIT_IO_UNIT (0x80) 1120 #define MPI25_IOUNITPAGE7_PM_INIT_PCIE_DPA (0xC0) 1121 1122 #define MPI25_IOUNITPAGE7_PM_MODE_MASK (0x07) 1123 #define MPI25_IOUNITPAGE7_PM_MODE_UNAVAILABLE (0x00) 1124 #define MPI25_IOUNITPAGE7_PM_MODE_UNKNOWN (0x01) 1125 #define MPI25_IOUNITPAGE7_PM_MODE_FULL_POWER (0x04) 1126 #define MPI25_IOUNITPAGE7_PM_MODE_REDUCED_POWER (0x05) 1127 #define MPI25_IOUNITPAGE7_PM_MODE_STANDBY (0x06) 1128 1129 1130 /*defines for IO Unit Page 7 PCIeWidth field */ 1131 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X1 (0x01) 1132 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X2 (0x02) 1133 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X4 (0x04) 1134 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X8 (0x08) 1135 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X16 (0x10) 1136 1137 /*defines for IO Unit Page 7 PCIeSpeed field */ 1138 #define MPI2_IOUNITPAGE7_PCIE_SPEED_2_5_GBPS (0x00) 1139 #define MPI2_IOUNITPAGE7_PCIE_SPEED_5_0_GBPS (0x01) 1140 #define MPI2_IOUNITPAGE7_PCIE_SPEED_8_0_GBPS (0x02) 1141 #define MPI2_IOUNITPAGE7_PCIE_SPEED_16_0_GBPS (0x03) 1142 1143 /*defines for IO Unit Page 7 ProcessorState field */ 1144 #define MPI2_IOUNITPAGE7_PSTATE_MASK_SECOND (0x0000000F) 1145 #define MPI2_IOUNITPAGE7_PSTATE_SHIFT_SECOND (0) 1146 1147 #define MPI2_IOUNITPAGE7_PSTATE_NOT_PRESENT (0x00) 1148 #define MPI2_IOUNITPAGE7_PSTATE_DISABLED (0x01) 1149 #define MPI2_IOUNITPAGE7_PSTATE_ENABLED (0x02) 1150 1151 /*defines for IO Unit Page 7 PowerManagementCapabilities field */ 1152 #define MPI25_IOUNITPAGE7_PMCAP_DPA_FULL_PWR_MODE (0x00400000) 1153 #define MPI25_IOUNITPAGE7_PMCAP_DPA_REDUCED_PWR_MODE (0x00200000) 1154 #define MPI25_IOUNITPAGE7_PMCAP_DPA_STANDBY_MODE (0x00100000) 1155 #define MPI25_IOUNITPAGE7_PMCAP_HOST_FULL_PWR_MODE (0x00040000) 1156 #define MPI25_IOUNITPAGE7_PMCAP_HOST_REDUCED_PWR_MODE (0x00020000) 1157 #define MPI25_IOUNITPAGE7_PMCAP_HOST_STANDBY_MODE (0x00010000) 1158 #define MPI25_IOUNITPAGE7_PMCAP_IO_FULL_PWR_MODE (0x00004000) 1159 #define MPI25_IOUNITPAGE7_PMCAP_IO_REDUCED_PWR_MODE (0x00002000) 1160 #define MPI25_IOUNITPAGE7_PMCAP_IO_STANDBY_MODE (0x00001000) 1161 #define MPI2_IOUNITPAGE7_PMCAP_HOST_12_5_PCT_IOCSPEED (0x00000400) 1162 #define MPI2_IOUNITPAGE7_PMCAP_HOST_25_0_PCT_IOCSPEED (0x00000200) 1163 #define MPI2_IOUNITPAGE7_PMCAP_HOST_50_0_PCT_IOCSPEED (0x00000100) 1164 #define MPI25_IOUNITPAGE7_PMCAP_IO_12_5_PCT_IOCSPEED (0x00000040) 1165 #define MPI25_IOUNITPAGE7_PMCAP_IO_25_0_PCT_IOCSPEED (0x00000020) 1166 #define MPI25_IOUNITPAGE7_PMCAP_IO_50_0_PCT_IOCSPEED (0x00000010) 1167 #define MPI2_IOUNITPAGE7_PMCAP_HOST_WIDTH_CHANGE_PCIE (0x00000008) 1168 #define MPI2_IOUNITPAGE7_PMCAP_HOST_SPEED_CHANGE_PCIE (0x00000004) 1169 #define MPI25_IOUNITPAGE7_PMCAP_IO_WIDTH_CHANGE_PCIE (0x00000002) 1170 #define MPI25_IOUNITPAGE7_PMCAP_IO_SPEED_CHANGE_PCIE (0x00000001) 1171 1172 /*obsolete names for the PowerManagementCapabilities bits (above) */ 1173 #define MPI2_IOUNITPAGE7_PMCAP_12_5_PCT_IOCSPEED (0x00000400) 1174 #define MPI2_IOUNITPAGE7_PMCAP_25_0_PCT_IOCSPEED (0x00000200) 1175 #define MPI2_IOUNITPAGE7_PMCAP_50_0_PCT_IOCSPEED (0x00000100) 1176 #define MPI2_IOUNITPAGE7_PMCAP_PCIE_WIDTH_CHANGE (0x00000008) /*obsolete */ 1177 #define MPI2_IOUNITPAGE7_PMCAP_PCIE_SPEED_CHANGE (0x00000004) /*obsolete */ 1178 1179 1180 /*defines for IO Unit Page 7 IOCTemperatureUnits field */ 1181 #define MPI2_IOUNITPAGE7_IOC_TEMP_NOT_PRESENT (0x00) 1182 #define MPI2_IOUNITPAGE7_IOC_TEMP_FAHRENHEIT (0x01) 1183 #define MPI2_IOUNITPAGE7_IOC_TEMP_CELSIUS (0x02) 1184 1185 /*defines for IO Unit Page 7 IOCSpeed field */ 1186 #define MPI2_IOUNITPAGE7_IOC_SPEED_FULL (0x01) 1187 #define MPI2_IOUNITPAGE7_IOC_SPEED_HALF (0x02) 1188 #define MPI2_IOUNITPAGE7_IOC_SPEED_QUARTER (0x04) 1189 #define MPI2_IOUNITPAGE7_IOC_SPEED_EIGHTH (0x08) 1190 1191 /*defines for IO Unit Page 7 BoardTemperatureUnits field */ 1192 #define MPI2_IOUNITPAGE7_BOARD_TEMP_NOT_PRESENT (0x00) 1193 #define MPI2_IOUNITPAGE7_BOARD_TEMP_FAHRENHEIT (0x01) 1194 #define MPI2_IOUNITPAGE7_BOARD_TEMP_CELSIUS (0x02) 1195 1196 /* defines for IO Unit Page 7 Flags field */ 1197 #define MPI2_IOUNITPAGE7_FLAG_CABLE_POWER_EXC (0x01) 1198 1199 /*IO Unit Page 8 */ 1200 1201 #define MPI2_IOUNIT8_NUM_THRESHOLDS (4) 1202 1203 typedef struct _MPI2_IOUNIT8_SENSOR { 1204 U16 Flags; /*0x00 */ 1205 U16 Reserved1; /*0x02 */ 1206 U16 1207 Threshold[MPI2_IOUNIT8_NUM_THRESHOLDS]; /*0x04 */ 1208 U32 Reserved2; /*0x0C */ 1209 U32 Reserved3; /*0x10 */ 1210 U32 Reserved4; /*0x14 */ 1211 } MPI2_IOUNIT8_SENSOR, *PTR_MPI2_IOUNIT8_SENSOR, 1212 Mpi2IOUnit8Sensor_t, *pMpi2IOUnit8Sensor_t; 1213 1214 /*defines for IO Unit Page 8 Sensor Flags field */ 1215 #define MPI2_IOUNIT8_SENSOR_FLAGS_T3_ENABLE (0x0008) 1216 #define MPI2_IOUNIT8_SENSOR_FLAGS_T2_ENABLE (0x0004) 1217 #define MPI2_IOUNIT8_SENSOR_FLAGS_T1_ENABLE (0x0002) 1218 #define MPI2_IOUNIT8_SENSOR_FLAGS_T0_ENABLE (0x0001) 1219 1220 /* 1221 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1222 *one and check the value returned for NumSensors at runtime. 1223 */ 1224 #ifndef MPI2_IOUNITPAGE8_SENSOR_ENTRIES 1225 #define MPI2_IOUNITPAGE8_SENSOR_ENTRIES (1) 1226 #endif 1227 1228 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_8 { 1229 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1230 U32 Reserved1; /*0x04 */ 1231 U32 Reserved2; /*0x08 */ 1232 U8 NumSensors; /*0x0C */ 1233 U8 PollingInterval; /*0x0D */ 1234 U16 Reserved3; /*0x0E */ 1235 MPI2_IOUNIT8_SENSOR 1236 Sensor[MPI2_IOUNITPAGE8_SENSOR_ENTRIES];/*0x10 */ 1237 } MPI2_CONFIG_PAGE_IO_UNIT_8, 1238 *PTR_MPI2_CONFIG_PAGE_IO_UNIT_8, 1239 Mpi2IOUnitPage8_t, *pMpi2IOUnitPage8_t; 1240 1241 #define MPI2_IOUNITPAGE8_PAGEVERSION (0x00) 1242 1243 1244 /*IO Unit Page 9 */ 1245 1246 typedef struct _MPI2_IOUNIT9_SENSOR { 1247 U16 CurrentTemperature; /*0x00 */ 1248 U16 Reserved1; /*0x02 */ 1249 U8 Flags; /*0x04 */ 1250 U8 Reserved2; /*0x05 */ 1251 U16 Reserved3; /*0x06 */ 1252 U32 Reserved4; /*0x08 */ 1253 U32 Reserved5; /*0x0C */ 1254 } MPI2_IOUNIT9_SENSOR, *PTR_MPI2_IOUNIT9_SENSOR, 1255 Mpi2IOUnit9Sensor_t, *pMpi2IOUnit9Sensor_t; 1256 1257 /*defines for IO Unit Page 9 Sensor Flags field */ 1258 #define MPI2_IOUNIT9_SENSOR_FLAGS_TEMP_VALID (0x01) 1259 1260 /* 1261 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1262 *one and check the value returned for NumSensors at runtime. 1263 */ 1264 #ifndef MPI2_IOUNITPAGE9_SENSOR_ENTRIES 1265 #define MPI2_IOUNITPAGE9_SENSOR_ENTRIES (1) 1266 #endif 1267 1268 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_9 { 1269 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1270 U32 Reserved1; /*0x04 */ 1271 U32 Reserved2; /*0x08 */ 1272 U8 NumSensors; /*0x0C */ 1273 U8 Reserved4; /*0x0D */ 1274 U16 Reserved3; /*0x0E */ 1275 MPI2_IOUNIT9_SENSOR 1276 Sensor[MPI2_IOUNITPAGE9_SENSOR_ENTRIES];/*0x10 */ 1277 } MPI2_CONFIG_PAGE_IO_UNIT_9, 1278 *PTR_MPI2_CONFIG_PAGE_IO_UNIT_9, 1279 Mpi2IOUnitPage9_t, *pMpi2IOUnitPage9_t; 1280 1281 #define MPI2_IOUNITPAGE9_PAGEVERSION (0x00) 1282 1283 1284 /*IO Unit Page 10 */ 1285 1286 typedef struct _MPI2_IOUNIT10_FUNCTION { 1287 U8 CreditPercent; /*0x00 */ 1288 U8 Reserved1; /*0x01 */ 1289 U16 Reserved2; /*0x02 */ 1290 } MPI2_IOUNIT10_FUNCTION, 1291 *PTR_MPI2_IOUNIT10_FUNCTION, 1292 Mpi2IOUnit10Function_t, 1293 *pMpi2IOUnit10Function_t; 1294 1295 /* 1296 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1297 *one and check the value returned for NumFunctions at runtime. 1298 */ 1299 #ifndef MPI2_IOUNITPAGE10_FUNCTION_ENTRIES 1300 #define MPI2_IOUNITPAGE10_FUNCTION_ENTRIES (1) 1301 #endif 1302 1303 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_10 { 1304 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1305 U8 NumFunctions; /*0x04 */ 1306 U8 Reserved1; /*0x05 */ 1307 U16 Reserved2; /*0x06 */ 1308 U32 Reserved3; /*0x08 */ 1309 U32 Reserved4; /*0x0C */ 1310 MPI2_IOUNIT10_FUNCTION 1311 Function[MPI2_IOUNITPAGE10_FUNCTION_ENTRIES];/*0x10 */ 1312 } MPI2_CONFIG_PAGE_IO_UNIT_10, 1313 *PTR_MPI2_CONFIG_PAGE_IO_UNIT_10, 1314 Mpi2IOUnitPage10_t, *pMpi2IOUnitPage10_t; 1315 1316 #define MPI2_IOUNITPAGE10_PAGEVERSION (0x01) 1317 1318 1319 /* IO Unit Page 11 (for MPI v2.6 and later) */ 1320 1321 typedef struct _MPI26_IOUNIT11_SPINUP_GROUP { 1322 U8 MaxTargetSpinup; /* 0x00 */ 1323 U8 SpinupDelay; /* 0x01 */ 1324 U8 SpinupFlags; /* 0x02 */ 1325 U8 Reserved1; /* 0x03 */ 1326 } MPI26_IOUNIT11_SPINUP_GROUP, 1327 *PTR_MPI26_IOUNIT11_SPINUP_GROUP, 1328 Mpi26IOUnit11SpinupGroup_t, 1329 *pMpi26IOUnit11SpinupGroup_t; 1330 1331 /* defines for IO Unit Page 11 SpinupFlags */ 1332 #define MPI26_IOUNITPAGE11_SPINUP_DISABLE_FLAG (0x01) 1333 1334 1335 /* 1336 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1337 * four and check the value returned for NumPhys at runtime. 1338 */ 1339 #ifndef MPI26_IOUNITPAGE11_PHY_MAX 1340 #define MPI26_IOUNITPAGE11_PHY_MAX (4) 1341 #endif 1342 1343 typedef struct _MPI26_CONFIG_PAGE_IO_UNIT_11 { 1344 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1345 U32 Reserved1; /*0x04 */ 1346 MPI26_IOUNIT11_SPINUP_GROUP SpinupGroupParameters[4]; /*0x08 */ 1347 U32 Reserved2; /*0x18 */ 1348 U32 Reserved3; /*0x1C */ 1349 U32 Reserved4; /*0x20 */ 1350 U8 BootDeviceWaitTime; /*0x24 */ 1351 U8 Reserved5; /*0x25 */ 1352 U16 Reserved6; /*0x26 */ 1353 U8 NumPhys; /*0x28 */ 1354 U8 PEInitialSpinupDelay; /*0x29 */ 1355 U8 PEReplyDelay; /*0x2A */ 1356 U8 Flags; /*0x2B */ 1357 U8 PHY[MPI26_IOUNITPAGE11_PHY_MAX];/*0x2C */ 1358 } MPI26_CONFIG_PAGE_IO_UNIT_11, 1359 *PTR_MPI26_CONFIG_PAGE_IO_UNIT_11, 1360 Mpi26IOUnitPage11_t, 1361 *pMpi26IOUnitPage11_t; 1362 1363 #define MPI26_IOUNITPAGE11_PAGEVERSION (0x00) 1364 1365 /* defines for Flags field */ 1366 #define MPI26_IOUNITPAGE11_FLAGS_AUTO_PORTENABLE (0x01) 1367 1368 /* defines for PHY field */ 1369 #define MPI26_IOUNITPAGE11_PHY_SPINUP_GROUP_MASK (0x03) 1370 1371 1372 1373 1374 1375 1376 /**************************************************************************** 1377 * IOC Config Pages 1378 ****************************************************************************/ 1379 1380 /*IOC Page 0 */ 1381 1382 typedef struct _MPI2_CONFIG_PAGE_IOC_0 { 1383 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1384 U32 Reserved1; /*0x04 */ 1385 U32 Reserved2; /*0x08 */ 1386 U16 VendorID; /*0x0C */ 1387 U16 DeviceID; /*0x0E */ 1388 U8 RevisionID; /*0x10 */ 1389 U8 Reserved3; /*0x11 */ 1390 U16 Reserved4; /*0x12 */ 1391 U32 ClassCode; /*0x14 */ 1392 U16 SubsystemVendorID; /*0x18 */ 1393 U16 SubsystemID; /*0x1A */ 1394 } MPI2_CONFIG_PAGE_IOC_0, 1395 *PTR_MPI2_CONFIG_PAGE_IOC_0, 1396 Mpi2IOCPage0_t, *pMpi2IOCPage0_t; 1397 1398 #define MPI2_IOCPAGE0_PAGEVERSION (0x02) 1399 1400 1401 /*IOC Page 1 */ 1402 1403 typedef struct _MPI2_CONFIG_PAGE_IOC_1 { 1404 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1405 U32 Flags; /*0x04 */ 1406 U32 CoalescingTimeout; /*0x08 */ 1407 U8 CoalescingDepth; /*0x0C */ 1408 U8 PCISlotNum; /*0x0D */ 1409 U8 PCIBusNum; /*0x0E */ 1410 U8 PCIDomainSegment; /*0x0F */ 1411 U32 Reserved1; /*0x10 */ 1412 U32 ProductSpecific; /* 0x14 */ 1413 } MPI2_CONFIG_PAGE_IOC_1, 1414 *PTR_MPI2_CONFIG_PAGE_IOC_1, 1415 Mpi2IOCPage1_t, *pMpi2IOCPage1_t; 1416 1417 #define MPI2_IOCPAGE1_PAGEVERSION (0x05) 1418 1419 /*defines for IOC Page 1 Flags field */ 1420 #define MPI2_IOCPAGE1_REPLY_COALESCING (0x00000001) 1421 1422 #define MPI2_IOCPAGE1_PCISLOTNUM_UNKNOWN (0xFF) 1423 #define MPI2_IOCPAGE1_PCIBUSNUM_UNKNOWN (0xFF) 1424 #define MPI2_IOCPAGE1_PCIDOMAIN_UNKNOWN (0xFF) 1425 1426 /*IOC Page 6 */ 1427 1428 typedef struct _MPI2_CONFIG_PAGE_IOC_6 { 1429 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1430 U32 1431 CapabilitiesFlags; /*0x04 */ 1432 U8 MaxDrivesRAID0; /*0x08 */ 1433 U8 MaxDrivesRAID1; /*0x09 */ 1434 U8 1435 MaxDrivesRAID1E; /*0x0A */ 1436 U8 1437 MaxDrivesRAID10; /*0x0B */ 1438 U8 MinDrivesRAID0; /*0x0C */ 1439 U8 MinDrivesRAID1; /*0x0D */ 1440 U8 1441 MinDrivesRAID1E; /*0x0E */ 1442 U8 1443 MinDrivesRAID10; /*0x0F */ 1444 U32 Reserved1; /*0x10 */ 1445 U8 1446 MaxGlobalHotSpares; /*0x14 */ 1447 U8 MaxPhysDisks; /*0x15 */ 1448 U8 MaxVolumes; /*0x16 */ 1449 U8 MaxConfigs; /*0x17 */ 1450 U8 MaxOCEDisks; /*0x18 */ 1451 U8 Reserved2; /*0x19 */ 1452 U16 Reserved3; /*0x1A */ 1453 U32 1454 SupportedStripeSizeMapRAID0; /*0x1C */ 1455 U32 1456 SupportedStripeSizeMapRAID1E; /*0x20 */ 1457 U32 1458 SupportedStripeSizeMapRAID10; /*0x24 */ 1459 U32 Reserved4; /*0x28 */ 1460 U32 Reserved5; /*0x2C */ 1461 U16 1462 DefaultMetadataSize; /*0x30 */ 1463 U16 Reserved6; /*0x32 */ 1464 U16 1465 MaxBadBlockTableEntries; /*0x34 */ 1466 U16 Reserved7; /*0x36 */ 1467 U32 1468 IRNvsramVersion; /*0x38 */ 1469 } MPI2_CONFIG_PAGE_IOC_6, 1470 *PTR_MPI2_CONFIG_PAGE_IOC_6, 1471 Mpi2IOCPage6_t, *pMpi2IOCPage6_t; 1472 1473 #define MPI2_IOCPAGE6_PAGEVERSION (0x05) 1474 1475 /*defines for IOC Page 6 CapabilitiesFlags */ 1476 #define MPI2_IOCPAGE6_CAP_FLAGS_4K_SECTORS_SUPPORT (0x00000020) 1477 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID10_SUPPORT (0x00000010) 1478 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID1_SUPPORT (0x00000008) 1479 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID1E_SUPPORT (0x00000004) 1480 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID0_SUPPORT (0x00000002) 1481 #define MPI2_IOCPAGE6_CAP_FLAGS_GLOBAL_HOT_SPARE (0x00000001) 1482 1483 1484 /*IOC Page 7 */ 1485 1486 #define MPI2_IOCPAGE7_EVENTMASK_WORDS (4) 1487 1488 typedef struct _MPI2_CONFIG_PAGE_IOC_7 { 1489 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1490 U32 Reserved1; /*0x04 */ 1491 U32 1492 EventMasks[MPI2_IOCPAGE7_EVENTMASK_WORDS];/*0x08 */ 1493 U16 SASBroadcastPrimitiveMasks; /*0x18 */ 1494 U16 SASNotifyPrimitiveMasks; /*0x1A */ 1495 U32 Reserved3; /*0x1C */ 1496 } MPI2_CONFIG_PAGE_IOC_7, 1497 *PTR_MPI2_CONFIG_PAGE_IOC_7, 1498 Mpi2IOCPage7_t, *pMpi2IOCPage7_t; 1499 1500 #define MPI2_IOCPAGE7_PAGEVERSION (0x02) 1501 1502 1503 /*IOC Page 8 */ 1504 1505 typedef struct _MPI2_CONFIG_PAGE_IOC_8 { 1506 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1507 U8 NumDevsPerEnclosure; /*0x04 */ 1508 U8 Reserved1; /*0x05 */ 1509 U16 Reserved2; /*0x06 */ 1510 U16 MaxPersistentEntries; /*0x08 */ 1511 U16 MaxNumPhysicalMappedIDs; /*0x0A */ 1512 U16 Flags; /*0x0C */ 1513 U16 Reserved3; /*0x0E */ 1514 U16 IRVolumeMappingFlags; /*0x10 */ 1515 U16 Reserved4; /*0x12 */ 1516 U32 Reserved5; /*0x14 */ 1517 } MPI2_CONFIG_PAGE_IOC_8, 1518 *PTR_MPI2_CONFIG_PAGE_IOC_8, 1519 Mpi2IOCPage8_t, *pMpi2IOCPage8_t; 1520 1521 #define MPI2_IOCPAGE8_PAGEVERSION (0x00) 1522 1523 /*defines for IOC Page 8 Flags field */ 1524 #define MPI2_IOCPAGE8_FLAGS_DA_START_SLOT_1 (0x00000020) 1525 #define MPI2_IOCPAGE8_FLAGS_RESERVED_TARGETID_0 (0x00000010) 1526 1527 #define MPI2_IOCPAGE8_FLAGS_MASK_MAPPING_MODE (0x0000000E) 1528 #define MPI2_IOCPAGE8_FLAGS_DEVICE_PERSISTENCE_MAPPING (0x00000000) 1529 #define MPI2_IOCPAGE8_FLAGS_ENCLOSURE_SLOT_MAPPING (0x00000002) 1530 1531 #define MPI2_IOCPAGE8_FLAGS_DISABLE_PERSISTENT_MAPPING (0x00000001) 1532 #define MPI2_IOCPAGE8_FLAGS_ENABLE_PERSISTENT_MAPPING (0x00000000) 1533 1534 /*defines for IOC Page 8 IRVolumeMappingFlags */ 1535 #define MPI2_IOCPAGE8_IRFLAGS_MASK_VOLUME_MAPPING_MODE (0x00000003) 1536 #define MPI2_IOCPAGE8_IRFLAGS_LOW_VOLUME_MAPPING (0x00000000) 1537 #define MPI2_IOCPAGE8_IRFLAGS_HIGH_VOLUME_MAPPING (0x00000001) 1538 1539 1540 /**************************************************************************** 1541 * BIOS Config Pages 1542 ****************************************************************************/ 1543 1544 /*BIOS Page 1 */ 1545 1546 typedef struct _MPI2_CONFIG_PAGE_BIOS_1 { 1547 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1548 U32 BiosOptions; /*0x04 */ 1549 U32 IOCSettings; /*0x08 */ 1550 U8 SSUTimeout; /*0x0C */ 1551 U8 MaxEnclosureLevel; /*0x0D */ 1552 U16 Reserved2; /*0x0E */ 1553 U32 DeviceSettings; /*0x10 */ 1554 U16 NumberOfDevices; /*0x14 */ 1555 U16 UEFIVersion; /*0x16 */ 1556 U16 IOTimeoutBlockDevicesNonRM; /*0x18 */ 1557 U16 IOTimeoutSequential; /*0x1A */ 1558 U16 IOTimeoutOther; /*0x1C */ 1559 U16 IOTimeoutBlockDevicesRM; /*0x1E */ 1560 } MPI2_CONFIG_PAGE_BIOS_1, 1561 *PTR_MPI2_CONFIG_PAGE_BIOS_1, 1562 Mpi2BiosPage1_t, *pMpi2BiosPage1_t; 1563 1564 #define MPI2_BIOSPAGE1_PAGEVERSION (0x07) 1565 1566 /*values for BIOS Page 1 BiosOptions field */ 1567 #define MPI2_BIOSPAGE1_OPTIONS_BOOT_LIST_ADD_ALT_BOOT_DEVICE (0x00008000) 1568 #define MPI2_BIOSPAGE1_OPTIONS_ADVANCED_CONFIG (0x00004000) 1569 1570 #define MPI2_BIOSPAGE1_OPTIONS_PNS_MASK (0x00003800) 1571 #define MPI2_BIOSPAGE1_OPTIONS_PNS_PBDHL (0x00000000) 1572 #define MPI2_BIOSPAGE1_OPTIONS_PNS_ENCSLOSURE (0x00000800) 1573 #define MPI2_BIOSPAGE1_OPTIONS_PNS_LWWID (0x00001000) 1574 #define MPI2_BIOSPAGE1_OPTIONS_PNS_PSENS (0x00001800) 1575 #define MPI2_BIOSPAGE1_OPTIONS_PNS_ESPHY (0x00002000) 1576 1577 #define MPI2_BIOSPAGE1_OPTIONS_X86_DISABLE_BIOS (0x00000400) 1578 1579 #define MPI2_BIOSPAGE1_OPTIONS_MASK_REGISTRATION_UEFI_BSD (0x00000300) 1580 #define MPI2_BIOSPAGE1_OPTIONS_USE_BIT0_REGISTRATION_UEFI_BSD (0x00000000) 1581 #define MPI2_BIOSPAGE1_OPTIONS_FULL_REGISTRATION_UEFI_BSD (0x00000100) 1582 #define MPI2_BIOSPAGE1_OPTIONS_ADAPTER_REGISTRATION_UEFI_BSD (0x00000200) 1583 #define MPI2_BIOSPAGE1_OPTIONS_DISABLE_REGISTRATION_UEFI_BSD (0x00000300) 1584 1585 #define MPI2_BIOSPAGE1_OPTIONS_MASK_OEM_ID (0x000000F0) 1586 #define MPI2_BIOSPAGE1_OPTIONS_LSI_OEM_ID (0x00000000) 1587 1588 #define MPI2_BIOSPAGE1_OPTIONS_MASK_UEFI_HII_REGISTRATION (0x00000006) 1589 #define MPI2_BIOSPAGE1_OPTIONS_ENABLE_UEFI_HII (0x00000000) 1590 #define MPI2_BIOSPAGE1_OPTIONS_DISABLE_UEFI_HII (0x00000002) 1591 #define MPI2_BIOSPAGE1_OPTIONS_VERSION_CHECK_UEFI_HII (0x00000004) 1592 1593 #define MPI2_BIOSPAGE1_OPTIONS_DISABLE_BIOS (0x00000001) 1594 1595 /*values for BIOS Page 1 IOCSettings field */ 1596 #define MPI2_BIOSPAGE1_IOCSET_MASK_BOOT_PREFERENCE (0x00030000) 1597 #define MPI2_BIOSPAGE1_IOCSET_ENCLOSURE_SLOT_BOOT (0x00000000) 1598 #define MPI2_BIOSPAGE1_IOCSET_SAS_ADDRESS_BOOT (0x00010000) 1599 1600 #define MPI2_BIOSPAGE1_IOCSET_MASK_RM_SETTING (0x000000C0) 1601 #define MPI2_BIOSPAGE1_IOCSET_NONE_RM_SETTING (0x00000000) 1602 #define MPI2_BIOSPAGE1_IOCSET_BOOT_RM_SETTING (0x00000040) 1603 #define MPI2_BIOSPAGE1_IOCSET_MEDIA_RM_SETTING (0x00000080) 1604 1605 #define MPI2_BIOSPAGE1_IOCSET_MASK_ADAPTER_SUPPORT (0x00000030) 1606 #define MPI2_BIOSPAGE1_IOCSET_NO_SUPPORT (0x00000000) 1607 #define MPI2_BIOSPAGE1_IOCSET_BIOS_SUPPORT (0x00000010) 1608 #define MPI2_BIOSPAGE1_IOCSET_OS_SUPPORT (0x00000020) 1609 #define MPI2_BIOSPAGE1_IOCSET_ALL_SUPPORT (0x00000030) 1610 1611 #define MPI2_BIOSPAGE1_IOCSET_ALTERNATE_CHS (0x00000008) 1612 1613 /*values for BIOS Page 1 DeviceSettings field */ 1614 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_SMART_POLLING (0x00000010) 1615 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_SEQ_LUN (0x00000008) 1616 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_RM_LUN (0x00000004) 1617 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_NON_RM_LUN (0x00000002) 1618 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_OTHER_LUN (0x00000001) 1619 1620 /*defines for BIOS Page 1 UEFIVersion field */ 1621 #define MPI2_BIOSPAGE1_UEFI_VER_MAJOR_MASK (0xFF00) 1622 #define MPI2_BIOSPAGE1_UEFI_VER_MAJOR_SHIFT (8) 1623 #define MPI2_BIOSPAGE1_UEFI_VER_MINOR_MASK (0x00FF) 1624 #define MPI2_BIOSPAGE1_UEFI_VER_MINOR_SHIFT (0) 1625 1626 1627 1628 /*BIOS Page 2 */ 1629 1630 typedef struct _MPI2_BOOT_DEVICE_ADAPTER_ORDER { 1631 U32 Reserved1; /*0x00 */ 1632 U32 Reserved2; /*0x04 */ 1633 U32 Reserved3; /*0x08 */ 1634 U32 Reserved4; /*0x0C */ 1635 U32 Reserved5; /*0x10 */ 1636 U32 Reserved6; /*0x14 */ 1637 } MPI2_BOOT_DEVICE_ADAPTER_ORDER, 1638 *PTR_MPI2_BOOT_DEVICE_ADAPTER_ORDER, 1639 Mpi2BootDeviceAdapterOrder_t, 1640 *pMpi2BootDeviceAdapterOrder_t; 1641 1642 typedef struct _MPI2_BOOT_DEVICE_SAS_WWID { 1643 U64 SASAddress; /*0x00 */ 1644 U8 LUN[8]; /*0x08 */ 1645 U32 Reserved1; /*0x10 */ 1646 U32 Reserved2; /*0x14 */ 1647 } MPI2_BOOT_DEVICE_SAS_WWID, 1648 *PTR_MPI2_BOOT_DEVICE_SAS_WWID, 1649 Mpi2BootDeviceSasWwid_t, 1650 *pMpi2BootDeviceSasWwid_t; 1651 1652 typedef struct _MPI2_BOOT_DEVICE_ENCLOSURE_SLOT { 1653 U64 EnclosureLogicalID; /*0x00 */ 1654 U32 Reserved1; /*0x08 */ 1655 U32 Reserved2; /*0x0C */ 1656 U16 SlotNumber; /*0x10 */ 1657 U16 Reserved3; /*0x12 */ 1658 U32 Reserved4; /*0x14 */ 1659 } MPI2_BOOT_DEVICE_ENCLOSURE_SLOT, 1660 *PTR_MPI2_BOOT_DEVICE_ENCLOSURE_SLOT, 1661 Mpi2BootDeviceEnclosureSlot_t, 1662 *pMpi2BootDeviceEnclosureSlot_t; 1663 1664 typedef struct _MPI2_BOOT_DEVICE_DEVICE_NAME { 1665 U64 DeviceName; /*0x00 */ 1666 U8 LUN[8]; /*0x08 */ 1667 U32 Reserved1; /*0x10 */ 1668 U32 Reserved2; /*0x14 */ 1669 } MPI2_BOOT_DEVICE_DEVICE_NAME, 1670 *PTR_MPI2_BOOT_DEVICE_DEVICE_NAME, 1671 Mpi2BootDeviceDeviceName_t, 1672 *pMpi2BootDeviceDeviceName_t; 1673 1674 typedef union _MPI2_MPI2_BIOSPAGE2_BOOT_DEVICE { 1675 MPI2_BOOT_DEVICE_ADAPTER_ORDER AdapterOrder; 1676 MPI2_BOOT_DEVICE_SAS_WWID SasWwid; 1677 MPI2_BOOT_DEVICE_ENCLOSURE_SLOT EnclosureSlot; 1678 MPI2_BOOT_DEVICE_DEVICE_NAME DeviceName; 1679 } MPI2_BIOSPAGE2_BOOT_DEVICE, 1680 *PTR_MPI2_BIOSPAGE2_BOOT_DEVICE, 1681 Mpi2BiosPage2BootDevice_t, 1682 *pMpi2BiosPage2BootDevice_t; 1683 1684 typedef struct _MPI2_CONFIG_PAGE_BIOS_2 { 1685 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1686 U32 Reserved1; /*0x04 */ 1687 U32 Reserved2; /*0x08 */ 1688 U32 Reserved3; /*0x0C */ 1689 U32 Reserved4; /*0x10 */ 1690 U32 Reserved5; /*0x14 */ 1691 U32 Reserved6; /*0x18 */ 1692 U8 ReqBootDeviceForm; /*0x1C */ 1693 U8 Reserved7; /*0x1D */ 1694 U16 Reserved8; /*0x1E */ 1695 MPI2_BIOSPAGE2_BOOT_DEVICE RequestedBootDevice; /*0x20 */ 1696 U8 ReqAltBootDeviceForm; /*0x38 */ 1697 U8 Reserved9; /*0x39 */ 1698 U16 Reserved10; /*0x3A */ 1699 MPI2_BIOSPAGE2_BOOT_DEVICE RequestedAltBootDevice; /*0x3C */ 1700 U8 CurrentBootDeviceForm; /*0x58 */ 1701 U8 Reserved11; /*0x59 */ 1702 U16 Reserved12; /*0x5A */ 1703 MPI2_BIOSPAGE2_BOOT_DEVICE CurrentBootDevice; /*0x58 */ 1704 } MPI2_CONFIG_PAGE_BIOS_2, *PTR_MPI2_CONFIG_PAGE_BIOS_2, 1705 Mpi2BiosPage2_t, *pMpi2BiosPage2_t; 1706 1707 #define MPI2_BIOSPAGE2_PAGEVERSION (0x04) 1708 1709 /*values for BIOS Page 2 BootDeviceForm fields */ 1710 #define MPI2_BIOSPAGE2_FORM_MASK (0x0F) 1711 #define MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED (0x00) 1712 #define MPI2_BIOSPAGE2_FORM_SAS_WWID (0x05) 1713 #define MPI2_BIOSPAGE2_FORM_ENCLOSURE_SLOT (0x06) 1714 #define MPI2_BIOSPAGE2_FORM_DEVICE_NAME (0x07) 1715 1716 1717 /*BIOS Page 3 */ 1718 1719 #define MPI2_BIOSPAGE3_NUM_ADAPTER (4) 1720 1721 typedef struct _MPI2_ADAPTER_INFO { 1722 U8 PciBusNumber; /*0x00 */ 1723 U8 PciDeviceAndFunctionNumber; /*0x01 */ 1724 U16 AdapterFlags; /*0x02 */ 1725 } MPI2_ADAPTER_INFO, *PTR_MPI2_ADAPTER_INFO, 1726 Mpi2AdapterInfo_t, *pMpi2AdapterInfo_t; 1727 1728 #define MPI2_ADAPTER_INFO_FLAGS_EMBEDDED (0x0001) 1729 #define MPI2_ADAPTER_INFO_FLAGS_INIT_STATUS (0x0002) 1730 1731 typedef struct _MPI2_ADAPTER_ORDER_AUX { 1732 U64 WWID; /* 0x00 */ 1733 U32 Reserved1; /* 0x08 */ 1734 U32 Reserved2; /* 0x0C */ 1735 } MPI2_ADAPTER_ORDER_AUX, *PTR_MPI2_ADAPTER_ORDER_AUX, 1736 Mpi2AdapterOrderAux_t, *pMpi2AdapterOrderAux_t; 1737 1738 1739 typedef struct _MPI2_CONFIG_PAGE_BIOS_3 { 1740 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1741 U32 GlobalFlags; /*0x04 */ 1742 U32 BiosVersion; /*0x08 */ 1743 MPI2_ADAPTER_INFO AdapterOrder[MPI2_BIOSPAGE3_NUM_ADAPTER]; 1744 U32 Reserved1; /*0x1C */ 1745 MPI2_ADAPTER_ORDER_AUX AdapterOrderAux[MPI2_BIOSPAGE3_NUM_ADAPTER]; 1746 } MPI2_CONFIG_PAGE_BIOS_3, 1747 *PTR_MPI2_CONFIG_PAGE_BIOS_3, 1748 Mpi2BiosPage3_t, *pMpi2BiosPage3_t; 1749 1750 #define MPI2_BIOSPAGE3_PAGEVERSION (0x01) 1751 1752 /*values for BIOS Page 3 GlobalFlags */ 1753 #define MPI2_BIOSPAGE3_FLAGS_PAUSE_ON_ERROR (0x00000002) 1754 #define MPI2_BIOSPAGE3_FLAGS_VERBOSE_ENABLE (0x00000004) 1755 #define MPI2_BIOSPAGE3_FLAGS_HOOK_INT_40_DISABLE (0x00000010) 1756 1757 #define MPI2_BIOSPAGE3_FLAGS_DEV_LIST_DISPLAY_MASK (0x000000E0) 1758 #define MPI2_BIOSPAGE3_FLAGS_INSTALLED_DEV_DISPLAY (0x00000000) 1759 #define MPI2_BIOSPAGE3_FLAGS_ADAPTER_DISPLAY (0x00000020) 1760 #define MPI2_BIOSPAGE3_FLAGS_ADAPTER_DEV_DISPLAY (0x00000040) 1761 1762 1763 /*BIOS Page 4 */ 1764 1765 /* 1766 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1767 *one and check the value returned for NumPhys at runtime. 1768 */ 1769 #ifndef MPI2_BIOS_PAGE_4_PHY_ENTRIES 1770 #define MPI2_BIOS_PAGE_4_PHY_ENTRIES (1) 1771 #endif 1772 1773 typedef struct _MPI2_BIOS4_ENTRY { 1774 U64 ReassignmentWWID; /*0x00 */ 1775 U64 ReassignmentDeviceName; /*0x08 */ 1776 } MPI2_BIOS4_ENTRY, *PTR_MPI2_BIOS4_ENTRY, 1777 Mpi2MBios4Entry_t, *pMpi2Bios4Entry_t; 1778 1779 typedef struct _MPI2_CONFIG_PAGE_BIOS_4 { 1780 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1781 U8 NumPhys; /*0x04 */ 1782 U8 Reserved1; /*0x05 */ 1783 U16 Reserved2; /*0x06 */ 1784 MPI2_BIOS4_ENTRY 1785 Phy[MPI2_BIOS_PAGE_4_PHY_ENTRIES]; /*0x08 */ 1786 } MPI2_CONFIG_PAGE_BIOS_4, *PTR_MPI2_CONFIG_PAGE_BIOS_4, 1787 Mpi2BiosPage4_t, *pMpi2BiosPage4_t; 1788 1789 #define MPI2_BIOSPAGE4_PAGEVERSION (0x01) 1790 1791 1792 /**************************************************************************** 1793 * RAID Volume Config Pages 1794 ****************************************************************************/ 1795 1796 /*RAID Volume Page 0 */ 1797 1798 typedef struct _MPI2_RAIDVOL0_PHYS_DISK { 1799 U8 RAIDSetNum; /*0x00 */ 1800 U8 PhysDiskMap; /*0x01 */ 1801 U8 PhysDiskNum; /*0x02 */ 1802 U8 Reserved; /*0x03 */ 1803 } MPI2_RAIDVOL0_PHYS_DISK, *PTR_MPI2_RAIDVOL0_PHYS_DISK, 1804 Mpi2RaidVol0PhysDisk_t, *pMpi2RaidVol0PhysDisk_t; 1805 1806 /*defines for the PhysDiskMap field */ 1807 #define MPI2_RAIDVOL0_PHYSDISK_PRIMARY (0x01) 1808 #define MPI2_RAIDVOL0_PHYSDISK_SECONDARY (0x02) 1809 1810 typedef struct _MPI2_RAIDVOL0_SETTINGS { 1811 U16 Settings; /*0x00 */ 1812 U8 HotSparePool; /*0x01 */ 1813 U8 Reserved; /*0x02 */ 1814 } MPI2_RAIDVOL0_SETTINGS, *PTR_MPI2_RAIDVOL0_SETTINGS, 1815 Mpi2RaidVol0Settings_t, 1816 *pMpi2RaidVol0Settings_t; 1817 1818 /*RAID Volume Page 0 HotSparePool defines, also used in RAID Physical Disk */ 1819 #define MPI2_RAID_HOT_SPARE_POOL_0 (0x01) 1820 #define MPI2_RAID_HOT_SPARE_POOL_1 (0x02) 1821 #define MPI2_RAID_HOT_SPARE_POOL_2 (0x04) 1822 #define MPI2_RAID_HOT_SPARE_POOL_3 (0x08) 1823 #define MPI2_RAID_HOT_SPARE_POOL_4 (0x10) 1824 #define MPI2_RAID_HOT_SPARE_POOL_5 (0x20) 1825 #define MPI2_RAID_HOT_SPARE_POOL_6 (0x40) 1826 #define MPI2_RAID_HOT_SPARE_POOL_7 (0x80) 1827 1828 /*RAID Volume Page 0 VolumeSettings defines */ 1829 #define MPI2_RAIDVOL0_SETTING_USE_PRODUCT_ID_SUFFIX (0x0008) 1830 #define MPI2_RAIDVOL0_SETTING_AUTO_CONFIG_HSWAP_DISABLE (0x0004) 1831 1832 #define MPI2_RAIDVOL0_SETTING_MASK_WRITE_CACHING (0x0003) 1833 #define MPI2_RAIDVOL0_SETTING_UNCHANGED (0x0000) 1834 #define MPI2_RAIDVOL0_SETTING_DISABLE_WRITE_CACHING (0x0001) 1835 #define MPI2_RAIDVOL0_SETTING_ENABLE_WRITE_CACHING (0x0002) 1836 1837 /* 1838 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1839 *one and check the value returned for NumPhysDisks at runtime. 1840 */ 1841 #ifndef MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX 1842 #define MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX (1) 1843 #endif 1844 1845 typedef struct _MPI2_CONFIG_PAGE_RAID_VOL_0 { 1846 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1847 U16 DevHandle; /*0x04 */ 1848 U8 VolumeState; /*0x06 */ 1849 U8 VolumeType; /*0x07 */ 1850 U32 VolumeStatusFlags; /*0x08 */ 1851 MPI2_RAIDVOL0_SETTINGS VolumeSettings; /*0x0C */ 1852 U64 MaxLBA; /*0x10 */ 1853 U32 StripeSize; /*0x18 */ 1854 U16 BlockSize; /*0x1C */ 1855 U16 Reserved1; /*0x1E */ 1856 U8 SupportedPhysDisks;/*0x20 */ 1857 U8 ResyncRate; /*0x21 */ 1858 U16 DataScrubDuration; /*0x22 */ 1859 U8 NumPhysDisks; /*0x24 */ 1860 U8 Reserved2; /*0x25 */ 1861 U8 Reserved3; /*0x26 */ 1862 U8 InactiveStatus; /*0x27 */ 1863 MPI2_RAIDVOL0_PHYS_DISK 1864 PhysDisk[MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX]; /*0x28 */ 1865 } MPI2_CONFIG_PAGE_RAID_VOL_0, 1866 *PTR_MPI2_CONFIG_PAGE_RAID_VOL_0, 1867 Mpi2RaidVolPage0_t, *pMpi2RaidVolPage0_t; 1868 1869 #define MPI2_RAIDVOLPAGE0_PAGEVERSION (0x0A) 1870 1871 /*values for RAID VolumeState */ 1872 #define MPI2_RAID_VOL_STATE_MISSING (0x00) 1873 #define MPI2_RAID_VOL_STATE_FAILED (0x01) 1874 #define MPI2_RAID_VOL_STATE_INITIALIZING (0x02) 1875 #define MPI2_RAID_VOL_STATE_ONLINE (0x03) 1876 #define MPI2_RAID_VOL_STATE_DEGRADED (0x04) 1877 #define MPI2_RAID_VOL_STATE_OPTIMAL (0x05) 1878 1879 /*values for RAID VolumeType */ 1880 #define MPI2_RAID_VOL_TYPE_RAID0 (0x00) 1881 #define MPI2_RAID_VOL_TYPE_RAID1E (0x01) 1882 #define MPI2_RAID_VOL_TYPE_RAID1 (0x02) 1883 #define MPI2_RAID_VOL_TYPE_RAID10 (0x05) 1884 #define MPI2_RAID_VOL_TYPE_UNKNOWN (0xFF) 1885 1886 /*values for RAID Volume Page 0 VolumeStatusFlags field */ 1887 #define MPI2_RAIDVOL0_STATUS_FLAG_PENDING_RESYNC (0x02000000) 1888 #define MPI2_RAIDVOL0_STATUS_FLAG_BACKG_INIT_PENDING (0x01000000) 1889 #define MPI2_RAIDVOL0_STATUS_FLAG_MDC_PENDING (0x00800000) 1890 #define MPI2_RAIDVOL0_STATUS_FLAG_USER_CONSIST_PENDING (0x00400000) 1891 #define MPI2_RAIDVOL0_STATUS_FLAG_MAKE_DATA_CONSISTENT (0x00200000) 1892 #define MPI2_RAIDVOL0_STATUS_FLAG_DATA_SCRUB (0x00100000) 1893 #define MPI2_RAIDVOL0_STATUS_FLAG_CONSISTENCY_CHECK (0x00080000) 1894 #define MPI2_RAIDVOL0_STATUS_FLAG_CAPACITY_EXPANSION (0x00040000) 1895 #define MPI2_RAIDVOL0_STATUS_FLAG_BACKGROUND_INIT (0x00020000) 1896 #define MPI2_RAIDVOL0_STATUS_FLAG_RESYNC_IN_PROGRESS (0x00010000) 1897 #define MPI2_RAIDVOL0_STATUS_FLAG_VOL_NOT_CONSISTENT (0x00000080) 1898 #define MPI2_RAIDVOL0_STATUS_FLAG_OCE_ALLOWED (0x00000040) 1899 #define MPI2_RAIDVOL0_STATUS_FLAG_BGI_COMPLETE (0x00000020) 1900 #define MPI2_RAIDVOL0_STATUS_FLAG_1E_OFFSET_MIRROR (0x00000000) 1901 #define MPI2_RAIDVOL0_STATUS_FLAG_1E_ADJACENT_MIRROR (0x00000010) 1902 #define MPI2_RAIDVOL0_STATUS_FLAG_BAD_BLOCK_TABLE_FULL (0x00000008) 1903 #define MPI2_RAIDVOL0_STATUS_FLAG_VOLUME_INACTIVE (0x00000004) 1904 #define MPI2_RAIDVOL0_STATUS_FLAG_QUIESCED (0x00000002) 1905 #define MPI2_RAIDVOL0_STATUS_FLAG_ENABLED (0x00000001) 1906 1907 /*values for RAID Volume Page 0 SupportedPhysDisks field */ 1908 #define MPI2_RAIDVOL0_SUPPORT_SOLID_STATE_DISKS (0x08) 1909 #define MPI2_RAIDVOL0_SUPPORT_HARD_DISKS (0x04) 1910 #define MPI2_RAIDVOL0_SUPPORT_SAS_PROTOCOL (0x02) 1911 #define MPI2_RAIDVOL0_SUPPORT_SATA_PROTOCOL (0x01) 1912 1913 /*values for RAID Volume Page 0 InactiveStatus field */ 1914 #define MPI2_RAIDVOLPAGE0_UNKNOWN_INACTIVE (0x00) 1915 #define MPI2_RAIDVOLPAGE0_STALE_METADATA_INACTIVE (0x01) 1916 #define MPI2_RAIDVOLPAGE0_FOREIGN_VOLUME_INACTIVE (0x02) 1917 #define MPI2_RAIDVOLPAGE0_INSUFFICIENT_RESOURCE_INACTIVE (0x03) 1918 #define MPI2_RAIDVOLPAGE0_CLONE_VOLUME_INACTIVE (0x04) 1919 #define MPI2_RAIDVOLPAGE0_INSUFFICIENT_METADATA_INACTIVE (0x05) 1920 #define MPI2_RAIDVOLPAGE0_PREVIOUSLY_DELETED (0x06) 1921 1922 1923 /*RAID Volume Page 1 */ 1924 1925 typedef struct _MPI2_CONFIG_PAGE_RAID_VOL_1 { 1926 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1927 U16 DevHandle; /*0x04 */ 1928 U16 Reserved0; /*0x06 */ 1929 U8 GUID[24]; /*0x08 */ 1930 U8 Name[16]; /*0x20 */ 1931 U64 WWID; /*0x30 */ 1932 U32 Reserved1; /*0x38 */ 1933 U32 Reserved2; /*0x3C */ 1934 } MPI2_CONFIG_PAGE_RAID_VOL_1, 1935 *PTR_MPI2_CONFIG_PAGE_RAID_VOL_1, 1936 Mpi2RaidVolPage1_t, *pMpi2RaidVolPage1_t; 1937 1938 #define MPI2_RAIDVOLPAGE1_PAGEVERSION (0x03) 1939 1940 1941 /**************************************************************************** 1942 * RAID Physical Disk Config Pages 1943 ****************************************************************************/ 1944 1945 /*RAID Physical Disk Page 0 */ 1946 1947 typedef struct _MPI2_RAIDPHYSDISK0_SETTINGS { 1948 U16 Reserved1; /*0x00 */ 1949 U8 HotSparePool; /*0x02 */ 1950 U8 Reserved2; /*0x03 */ 1951 } MPI2_RAIDPHYSDISK0_SETTINGS, 1952 *PTR_MPI2_RAIDPHYSDISK0_SETTINGS, 1953 Mpi2RaidPhysDisk0Settings_t, 1954 *pMpi2RaidPhysDisk0Settings_t; 1955 1956 /*use MPI2_RAID_HOT_SPARE_POOL_ defines for the HotSparePool field */ 1957 1958 typedef struct _MPI2_RAIDPHYSDISK0_INQUIRY_DATA { 1959 U8 VendorID[8]; /*0x00 */ 1960 U8 ProductID[16]; /*0x08 */ 1961 U8 ProductRevLevel[4]; /*0x18 */ 1962 U8 SerialNum[32]; /*0x1C */ 1963 } MPI2_RAIDPHYSDISK0_INQUIRY_DATA, 1964 *PTR_MPI2_RAIDPHYSDISK0_INQUIRY_DATA, 1965 Mpi2RaidPhysDisk0InquiryData_t, 1966 *pMpi2RaidPhysDisk0InquiryData_t; 1967 1968 typedef struct _MPI2_CONFIG_PAGE_RD_PDISK_0 { 1969 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1970 U16 DevHandle; /*0x04 */ 1971 U8 Reserved1; /*0x06 */ 1972 U8 PhysDiskNum; /*0x07 */ 1973 MPI2_RAIDPHYSDISK0_SETTINGS PhysDiskSettings; /*0x08 */ 1974 U32 Reserved2; /*0x0C */ 1975 MPI2_RAIDPHYSDISK0_INQUIRY_DATA InquiryData; /*0x10 */ 1976 U32 Reserved3; /*0x4C */ 1977 U8 PhysDiskState; /*0x50 */ 1978 U8 OfflineReason; /*0x51 */ 1979 U8 IncompatibleReason; /*0x52 */ 1980 U8 PhysDiskAttributes; /*0x53 */ 1981 U32 PhysDiskStatusFlags;/*0x54 */ 1982 U64 DeviceMaxLBA; /*0x58 */ 1983 U64 HostMaxLBA; /*0x60 */ 1984 U64 CoercedMaxLBA; /*0x68 */ 1985 U16 BlockSize; /*0x70 */ 1986 U16 Reserved5; /*0x72 */ 1987 U32 Reserved6; /*0x74 */ 1988 } MPI2_CONFIG_PAGE_RD_PDISK_0, 1989 *PTR_MPI2_CONFIG_PAGE_RD_PDISK_0, 1990 Mpi2RaidPhysDiskPage0_t, 1991 *pMpi2RaidPhysDiskPage0_t; 1992 1993 #define MPI2_RAIDPHYSDISKPAGE0_PAGEVERSION (0x05) 1994 1995 /*PhysDiskState defines */ 1996 #define MPI2_RAID_PD_STATE_NOT_CONFIGURED (0x00) 1997 #define MPI2_RAID_PD_STATE_NOT_COMPATIBLE (0x01) 1998 #define MPI2_RAID_PD_STATE_OFFLINE (0x02) 1999 #define MPI2_RAID_PD_STATE_ONLINE (0x03) 2000 #define MPI2_RAID_PD_STATE_HOT_SPARE (0x04) 2001 #define MPI2_RAID_PD_STATE_DEGRADED (0x05) 2002 #define MPI2_RAID_PD_STATE_REBUILDING (0x06) 2003 #define MPI2_RAID_PD_STATE_OPTIMAL (0x07) 2004 2005 /*OfflineReason defines */ 2006 #define MPI2_PHYSDISK0_ONLINE (0x00) 2007 #define MPI2_PHYSDISK0_OFFLINE_MISSING (0x01) 2008 #define MPI2_PHYSDISK0_OFFLINE_FAILED (0x03) 2009 #define MPI2_PHYSDISK0_OFFLINE_INITIALIZING (0x04) 2010 #define MPI2_PHYSDISK0_OFFLINE_REQUESTED (0x05) 2011 #define MPI2_PHYSDISK0_OFFLINE_FAILED_REQUESTED (0x06) 2012 #define MPI2_PHYSDISK0_OFFLINE_OTHER (0xFF) 2013 2014 /*IncompatibleReason defines */ 2015 #define MPI2_PHYSDISK0_COMPATIBLE (0x00) 2016 #define MPI2_PHYSDISK0_INCOMPATIBLE_PROTOCOL (0x01) 2017 #define MPI2_PHYSDISK0_INCOMPATIBLE_BLOCKSIZE (0x02) 2018 #define MPI2_PHYSDISK0_INCOMPATIBLE_MAX_LBA (0x03) 2019 #define MPI2_PHYSDISK0_INCOMPATIBLE_SATA_EXTENDED_CMD (0x04) 2020 #define MPI2_PHYSDISK0_INCOMPATIBLE_REMOVEABLE_MEDIA (0x05) 2021 #define MPI2_PHYSDISK0_INCOMPATIBLE_MEDIA_TYPE (0x06) 2022 #define MPI2_PHYSDISK0_INCOMPATIBLE_UNKNOWN (0xFF) 2023 2024 /*PhysDiskAttributes defines */ 2025 #define MPI2_PHYSDISK0_ATTRIB_MEDIA_MASK (0x0C) 2026 #define MPI2_PHYSDISK0_ATTRIB_SOLID_STATE_DRIVE (0x08) 2027 #define MPI2_PHYSDISK0_ATTRIB_HARD_DISK_DRIVE (0x04) 2028 2029 #define MPI2_PHYSDISK0_ATTRIB_PROTOCOL_MASK (0x03) 2030 #define MPI2_PHYSDISK0_ATTRIB_SAS_PROTOCOL (0x02) 2031 #define MPI2_PHYSDISK0_ATTRIB_SATA_PROTOCOL (0x01) 2032 2033 /*PhysDiskStatusFlags defines */ 2034 #define MPI2_PHYSDISK0_STATUS_FLAG_NOT_CERTIFIED (0x00000040) 2035 #define MPI2_PHYSDISK0_STATUS_FLAG_OCE_TARGET (0x00000020) 2036 #define MPI2_PHYSDISK0_STATUS_FLAG_WRITE_CACHE_ENABLED (0x00000010) 2037 #define MPI2_PHYSDISK0_STATUS_FLAG_OPTIMAL_PREVIOUS (0x00000000) 2038 #define MPI2_PHYSDISK0_STATUS_FLAG_NOT_OPTIMAL_PREVIOUS (0x00000008) 2039 #define MPI2_PHYSDISK0_STATUS_FLAG_INACTIVE_VOLUME (0x00000004) 2040 #define MPI2_PHYSDISK0_STATUS_FLAG_QUIESCED (0x00000002) 2041 #define MPI2_PHYSDISK0_STATUS_FLAG_OUT_OF_SYNC (0x00000001) 2042 2043 2044 /*RAID Physical Disk Page 1 */ 2045 2046 /* 2047 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2048 *one and check the value returned for NumPhysDiskPaths at runtime. 2049 */ 2050 #ifndef MPI2_RAID_PHYS_DISK1_PATH_MAX 2051 #define MPI2_RAID_PHYS_DISK1_PATH_MAX (1) 2052 #endif 2053 2054 typedef struct _MPI2_RAIDPHYSDISK1_PATH { 2055 U16 DevHandle; /*0x00 */ 2056 U16 Reserved1; /*0x02 */ 2057 U64 WWID; /*0x04 */ 2058 U64 OwnerWWID; /*0x0C */ 2059 U8 OwnerIdentifier; /*0x14 */ 2060 U8 Reserved2; /*0x15 */ 2061 U16 Flags; /*0x16 */ 2062 } MPI2_RAIDPHYSDISK1_PATH, *PTR_MPI2_RAIDPHYSDISK1_PATH, 2063 Mpi2RaidPhysDisk1Path_t, 2064 *pMpi2RaidPhysDisk1Path_t; 2065 2066 /*RAID Physical Disk Page 1 Physical Disk Path Flags field defines */ 2067 #define MPI2_RAID_PHYSDISK1_FLAG_PRIMARY (0x0004) 2068 #define MPI2_RAID_PHYSDISK1_FLAG_BROKEN (0x0002) 2069 #define MPI2_RAID_PHYSDISK1_FLAG_INVALID (0x0001) 2070 2071 typedef struct _MPI2_CONFIG_PAGE_RD_PDISK_1 { 2072 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 2073 U8 NumPhysDiskPaths; /*0x04 */ 2074 U8 PhysDiskNum; /*0x05 */ 2075 U16 Reserved1; /*0x06 */ 2076 U32 Reserved2; /*0x08 */ 2077 MPI2_RAIDPHYSDISK1_PATH 2078 PhysicalDiskPath[MPI2_RAID_PHYS_DISK1_PATH_MAX];/*0x0C */ 2079 } MPI2_CONFIG_PAGE_RD_PDISK_1, 2080 *PTR_MPI2_CONFIG_PAGE_RD_PDISK_1, 2081 Mpi2RaidPhysDiskPage1_t, 2082 *pMpi2RaidPhysDiskPage1_t; 2083 2084 #define MPI2_RAIDPHYSDISKPAGE1_PAGEVERSION (0x02) 2085 2086 2087 /**************************************************************************** 2088 * values for fields used by several types of SAS Config Pages 2089 ****************************************************************************/ 2090 2091 /*values for NegotiatedLinkRates fields */ 2092 #define MPI2_SAS_NEG_LINK_RATE_MASK_LOGICAL (0xF0) 2093 #define MPI2_SAS_NEG_LINK_RATE_SHIFT_LOGICAL (4) 2094 #define MPI2_SAS_NEG_LINK_RATE_MASK_PHYSICAL (0x0F) 2095 /*link rates used for Negotiated Physical and Logical Link Rate */ 2096 #define MPI2_SAS_NEG_LINK_RATE_UNKNOWN_LINK_RATE (0x00) 2097 #define MPI2_SAS_NEG_LINK_RATE_PHY_DISABLED (0x01) 2098 #define MPI2_SAS_NEG_LINK_RATE_NEGOTIATION_FAILED (0x02) 2099 #define MPI2_SAS_NEG_LINK_RATE_SATA_OOB_COMPLETE (0x03) 2100 #define MPI2_SAS_NEG_LINK_RATE_PORT_SELECTOR (0x04) 2101 #define MPI2_SAS_NEG_LINK_RATE_SMP_RESET_IN_PROGRESS (0x05) 2102 #define MPI2_SAS_NEG_LINK_RATE_UNSUPPORTED_PHY (0x06) 2103 #define MPI2_SAS_NEG_LINK_RATE_1_5 (0x08) 2104 #define MPI2_SAS_NEG_LINK_RATE_3_0 (0x09) 2105 #define MPI2_SAS_NEG_LINK_RATE_6_0 (0x0A) 2106 #define MPI25_SAS_NEG_LINK_RATE_12_0 (0x0B) 2107 #define MPI26_SAS_NEG_LINK_RATE_22_5 (0x0C) 2108 2109 2110 /*values for AttachedPhyInfo fields */ 2111 #define MPI2_SAS_APHYINFO_INSIDE_ZPSDS_PERSISTENT (0x00000040) 2112 #define MPI2_SAS_APHYINFO_REQUESTED_INSIDE_ZPSDS (0x00000020) 2113 #define MPI2_SAS_APHYINFO_BREAK_REPLY_CAPABLE (0x00000010) 2114 2115 #define MPI2_SAS_APHYINFO_REASON_MASK (0x0000000F) 2116 #define MPI2_SAS_APHYINFO_REASON_UNKNOWN (0x00000000) 2117 #define MPI2_SAS_APHYINFO_REASON_POWER_ON (0x00000001) 2118 #define MPI2_SAS_APHYINFO_REASON_HARD_RESET (0x00000002) 2119 #define MPI2_SAS_APHYINFO_REASON_SMP_PHY_CONTROL (0x00000003) 2120 #define MPI2_SAS_APHYINFO_REASON_LOSS_OF_SYNC (0x00000004) 2121 #define MPI2_SAS_APHYINFO_REASON_MULTIPLEXING_SEQ (0x00000005) 2122 #define MPI2_SAS_APHYINFO_REASON_IT_NEXUS_LOSS_TIMER (0x00000006) 2123 #define MPI2_SAS_APHYINFO_REASON_BREAK_TIMEOUT (0x00000007) 2124 #define MPI2_SAS_APHYINFO_REASON_PHY_TEST_STOPPED (0x00000008) 2125 2126 2127 /*values for PhyInfo fields */ 2128 #define MPI2_SAS_PHYINFO_PHY_VACANT (0x80000000) 2129 2130 #define MPI2_SAS_PHYINFO_PHY_POWER_CONDITION_MASK (0x18000000) 2131 #define MPI2_SAS_PHYINFO_SHIFT_PHY_POWER_CONDITION (27) 2132 #define MPI2_SAS_PHYINFO_PHY_POWER_ACTIVE (0x00000000) 2133 #define MPI2_SAS_PHYINFO_PHY_POWER_PARTIAL (0x08000000) 2134 #define MPI2_SAS_PHYINFO_PHY_POWER_SLUMBER (0x10000000) 2135 2136 #define MPI2_SAS_PHYINFO_CHANGED_REQ_INSIDE_ZPSDS (0x04000000) 2137 #define MPI2_SAS_PHYINFO_INSIDE_ZPSDS_PERSISTENT (0x02000000) 2138 #define MPI2_SAS_PHYINFO_REQ_INSIDE_ZPSDS (0x01000000) 2139 #define MPI2_SAS_PHYINFO_ZONE_GROUP_PERSISTENT (0x00400000) 2140 #define MPI2_SAS_PHYINFO_INSIDE_ZPSDS (0x00200000) 2141 #define MPI2_SAS_PHYINFO_ZONING_ENABLED (0x00100000) 2142 2143 #define MPI2_SAS_PHYINFO_REASON_MASK (0x000F0000) 2144 #define MPI2_SAS_PHYINFO_REASON_UNKNOWN (0x00000000) 2145 #define MPI2_SAS_PHYINFO_REASON_POWER_ON (0x00010000) 2146 #define MPI2_SAS_PHYINFO_REASON_HARD_RESET (0x00020000) 2147 #define MPI2_SAS_PHYINFO_REASON_SMP_PHY_CONTROL (0x00030000) 2148 #define MPI2_SAS_PHYINFO_REASON_LOSS_OF_SYNC (0x00040000) 2149 #define MPI2_SAS_PHYINFO_REASON_MULTIPLEXING_SEQ (0x00050000) 2150 #define MPI2_SAS_PHYINFO_REASON_IT_NEXUS_LOSS_TIMER (0x00060000) 2151 #define MPI2_SAS_PHYINFO_REASON_BREAK_TIMEOUT (0x00070000) 2152 #define MPI2_SAS_PHYINFO_REASON_PHY_TEST_STOPPED (0x00080000) 2153 2154 #define MPI2_SAS_PHYINFO_MULTIPLEXING_SUPPORTED (0x00008000) 2155 #define MPI2_SAS_PHYINFO_SATA_PORT_ACTIVE (0x00004000) 2156 #define MPI2_SAS_PHYINFO_SATA_PORT_SELECTOR_PRESENT (0x00002000) 2157 #define MPI2_SAS_PHYINFO_VIRTUAL_PHY (0x00001000) 2158 2159 #define MPI2_SAS_PHYINFO_MASK_PARTIAL_PATHWAY_TIME (0x00000F00) 2160 #define MPI2_SAS_PHYINFO_SHIFT_PARTIAL_PATHWAY_TIME (8) 2161 2162 #define MPI2_SAS_PHYINFO_MASK_ROUTING_ATTRIBUTE (0x000000F0) 2163 #define MPI2_SAS_PHYINFO_DIRECT_ROUTING (0x00000000) 2164 #define MPI2_SAS_PHYINFO_SUBTRACTIVE_ROUTING (0x00000010) 2165 #define MPI2_SAS_PHYINFO_TABLE_ROUTING (0x00000020) 2166 2167 2168 /*values for SAS ProgrammedLinkRate fields */ 2169 #define MPI2_SAS_PRATE_MAX_RATE_MASK (0xF0) 2170 #define MPI2_SAS_PRATE_MAX_RATE_NOT_PROGRAMMABLE (0x00) 2171 #define MPI2_SAS_PRATE_MAX_RATE_1_5 (0x80) 2172 #define MPI2_SAS_PRATE_MAX_RATE_3_0 (0x90) 2173 #define MPI2_SAS_PRATE_MAX_RATE_6_0 (0xA0) 2174 #define MPI25_SAS_PRATE_MAX_RATE_12_0 (0xB0) 2175 #define MPI26_SAS_PRATE_MAX_RATE_22_5 (0xC0) 2176 #define MPI2_SAS_PRATE_MIN_RATE_MASK (0x0F) 2177 #define MPI2_SAS_PRATE_MIN_RATE_NOT_PROGRAMMABLE (0x00) 2178 #define MPI2_SAS_PRATE_MIN_RATE_1_5 (0x08) 2179 #define MPI2_SAS_PRATE_MIN_RATE_3_0 (0x09) 2180 #define MPI2_SAS_PRATE_MIN_RATE_6_0 (0x0A) 2181 #define MPI25_SAS_PRATE_MIN_RATE_12_0 (0x0B) 2182 #define MPI26_SAS_PRATE_MIN_RATE_22_5 (0x0C) 2183 2184 2185 /*values for SAS HwLinkRate fields */ 2186 #define MPI2_SAS_HWRATE_MAX_RATE_MASK (0xF0) 2187 #define MPI2_SAS_HWRATE_MAX_RATE_1_5 (0x80) 2188 #define MPI2_SAS_HWRATE_MAX_RATE_3_0 (0x90) 2189 #define MPI2_SAS_HWRATE_MAX_RATE_6_0 (0xA0) 2190 #define MPI25_SAS_HWRATE_MAX_RATE_12_0 (0xB0) 2191 #define MPI26_SAS_HWRATE_MAX_RATE_22_5 (0xC0) 2192 #define MPI2_SAS_HWRATE_MIN_RATE_MASK (0x0F) 2193 #define MPI2_SAS_HWRATE_MIN_RATE_1_5 (0x08) 2194 #define MPI2_SAS_HWRATE_MIN_RATE_3_0 (0x09) 2195 #define MPI2_SAS_HWRATE_MIN_RATE_6_0 (0x0A) 2196 #define MPI25_SAS_HWRATE_MIN_RATE_12_0 (0x0B) 2197 #define MPI26_SAS_HWRATE_MIN_RATE_22_5 (0x0C) 2198 2199 2200 2201 /**************************************************************************** 2202 * SAS IO Unit Config Pages 2203 ****************************************************************************/ 2204 2205 /*SAS IO Unit Page 0 */ 2206 2207 typedef struct _MPI2_SAS_IO_UNIT0_PHY_DATA { 2208 U8 Port; /*0x00 */ 2209 U8 PortFlags; /*0x01 */ 2210 U8 PhyFlags; /*0x02 */ 2211 U8 NegotiatedLinkRate; /*0x03 */ 2212 U32 ControllerPhyDeviceInfo;/*0x04 */ 2213 U16 AttachedDevHandle; /*0x08 */ 2214 U16 ControllerDevHandle; /*0x0A */ 2215 U32 DiscoveryStatus; /*0x0C */ 2216 U32 Reserved; /*0x10 */ 2217 } MPI2_SAS_IO_UNIT0_PHY_DATA, 2218 *PTR_MPI2_SAS_IO_UNIT0_PHY_DATA, 2219 Mpi2SasIOUnit0PhyData_t, 2220 *pMpi2SasIOUnit0PhyData_t; 2221 2222 /* 2223 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2224 *one and check the value returned for NumPhys at runtime. 2225 */ 2226 #ifndef MPI2_SAS_IOUNIT0_PHY_MAX 2227 #define MPI2_SAS_IOUNIT0_PHY_MAX (1) 2228 #endif 2229 2230 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_0 { 2231 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */ 2232 U32 Reserved1;/*0x08 */ 2233 U8 NumPhys; /*0x0C */ 2234 U8 Reserved2;/*0x0D */ 2235 U16 Reserved3;/*0x0E */ 2236 MPI2_SAS_IO_UNIT0_PHY_DATA 2237 PhyData[MPI2_SAS_IOUNIT0_PHY_MAX]; /*0x10 */ 2238 } MPI2_CONFIG_PAGE_SASIOUNIT_0, 2239 *PTR_MPI2_CONFIG_PAGE_SASIOUNIT_0, 2240 Mpi2SasIOUnitPage0_t, *pMpi2SasIOUnitPage0_t; 2241 2242 #define MPI2_SASIOUNITPAGE0_PAGEVERSION (0x05) 2243 2244 /*values for SAS IO Unit Page 0 PortFlags */ 2245 #define MPI2_SASIOUNIT0_PORTFLAGS_DISCOVERY_IN_PROGRESS (0x08) 2246 #define MPI2_SASIOUNIT0_PORTFLAGS_AUTO_PORT_CONFIG (0x01) 2247 2248 /*values for SAS IO Unit Page 0 PhyFlags */ 2249 #define MPI2_SASIOUNIT0_PHYFLAGS_INIT_PERSIST_CONNECT (0x40) 2250 #define MPI2_SASIOUNIT0_PHYFLAGS_TARG_PERSIST_CONNECT (0x20) 2251 #define MPI2_SASIOUNIT0_PHYFLAGS_ZONING_ENABLED (0x10) 2252 #define MPI2_SASIOUNIT0_PHYFLAGS_PHY_DISABLED (0x08) 2253 2254 /*use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */ 2255 2256 /*see mpi2_sas.h for values for 2257 *SAS IO Unit Page 0 ControllerPhyDeviceInfo values */ 2258 2259 /*values for SAS IO Unit Page 0 DiscoveryStatus */ 2260 #define MPI2_SASIOUNIT0_DS_MAX_ENCLOSURES_EXCEED (0x80000000) 2261 #define MPI2_SASIOUNIT0_DS_MAX_EXPANDERS_EXCEED (0x40000000) 2262 #define MPI2_SASIOUNIT0_DS_MAX_DEVICES_EXCEED (0x20000000) 2263 #define MPI2_SASIOUNIT0_DS_MAX_TOPO_PHYS_EXCEED (0x10000000) 2264 #define MPI2_SASIOUNIT0_DS_DOWNSTREAM_INITIATOR (0x08000000) 2265 #define MPI2_SASIOUNIT0_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE (0x00008000) 2266 #define MPI2_SASIOUNIT0_DS_EXP_MULTI_SUBTRACTIVE (0x00004000) 2267 #define MPI2_SASIOUNIT0_DS_MULTI_PORT_DOMAIN (0x00002000) 2268 #define MPI2_SASIOUNIT0_DS_TABLE_TO_SUBTRACTIVE_LINK (0x00001000) 2269 #define MPI2_SASIOUNIT0_DS_UNSUPPORTED_DEVICE (0x00000800) 2270 #define MPI2_SASIOUNIT0_DS_TABLE_LINK (0x00000400) 2271 #define MPI2_SASIOUNIT0_DS_SUBTRACTIVE_LINK (0x00000200) 2272 #define MPI2_SASIOUNIT0_DS_SMP_CRC_ERROR (0x00000100) 2273 #define MPI2_SASIOUNIT0_DS_SMP_FUNCTION_FAILED (0x00000080) 2274 #define MPI2_SASIOUNIT0_DS_INDEX_NOT_EXIST (0x00000040) 2275 #define MPI2_SASIOUNIT0_DS_OUT_ROUTE_ENTRIES (0x00000020) 2276 #define MPI2_SASIOUNIT0_DS_SMP_TIMEOUT (0x00000010) 2277 #define MPI2_SASIOUNIT0_DS_MULTIPLE_PORTS (0x00000004) 2278 #define MPI2_SASIOUNIT0_DS_UNADDRESSABLE_DEVICE (0x00000002) 2279 #define MPI2_SASIOUNIT0_DS_LOOP_DETECTED (0x00000001) 2280 2281 2282 /*SAS IO Unit Page 1 */ 2283 2284 typedef struct _MPI2_SAS_IO_UNIT1_PHY_DATA { 2285 U8 Port; /*0x00 */ 2286 U8 PortFlags; /*0x01 */ 2287 U8 PhyFlags; /*0x02 */ 2288 U8 MaxMinLinkRate; /*0x03 */ 2289 U32 ControllerPhyDeviceInfo; /*0x04 */ 2290 U16 MaxTargetPortConnectTime; /*0x08 */ 2291 U16 Reserved1; /*0x0A */ 2292 } MPI2_SAS_IO_UNIT1_PHY_DATA, 2293 *PTR_MPI2_SAS_IO_UNIT1_PHY_DATA, 2294 Mpi2SasIOUnit1PhyData_t, 2295 *pMpi2SasIOUnit1PhyData_t; 2296 2297 /* 2298 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2299 *one and check the value returned for NumPhys at runtime. 2300 */ 2301 #ifndef MPI2_SAS_IOUNIT1_PHY_MAX 2302 #define MPI2_SAS_IOUNIT1_PHY_MAX (1) 2303 #endif 2304 2305 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_1 { 2306 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */ 2307 U16 2308 ControlFlags; /*0x08 */ 2309 U16 2310 SASNarrowMaxQueueDepth; /*0x0A */ 2311 U16 2312 AdditionalControlFlags; /*0x0C */ 2313 U16 2314 SASWideMaxQueueDepth; /*0x0E */ 2315 U8 2316 NumPhys; /*0x10 */ 2317 U8 2318 SATAMaxQDepth; /*0x11 */ 2319 U8 2320 ReportDeviceMissingDelay; /*0x12 */ 2321 U8 2322 IODeviceMissingDelay; /*0x13 */ 2323 MPI2_SAS_IO_UNIT1_PHY_DATA 2324 PhyData[MPI2_SAS_IOUNIT1_PHY_MAX]; /*0x14 */ 2325 } MPI2_CONFIG_PAGE_SASIOUNIT_1, 2326 *PTR_MPI2_CONFIG_PAGE_SASIOUNIT_1, 2327 Mpi2SasIOUnitPage1_t, *pMpi2SasIOUnitPage1_t; 2328 2329 #define MPI2_SASIOUNITPAGE1_PAGEVERSION (0x09) 2330 2331 /*values for SAS IO Unit Page 1 ControlFlags */ 2332 #define MPI2_SASIOUNIT1_CONTROL_DEVICE_SELF_TEST (0x8000) 2333 #define MPI2_SASIOUNIT1_CONTROL_SATA_3_0_MAX (0x4000) 2334 #define MPI2_SASIOUNIT1_CONTROL_SATA_1_5_MAX (0x2000) 2335 #define MPI2_SASIOUNIT1_CONTROL_SATA_SW_PRESERVE (0x1000) 2336 2337 #define MPI2_SASIOUNIT1_CONTROL_MASK_DEV_SUPPORT (0x0600) 2338 #define MPI2_SASIOUNIT1_CONTROL_SHIFT_DEV_SUPPORT (9) 2339 #define MPI2_SASIOUNIT1_CONTROL_DEV_SUPPORT_BOTH (0x0) 2340 #define MPI2_SASIOUNIT1_CONTROL_DEV_SAS_SUPPORT (0x1) 2341 #define MPI2_SASIOUNIT1_CONTROL_DEV_SATA_SUPPORT (0x2) 2342 2343 #define MPI2_SASIOUNIT1_CONTROL_SATA_48BIT_LBA_REQUIRED (0x0080) 2344 #define MPI2_SASIOUNIT1_CONTROL_SATA_SMART_REQUIRED (0x0040) 2345 #define MPI2_SASIOUNIT1_CONTROL_SATA_NCQ_REQUIRED (0x0020) 2346 #define MPI2_SASIOUNIT1_CONTROL_SATA_FUA_REQUIRED (0x0010) 2347 #define MPI2_SASIOUNIT1_CONTROL_TABLE_SUBTRACTIVE_ILLEGAL (0x0008) 2348 #define MPI2_SASIOUNIT1_CONTROL_SUBTRACTIVE_ILLEGAL (0x0004) 2349 #define MPI2_SASIOUNIT1_CONTROL_FIRST_LVL_DISC_ONLY (0x0002) 2350 #define MPI2_SASIOUNIT1_CONTROL_CLEAR_AFFILIATION (0x0001) 2351 2352 /*values for SAS IO Unit Page 1 AdditionalControlFlags */ 2353 #define MPI2_SASIOUNIT1_ACONTROL_DA_PERSIST_CONNECT (0x0100) 2354 #define MPI2_SASIOUNIT1_ACONTROL_MULTI_PORT_DOMAIN_ILLEGAL (0x0080) 2355 #define MPI2_SASIOUNIT1_ACONTROL_SATA_ASYNCHROUNOUS_NOTIFICATION (0x0040) 2356 #define MPI2_SASIOUNIT1_ACONTROL_INVALID_TOPOLOGY_CORRECTION (0x0020) 2357 #define MPI2_SASIOUNIT1_ACONTROL_PORT_ENABLE_ONLY_SATA_LINK_RESET (0x0010) 2358 #define MPI2_SASIOUNIT1_ACONTROL_OTHER_AFFILIATION_SATA_LINK_RESET (0x0008) 2359 #define MPI2_SASIOUNIT1_ACONTROL_SELF_AFFILIATION_SATA_LINK_RESET (0x0004) 2360 #define MPI2_SASIOUNIT1_ACONTROL_NO_AFFILIATION_SATA_LINK_RESET (0x0002) 2361 #define MPI2_SASIOUNIT1_ACONTROL_ALLOW_TABLE_TO_TABLE (0x0001) 2362 2363 /*defines for SAS IO Unit Page 1 ReportDeviceMissingDelay */ 2364 #define MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK (0x7F) 2365 #define MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16 (0x80) 2366 2367 /*values for SAS IO Unit Page 1 PortFlags */ 2368 #define MPI2_SASIOUNIT1_PORT_FLAGS_AUTO_PORT_CONFIG (0x01) 2369 2370 /*values for SAS IO Unit Page 1 PhyFlags */ 2371 #define MPI2_SASIOUNIT1_PHYFLAGS_INIT_PERSIST_CONNECT (0x40) 2372 #define MPI2_SASIOUNIT1_PHYFLAGS_TARG_PERSIST_CONNECT (0x20) 2373 #define MPI2_SASIOUNIT1_PHYFLAGS_ZONING_ENABLE (0x10) 2374 #define MPI2_SASIOUNIT1_PHYFLAGS_PHY_DISABLE (0x08) 2375 2376 /*values for SAS IO Unit Page 1 MaxMinLinkRate */ 2377 #define MPI2_SASIOUNIT1_MAX_RATE_MASK (0xF0) 2378 #define MPI2_SASIOUNIT1_MAX_RATE_1_5 (0x80) 2379 #define MPI2_SASIOUNIT1_MAX_RATE_3_0 (0x90) 2380 #define MPI2_SASIOUNIT1_MAX_RATE_6_0 (0xA0) 2381 #define MPI25_SASIOUNIT1_MAX_RATE_12_0 (0xB0) 2382 #define MPI26_SASIOUNIT1_MAX_RATE_22_5 (0xC0) 2383 #define MPI2_SASIOUNIT1_MIN_RATE_MASK (0x0F) 2384 #define MPI2_SASIOUNIT1_MIN_RATE_1_5 (0x08) 2385 #define MPI2_SASIOUNIT1_MIN_RATE_3_0 (0x09) 2386 #define MPI2_SASIOUNIT1_MIN_RATE_6_0 (0x0A) 2387 #define MPI25_SASIOUNIT1_MIN_RATE_12_0 (0x0B) 2388 #define MPI26_SASIOUNIT1_MIN_RATE_22_5 (0x0C) 2389 2390 /*see mpi2_sas.h for values for 2391 *SAS IO Unit Page 1 ControllerPhyDeviceInfo values */ 2392 2393 2394 /*SAS IO Unit Page 4 (for MPI v2.5 and earlier) */ 2395 2396 typedef struct _MPI2_SAS_IOUNIT4_SPINUP_GROUP { 2397 U8 MaxTargetSpinup; /*0x00 */ 2398 U8 SpinupDelay; /*0x01 */ 2399 U8 SpinupFlags; /*0x02 */ 2400 U8 Reserved1; /*0x03 */ 2401 } MPI2_SAS_IOUNIT4_SPINUP_GROUP, 2402 *PTR_MPI2_SAS_IOUNIT4_SPINUP_GROUP, 2403 Mpi2SasIOUnit4SpinupGroup_t, 2404 *pMpi2SasIOUnit4SpinupGroup_t; 2405 /*defines for SAS IO Unit Page 4 SpinupFlags */ 2406 #define MPI2_SASIOUNIT4_SPINUP_DISABLE_FLAG (0x01) 2407 2408 2409 /* 2410 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2411 *one and check the value returned for NumPhys at runtime. 2412 */ 2413 #ifndef MPI2_SAS_IOUNIT4_PHY_MAX 2414 #define MPI2_SAS_IOUNIT4_PHY_MAX (4) 2415 #endif 2416 2417 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_4 { 2418 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header;/*0x00 */ 2419 MPI2_SAS_IOUNIT4_SPINUP_GROUP 2420 SpinupGroupParameters[4]; /*0x08 */ 2421 U32 2422 Reserved1; /*0x18 */ 2423 U32 2424 Reserved2; /*0x1C */ 2425 U32 2426 Reserved3; /*0x20 */ 2427 U8 2428 BootDeviceWaitTime; /*0x24 */ 2429 U8 2430 SATADeviceWaitTime; /*0x25 */ 2431 U16 2432 Reserved5; /*0x26 */ 2433 U8 2434 NumPhys; /*0x28 */ 2435 U8 2436 PEInitialSpinupDelay; /*0x29 */ 2437 U8 2438 PEReplyDelay; /*0x2A */ 2439 U8 2440 Flags; /*0x2B */ 2441 U8 2442 PHY[MPI2_SAS_IOUNIT4_PHY_MAX]; /*0x2C */ 2443 } MPI2_CONFIG_PAGE_SASIOUNIT_4, 2444 *PTR_MPI2_CONFIG_PAGE_SASIOUNIT_4, 2445 Mpi2SasIOUnitPage4_t, *pMpi2SasIOUnitPage4_t; 2446 2447 #define MPI2_SASIOUNITPAGE4_PAGEVERSION (0x02) 2448 2449 /*defines for Flags field */ 2450 #define MPI2_SASIOUNIT4_FLAGS_AUTO_PORTENABLE (0x01) 2451 2452 /*defines for PHY field */ 2453 #define MPI2_SASIOUNIT4_PHY_SPINUP_GROUP_MASK (0x03) 2454 2455 2456 /*SAS IO Unit Page 5 */ 2457 2458 typedef struct _MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS { 2459 U8 ControlFlags; /*0x00 */ 2460 U8 PortWidthModGroup; /*0x01 */ 2461 U16 InactivityTimerExponent; /*0x02 */ 2462 U8 SATAPartialTimeout; /*0x04 */ 2463 U8 Reserved2; /*0x05 */ 2464 U8 SATASlumberTimeout; /*0x06 */ 2465 U8 Reserved3; /*0x07 */ 2466 U8 SASPartialTimeout; /*0x08 */ 2467 U8 Reserved4; /*0x09 */ 2468 U8 SASSlumberTimeout; /*0x0A */ 2469 U8 Reserved5; /*0x0B */ 2470 } MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS, 2471 *PTR_MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS, 2472 Mpi2SasIOUnit5PhyPmSettings_t, 2473 *pMpi2SasIOUnit5PhyPmSettings_t; 2474 2475 /*defines for ControlFlags field */ 2476 #define MPI2_SASIOUNIT5_CONTROL_SAS_SLUMBER_ENABLE (0x08) 2477 #define MPI2_SASIOUNIT5_CONTROL_SAS_PARTIAL_ENABLE (0x04) 2478 #define MPI2_SASIOUNIT5_CONTROL_SATA_SLUMBER_ENABLE (0x02) 2479 #define MPI2_SASIOUNIT5_CONTROL_SATA_PARTIAL_ENABLE (0x01) 2480 2481 /*defines for PortWidthModeGroup field */ 2482 #define MPI2_SASIOUNIT5_PWMG_DISABLE (0xFF) 2483 2484 /*defines for InactivityTimerExponent field */ 2485 #define MPI2_SASIOUNIT5_ITE_MASK_SAS_SLUMBER (0x7000) 2486 #define MPI2_SASIOUNIT5_ITE_SHIFT_SAS_SLUMBER (12) 2487 #define MPI2_SASIOUNIT5_ITE_MASK_SAS_PARTIAL (0x0700) 2488 #define MPI2_SASIOUNIT5_ITE_SHIFT_SAS_PARTIAL (8) 2489 #define MPI2_SASIOUNIT5_ITE_MASK_SATA_SLUMBER (0x0070) 2490 #define MPI2_SASIOUNIT5_ITE_SHIFT_SATA_SLUMBER (4) 2491 #define MPI2_SASIOUNIT5_ITE_MASK_SATA_PARTIAL (0x0007) 2492 #define MPI2_SASIOUNIT5_ITE_SHIFT_SATA_PARTIAL (0) 2493 2494 #define MPI2_SASIOUNIT5_ITE_TEN_SECONDS (7) 2495 #define MPI2_SASIOUNIT5_ITE_ONE_SECOND (6) 2496 #define MPI2_SASIOUNIT5_ITE_HUNDRED_MILLISECONDS (5) 2497 #define MPI2_SASIOUNIT5_ITE_TEN_MILLISECONDS (4) 2498 #define MPI2_SASIOUNIT5_ITE_ONE_MILLISECOND (3) 2499 #define MPI2_SASIOUNIT5_ITE_HUNDRED_MICROSECONDS (2) 2500 #define MPI2_SASIOUNIT5_ITE_TEN_MICROSECONDS (1) 2501 #define MPI2_SASIOUNIT5_ITE_ONE_MICROSECOND (0) 2502 2503 /* 2504 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2505 *one and check the value returned for NumPhys at runtime. 2506 */ 2507 #ifndef MPI2_SAS_IOUNIT5_PHY_MAX 2508 #define MPI2_SAS_IOUNIT5_PHY_MAX (1) 2509 #endif 2510 2511 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_5 { 2512 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */ 2513 U8 NumPhys; /*0x08 */ 2514 U8 Reserved1;/*0x09 */ 2515 U16 Reserved2;/*0x0A */ 2516 U32 Reserved3;/*0x0C */ 2517 MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS 2518 SASPhyPowerManagementSettings[MPI2_SAS_IOUNIT5_PHY_MAX];/*0x10 */ 2519 } MPI2_CONFIG_PAGE_SASIOUNIT_5, 2520 *PTR_MPI2_CONFIG_PAGE_SASIOUNIT_5, 2521 Mpi2SasIOUnitPage5_t, *pMpi2SasIOUnitPage5_t; 2522 2523 #define MPI2_SASIOUNITPAGE5_PAGEVERSION (0x01) 2524 2525 2526 /*SAS IO Unit Page 6 */ 2527 2528 typedef struct _MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS { 2529 U8 CurrentStatus; /*0x00 */ 2530 U8 CurrentModulation; /*0x01 */ 2531 U8 CurrentUtilization; /*0x02 */ 2532 U8 Reserved1; /*0x03 */ 2533 U32 Reserved2; /*0x04 */ 2534 } MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS, 2535 *PTR_MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS, 2536 Mpi2SasIOUnit6PortWidthModGroupStatus_t, 2537 *pMpi2SasIOUnit6PortWidthModGroupStatus_t; 2538 2539 /*defines for CurrentStatus field */ 2540 #define MPI2_SASIOUNIT6_STATUS_UNAVAILABLE (0x00) 2541 #define MPI2_SASIOUNIT6_STATUS_UNCONFIGURED (0x01) 2542 #define MPI2_SASIOUNIT6_STATUS_INVALID_CONFIG (0x02) 2543 #define MPI2_SASIOUNIT6_STATUS_LINK_DOWN (0x03) 2544 #define MPI2_SASIOUNIT6_STATUS_OBSERVATION_ONLY (0x04) 2545 #define MPI2_SASIOUNIT6_STATUS_INACTIVE (0x05) 2546 #define MPI2_SASIOUNIT6_STATUS_ACTIVE_IOUNIT (0x06) 2547 #define MPI2_SASIOUNIT6_STATUS_ACTIVE_HOST (0x07) 2548 2549 /*defines for CurrentModulation field */ 2550 #define MPI2_SASIOUNIT6_MODULATION_25_PERCENT (0x00) 2551 #define MPI2_SASIOUNIT6_MODULATION_50_PERCENT (0x01) 2552 #define MPI2_SASIOUNIT6_MODULATION_75_PERCENT (0x02) 2553 #define MPI2_SASIOUNIT6_MODULATION_100_PERCENT (0x03) 2554 2555 /* 2556 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2557 *one and check the value returned for NumGroups at runtime. 2558 */ 2559 #ifndef MPI2_SAS_IOUNIT6_GROUP_MAX 2560 #define MPI2_SAS_IOUNIT6_GROUP_MAX (1) 2561 #endif 2562 2563 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_6 { 2564 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */ 2565 U32 Reserved1; /*0x08 */ 2566 U32 Reserved2; /*0x0C */ 2567 U8 NumGroups; /*0x10 */ 2568 U8 Reserved3; /*0x11 */ 2569 U16 Reserved4; /*0x12 */ 2570 MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS 2571 PortWidthModulationGroupStatus[MPI2_SAS_IOUNIT6_GROUP_MAX]; /*0x14 */ 2572 } MPI2_CONFIG_PAGE_SASIOUNIT_6, 2573 *PTR_MPI2_CONFIG_PAGE_SASIOUNIT_6, 2574 Mpi2SasIOUnitPage6_t, *pMpi2SasIOUnitPage6_t; 2575 2576 #define MPI2_SASIOUNITPAGE6_PAGEVERSION (0x00) 2577 2578 2579 /*SAS IO Unit Page 7 */ 2580 2581 typedef struct _MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS { 2582 U8 Flags; /*0x00 */ 2583 U8 Reserved1; /*0x01 */ 2584 U16 Reserved2; /*0x02 */ 2585 U8 Threshold75Pct; /*0x04 */ 2586 U8 Threshold50Pct; /*0x05 */ 2587 U8 Threshold25Pct; /*0x06 */ 2588 U8 Reserved3; /*0x07 */ 2589 } MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS, 2590 *PTR_MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS, 2591 Mpi2SasIOUnit7PortWidthModGroupSettings_t, 2592 *pMpi2SasIOUnit7PortWidthModGroupSettings_t; 2593 2594 /*defines for Flags field */ 2595 #define MPI2_SASIOUNIT7_FLAGS_ENABLE_PORT_WIDTH_MODULATION (0x01) 2596 2597 2598 /* 2599 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2600 *one and check the value returned for NumGroups at runtime. 2601 */ 2602 #ifndef MPI2_SAS_IOUNIT7_GROUP_MAX 2603 #define MPI2_SAS_IOUNIT7_GROUP_MAX (1) 2604 #endif 2605 2606 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_7 { 2607 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */ 2608 U8 SamplingInterval; /*0x08 */ 2609 U8 WindowLength; /*0x09 */ 2610 U16 Reserved1; /*0x0A */ 2611 U32 Reserved2; /*0x0C */ 2612 U32 Reserved3; /*0x10 */ 2613 U8 NumGroups; /*0x14 */ 2614 U8 Reserved4; /*0x15 */ 2615 U16 Reserved5; /*0x16 */ 2616 MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS 2617 PortWidthModulationGroupSettings[MPI2_SAS_IOUNIT7_GROUP_MAX];/*0x18 */ 2618 } MPI2_CONFIG_PAGE_SASIOUNIT_7, 2619 *PTR_MPI2_CONFIG_PAGE_SASIOUNIT_7, 2620 Mpi2SasIOUnitPage7_t, *pMpi2SasIOUnitPage7_t; 2621 2622 #define MPI2_SASIOUNITPAGE7_PAGEVERSION (0x00) 2623 2624 2625 /*SAS IO Unit Page 8 */ 2626 2627 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_8 { 2628 MPI2_CONFIG_EXTENDED_PAGE_HEADER 2629 Header; /*0x00 */ 2630 U32 2631 Reserved1; /*0x08 */ 2632 U32 2633 PowerManagementCapabilities; /*0x0C */ 2634 U8 2635 TxRxSleepStatus; /*0x10 */ 2636 U8 2637 Reserved2; /*0x11 */ 2638 U16 2639 Reserved3; /*0x12 */ 2640 } MPI2_CONFIG_PAGE_SASIOUNIT_8, 2641 *PTR_MPI2_CONFIG_PAGE_SASIOUNIT_8, 2642 Mpi2SasIOUnitPage8_t, *pMpi2SasIOUnitPage8_t; 2643 2644 #define MPI2_SASIOUNITPAGE8_PAGEVERSION (0x00) 2645 2646 /*defines for PowerManagementCapabilities field */ 2647 #define MPI2_SASIOUNIT8_PM_HOST_PORT_WIDTH_MOD (0x00001000) 2648 #define MPI2_SASIOUNIT8_PM_HOST_SAS_SLUMBER_MODE (0x00000800) 2649 #define MPI2_SASIOUNIT8_PM_HOST_SAS_PARTIAL_MODE (0x00000400) 2650 #define MPI2_SASIOUNIT8_PM_HOST_SATA_SLUMBER_MODE (0x00000200) 2651 #define MPI2_SASIOUNIT8_PM_HOST_SATA_PARTIAL_MODE (0x00000100) 2652 #define MPI2_SASIOUNIT8_PM_IOUNIT_PORT_WIDTH_MOD (0x00000010) 2653 #define MPI2_SASIOUNIT8_PM_IOUNIT_SAS_SLUMBER_MODE (0x00000008) 2654 #define MPI2_SASIOUNIT8_PM_IOUNIT_SAS_PARTIAL_MODE (0x00000004) 2655 #define MPI2_SASIOUNIT8_PM_IOUNIT_SATA_SLUMBER_MODE (0x00000002) 2656 #define MPI2_SASIOUNIT8_PM_IOUNIT_SATA_PARTIAL_MODE (0x00000001) 2657 2658 /*defines for TxRxSleepStatus field */ 2659 #define MPI25_SASIOUNIT8_TXRXSLEEP_UNSUPPORTED (0x00) 2660 #define MPI25_SASIOUNIT8_TXRXSLEEP_DISENGAGED (0x01) 2661 #define MPI25_SASIOUNIT8_TXRXSLEEP_ACTIVE (0x02) 2662 #define MPI25_SASIOUNIT8_TXRXSLEEP_SHUTDOWN (0x03) 2663 2664 2665 2666 /*SAS IO Unit Page 16 */ 2667 2668 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT16 { 2669 MPI2_CONFIG_EXTENDED_PAGE_HEADER 2670 Header; /*0x00 */ 2671 U64 2672 TimeStamp; /*0x08 */ 2673 U32 2674 Reserved1; /*0x10 */ 2675 U32 2676 Reserved2; /*0x14 */ 2677 U32 2678 FastPathPendedRequests; /*0x18 */ 2679 U32 2680 FastPathUnPendedRequests; /*0x1C */ 2681 U32 2682 FastPathHostRequestStarts; /*0x20 */ 2683 U32 2684 FastPathFirmwareRequestStarts; /*0x24 */ 2685 U32 2686 FastPathHostCompletions; /*0x28 */ 2687 U32 2688 FastPathFirmwareCompletions; /*0x2C */ 2689 U32 2690 NonFastPathRequestStarts; /*0x30 */ 2691 U32 2692 NonFastPathHostCompletions; /*0x30 */ 2693 } MPI2_CONFIG_PAGE_SASIOUNIT16, 2694 *PTR_MPI2_CONFIG_PAGE_SASIOUNIT16, 2695 Mpi2SasIOUnitPage16_t, *pMpi2SasIOUnitPage16_t; 2696 2697 #define MPI2_SASIOUNITPAGE16_PAGEVERSION (0x00) 2698 2699 2700 /**************************************************************************** 2701 * SAS Expander Config Pages 2702 ****************************************************************************/ 2703 2704 /*SAS Expander Page 0 */ 2705 2706 typedef struct _MPI2_CONFIG_PAGE_EXPANDER_0 { 2707 MPI2_CONFIG_EXTENDED_PAGE_HEADER 2708 Header; /*0x00 */ 2709 U8 2710 PhysicalPort; /*0x08 */ 2711 U8 2712 ReportGenLength; /*0x09 */ 2713 U16 2714 EnclosureHandle; /*0x0A */ 2715 U64 2716 SASAddress; /*0x0C */ 2717 U32 2718 DiscoveryStatus; /*0x14 */ 2719 U16 2720 DevHandle; /*0x18 */ 2721 U16 2722 ParentDevHandle; /*0x1A */ 2723 U16 2724 ExpanderChangeCount; /*0x1C */ 2725 U16 2726 ExpanderRouteIndexes; /*0x1E */ 2727 U8 2728 NumPhys; /*0x20 */ 2729 U8 2730 SASLevel; /*0x21 */ 2731 U16 2732 Flags; /*0x22 */ 2733 U16 2734 STPBusInactivityTimeLimit; /*0x24 */ 2735 U16 2736 STPMaxConnectTimeLimit; /*0x26 */ 2737 U16 2738 STP_SMP_NexusLossTime; /*0x28 */ 2739 U16 2740 MaxNumRoutedSasAddresses; /*0x2A */ 2741 U64 2742 ActiveZoneManagerSASAddress;/*0x2C */ 2743 U16 2744 ZoneLockInactivityLimit; /*0x34 */ 2745 U16 2746 Reserved1; /*0x36 */ 2747 U8 2748 TimeToReducedFunc; /*0x38 */ 2749 U8 2750 InitialTimeToReducedFunc; /*0x39 */ 2751 U8 2752 MaxReducedFuncTime; /*0x3A */ 2753 U8 2754 Reserved2; /*0x3B */ 2755 } MPI2_CONFIG_PAGE_EXPANDER_0, 2756 *PTR_MPI2_CONFIG_PAGE_EXPANDER_0, 2757 Mpi2ExpanderPage0_t, *pMpi2ExpanderPage0_t; 2758 2759 #define MPI2_SASEXPANDER0_PAGEVERSION (0x06) 2760 2761 /*values for SAS Expander Page 0 DiscoveryStatus field */ 2762 #define MPI2_SAS_EXPANDER0_DS_MAX_ENCLOSURES_EXCEED (0x80000000) 2763 #define MPI2_SAS_EXPANDER0_DS_MAX_EXPANDERS_EXCEED (0x40000000) 2764 #define MPI2_SAS_EXPANDER0_DS_MAX_DEVICES_EXCEED (0x20000000) 2765 #define MPI2_SAS_EXPANDER0_DS_MAX_TOPO_PHYS_EXCEED (0x10000000) 2766 #define MPI2_SAS_EXPANDER0_DS_DOWNSTREAM_INITIATOR (0x08000000) 2767 #define MPI2_SAS_EXPANDER0_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE (0x00008000) 2768 #define MPI2_SAS_EXPANDER0_DS_EXP_MULTI_SUBTRACTIVE (0x00004000) 2769 #define MPI2_SAS_EXPANDER0_DS_MULTI_PORT_DOMAIN (0x00002000) 2770 #define MPI2_SAS_EXPANDER0_DS_TABLE_TO_SUBTRACTIVE_LINK (0x00001000) 2771 #define MPI2_SAS_EXPANDER0_DS_UNSUPPORTED_DEVICE (0x00000800) 2772 #define MPI2_SAS_EXPANDER0_DS_TABLE_LINK (0x00000400) 2773 #define MPI2_SAS_EXPANDER0_DS_SUBTRACTIVE_LINK (0x00000200) 2774 #define MPI2_SAS_EXPANDER0_DS_SMP_CRC_ERROR (0x00000100) 2775 #define MPI2_SAS_EXPANDER0_DS_SMP_FUNCTION_FAILED (0x00000080) 2776 #define MPI2_SAS_EXPANDER0_DS_INDEX_NOT_EXIST (0x00000040) 2777 #define MPI2_SAS_EXPANDER0_DS_OUT_ROUTE_ENTRIES (0x00000020) 2778 #define MPI2_SAS_EXPANDER0_DS_SMP_TIMEOUT (0x00000010) 2779 #define MPI2_SAS_EXPANDER0_DS_MULTIPLE_PORTS (0x00000004) 2780 #define MPI2_SAS_EXPANDER0_DS_UNADDRESSABLE_DEVICE (0x00000002) 2781 #define MPI2_SAS_EXPANDER0_DS_LOOP_DETECTED (0x00000001) 2782 2783 /*values for SAS Expander Page 0 Flags field */ 2784 #define MPI2_SAS_EXPANDER0_FLAGS_REDUCED_FUNCTIONALITY (0x2000) 2785 #define MPI2_SAS_EXPANDER0_FLAGS_ZONE_LOCKED (0x1000) 2786 #define MPI2_SAS_EXPANDER0_FLAGS_SUPPORTED_PHYSICAL_PRES (0x0800) 2787 #define MPI2_SAS_EXPANDER0_FLAGS_ASSERTED_PHYSICAL_PRES (0x0400) 2788 #define MPI2_SAS_EXPANDER0_FLAGS_ZONING_SUPPORT (0x0200) 2789 #define MPI2_SAS_EXPANDER0_FLAGS_ENABLED_ZONING (0x0100) 2790 #define MPI2_SAS_EXPANDER0_FLAGS_TABLE_TO_TABLE_SUPPORT (0x0080) 2791 #define MPI2_SAS_EXPANDER0_FLAGS_CONNECTOR_END_DEVICE (0x0010) 2792 #define MPI2_SAS_EXPANDER0_FLAGS_OTHERS_CONFIG (0x0004) 2793 #define MPI2_SAS_EXPANDER0_FLAGS_CONFIG_IN_PROGRESS (0x0002) 2794 #define MPI2_SAS_EXPANDER0_FLAGS_ROUTE_TABLE_CONFIG (0x0001) 2795 2796 2797 /*SAS Expander Page 1 */ 2798 2799 typedef struct _MPI2_CONFIG_PAGE_EXPANDER_1 { 2800 MPI2_CONFIG_EXTENDED_PAGE_HEADER 2801 Header; /*0x00 */ 2802 U8 2803 PhysicalPort; /*0x08 */ 2804 U8 2805 Reserved1; /*0x09 */ 2806 U16 2807 Reserved2; /*0x0A */ 2808 U8 2809 NumPhys; /*0x0C */ 2810 U8 2811 Phy; /*0x0D */ 2812 U16 2813 NumTableEntriesProgrammed; /*0x0E */ 2814 U8 2815 ProgrammedLinkRate; /*0x10 */ 2816 U8 2817 HwLinkRate; /*0x11 */ 2818 U16 2819 AttachedDevHandle; /*0x12 */ 2820 U32 2821 PhyInfo; /*0x14 */ 2822 U32 2823 AttachedDeviceInfo; /*0x18 */ 2824 U16 2825 ExpanderDevHandle; /*0x1C */ 2826 U8 2827 ChangeCount; /*0x1E */ 2828 U8 2829 NegotiatedLinkRate; /*0x1F */ 2830 U8 2831 PhyIdentifier; /*0x20 */ 2832 U8 2833 AttachedPhyIdentifier; /*0x21 */ 2834 U8 2835 Reserved3; /*0x22 */ 2836 U8 2837 DiscoveryInfo; /*0x23 */ 2838 U32 2839 AttachedPhyInfo; /*0x24 */ 2840 U8 2841 ZoneGroup; /*0x28 */ 2842 U8 2843 SelfConfigStatus; /*0x29 */ 2844 U16 2845 Reserved4; /*0x2A */ 2846 } MPI2_CONFIG_PAGE_EXPANDER_1, 2847 *PTR_MPI2_CONFIG_PAGE_EXPANDER_1, 2848 Mpi2ExpanderPage1_t, *pMpi2ExpanderPage1_t; 2849 2850 #define MPI2_SASEXPANDER1_PAGEVERSION (0x02) 2851 2852 /*use MPI2_SAS_PRATE_ defines for the ProgrammedLinkRate field */ 2853 2854 /*use MPI2_SAS_HWRATE_ defines for the HwLinkRate field */ 2855 2856 /*use MPI2_SAS_PHYINFO_ for the PhyInfo field */ 2857 2858 /*see mpi2_sas.h for the MPI2_SAS_DEVICE_INFO_ defines 2859 *used for the AttachedDeviceInfo field */ 2860 2861 /*use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */ 2862 2863 /*values for SAS Expander Page 1 DiscoveryInfo field */ 2864 #define MPI2_SAS_EXPANDER1_DISCINFO_BAD_PHY_DISABLED (0x04) 2865 #define MPI2_SAS_EXPANDER1_DISCINFO_LINK_STATUS_CHANGE (0x02) 2866 #define MPI2_SAS_EXPANDER1_DISCINFO_NO_ROUTING_ENTRIES (0x01) 2867 2868 /*use MPI2_SAS_APHYINFO_ defines for AttachedPhyInfo field */ 2869 2870 2871 /**************************************************************************** 2872 * SAS Device Config Pages 2873 ****************************************************************************/ 2874 2875 /*SAS Device Page 0 */ 2876 2877 typedef struct _MPI2_CONFIG_PAGE_SAS_DEV_0 { 2878 MPI2_CONFIG_EXTENDED_PAGE_HEADER 2879 Header; /*0x00 */ 2880 U16 2881 Slot; /*0x08 */ 2882 U16 2883 EnclosureHandle; /*0x0A */ 2884 U64 2885 SASAddress; /*0x0C */ 2886 U16 2887 ParentDevHandle; /*0x14 */ 2888 U8 2889 PhyNum; /*0x16 */ 2890 U8 2891 AccessStatus; /*0x17 */ 2892 U16 2893 DevHandle; /*0x18 */ 2894 U8 2895 AttachedPhyIdentifier; /*0x1A */ 2896 U8 2897 ZoneGroup; /*0x1B */ 2898 U32 2899 DeviceInfo; /*0x1C */ 2900 U16 2901 Flags; /*0x20 */ 2902 U8 2903 PhysicalPort; /*0x22 */ 2904 U8 2905 MaxPortConnections; /*0x23 */ 2906 U64 2907 DeviceName; /*0x24 */ 2908 U8 2909 PortGroups; /*0x2C */ 2910 U8 2911 DmaGroup; /*0x2D */ 2912 U8 2913 ControlGroup; /*0x2E */ 2914 U8 2915 EnclosureLevel; /*0x2F */ 2916 U32 2917 ConnectorName[4]; /*0x30 */ 2918 U32 2919 Reserved3; /*0x34 */ 2920 } MPI2_CONFIG_PAGE_SAS_DEV_0, 2921 *PTR_MPI2_CONFIG_PAGE_SAS_DEV_0, 2922 Mpi2SasDevicePage0_t, 2923 *pMpi2SasDevicePage0_t; 2924 2925 #define MPI2_SASDEVICE0_PAGEVERSION (0x09) 2926 2927 /*values for SAS Device Page 0 AccessStatus field */ 2928 #define MPI2_SAS_DEVICE0_ASTATUS_NO_ERRORS (0x00) 2929 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_INIT_FAILED (0x01) 2930 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_CAPABILITY_FAILED (0x02) 2931 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_AFFILIATION_CONFLICT (0x03) 2932 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_NEEDS_INITIALIZATION (0x04) 2933 #define MPI2_SAS_DEVICE0_ASTATUS_ROUTE_NOT_ADDRESSABLE (0x05) 2934 #define MPI2_SAS_DEVICE0_ASTATUS_SMP_ERROR_NOT_ADDRESSABLE (0x06) 2935 #define MPI2_SAS_DEVICE0_ASTATUS_DEVICE_BLOCKED (0x07) 2936 /*specific values for SATA Init failures */ 2937 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_UNKNOWN (0x10) 2938 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_AFFILIATION_CONFLICT (0x11) 2939 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_DIAG (0x12) 2940 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_IDENTIFICATION (0x13) 2941 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_CHECK_POWER (0x14) 2942 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_PIO_SN (0x15) 2943 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_MDMA_SN (0x16) 2944 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_UDMA_SN (0x17) 2945 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_ZONING_VIOLATION (0x18) 2946 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_NOT_ADDRESSABLE (0x19) 2947 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_MAX (0x1F) 2948 2949 /*see mpi2_sas.h for values for SAS Device Page 0 DeviceInfo values */ 2950 2951 /*values for SAS Device Page 0 Flags field */ 2952 #define MPI2_SAS_DEVICE0_FLAGS_UNAUTHORIZED_DEVICE (0x8000) 2953 #define MPI25_SAS_DEVICE0_FLAGS_ENABLED_FAST_PATH (0x4000) 2954 #define MPI25_SAS_DEVICE0_FLAGS_FAST_PATH_CAPABLE (0x2000) 2955 #define MPI2_SAS_DEVICE0_FLAGS_SLUMBER_PM_CAPABLE (0x1000) 2956 #define MPI2_SAS_DEVICE0_FLAGS_PARTIAL_PM_CAPABLE (0x0800) 2957 #define MPI2_SAS_DEVICE0_FLAGS_SATA_ASYNCHRONOUS_NOTIFY (0x0400) 2958 #define MPI2_SAS_DEVICE0_FLAGS_SATA_SW_PRESERVE (0x0200) 2959 #define MPI2_SAS_DEVICE0_FLAGS_UNSUPPORTED_DEVICE (0x0100) 2960 #define MPI2_SAS_DEVICE0_FLAGS_SATA_48BIT_LBA_SUPPORTED (0x0080) 2961 #define MPI2_SAS_DEVICE0_FLAGS_SATA_SMART_SUPPORTED (0x0040) 2962 #define MPI2_SAS_DEVICE0_FLAGS_SATA_NCQ_SUPPORTED (0x0020) 2963 #define MPI2_SAS_DEVICE0_FLAGS_SATA_FUA_SUPPORTED (0x0010) 2964 #define MPI2_SAS_DEVICE0_FLAGS_PORT_SELECTOR_ATTACH (0x0008) 2965 #define MPI2_SAS_DEVICE0_FLAGS_PERSIST_CAPABLE (0x0004) 2966 #define MPI2_SAS_DEVICE0_FLAGS_ENCL_LEVEL_VALID (0x0002) 2967 #define MPI2_SAS_DEVICE0_FLAGS_DEVICE_PRESENT (0x0001) 2968 2969 2970 /*SAS Device Page 1 */ 2971 2972 typedef struct _MPI2_CONFIG_PAGE_SAS_DEV_1 { 2973 MPI2_CONFIG_EXTENDED_PAGE_HEADER 2974 Header; /*0x00 */ 2975 U32 2976 Reserved1; /*0x08 */ 2977 U64 2978 SASAddress; /*0x0C */ 2979 U32 2980 Reserved2; /*0x14 */ 2981 U16 2982 DevHandle; /*0x18 */ 2983 U16 2984 Reserved3; /*0x1A */ 2985 U8 2986 InitialRegDeviceFIS[20];/*0x1C */ 2987 } MPI2_CONFIG_PAGE_SAS_DEV_1, 2988 *PTR_MPI2_CONFIG_PAGE_SAS_DEV_1, 2989 Mpi2SasDevicePage1_t, 2990 *pMpi2SasDevicePage1_t; 2991 2992 #define MPI2_SASDEVICE1_PAGEVERSION (0x01) 2993 2994 2995 /**************************************************************************** 2996 * SAS PHY Config Pages 2997 ****************************************************************************/ 2998 2999 /*SAS PHY Page 0 */ 3000 3001 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_0 { 3002 MPI2_CONFIG_EXTENDED_PAGE_HEADER 3003 Header; /*0x00 */ 3004 U16 3005 OwnerDevHandle; /*0x08 */ 3006 U16 3007 Reserved1; /*0x0A */ 3008 U16 3009 AttachedDevHandle; /*0x0C */ 3010 U8 3011 AttachedPhyIdentifier; /*0x0E */ 3012 U8 3013 Reserved2; /*0x0F */ 3014 U32 3015 AttachedPhyInfo; /*0x10 */ 3016 U8 3017 ProgrammedLinkRate; /*0x14 */ 3018 U8 3019 HwLinkRate; /*0x15 */ 3020 U8 3021 ChangeCount; /*0x16 */ 3022 U8 3023 Flags; /*0x17 */ 3024 U32 3025 PhyInfo; /*0x18 */ 3026 U8 3027 NegotiatedLinkRate; /*0x1C */ 3028 U8 3029 Reserved3; /*0x1D */ 3030 U16 3031 Reserved4; /*0x1E */ 3032 } MPI2_CONFIG_PAGE_SAS_PHY_0, 3033 *PTR_MPI2_CONFIG_PAGE_SAS_PHY_0, 3034 Mpi2SasPhyPage0_t, *pMpi2SasPhyPage0_t; 3035 3036 #define MPI2_SASPHY0_PAGEVERSION (0x03) 3037 3038 /*use MPI2_SAS_APHYINFO_ defines for AttachedPhyInfo field */ 3039 3040 /*use MPI2_SAS_PRATE_ defines for the ProgrammedLinkRate field */ 3041 3042 /*use MPI2_SAS_HWRATE_ defines for the HwLinkRate field */ 3043 3044 /*values for SAS PHY Page 0 Flags field */ 3045 #define MPI2_SAS_PHY0_FLAGS_SGPIO_DIRECT_ATTACH_ENC (0x01) 3046 3047 /*use MPI2_SAS_PHYINFO_ for the PhyInfo field */ 3048 3049 /*use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */ 3050 3051 3052 /*SAS PHY Page 1 */ 3053 3054 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_1 { 3055 MPI2_CONFIG_EXTENDED_PAGE_HEADER 3056 Header; /*0x00 */ 3057 U32 3058 Reserved1; /*0x08 */ 3059 U32 3060 InvalidDwordCount; /*0x0C */ 3061 U32 3062 RunningDisparityErrorCount; /*0x10 */ 3063 U32 3064 LossDwordSynchCount; /*0x14 */ 3065 U32 3066 PhyResetProblemCount; /*0x18 */ 3067 } MPI2_CONFIG_PAGE_SAS_PHY_1, 3068 *PTR_MPI2_CONFIG_PAGE_SAS_PHY_1, 3069 Mpi2SasPhyPage1_t, *pMpi2SasPhyPage1_t; 3070 3071 #define MPI2_SASPHY1_PAGEVERSION (0x01) 3072 3073 3074 /*SAS PHY Page 2 */ 3075 3076 typedef struct _MPI2_SASPHY2_PHY_EVENT { 3077 U8 PhyEventCode; /*0x00 */ 3078 U8 Reserved1; /*0x01 */ 3079 U16 Reserved2; /*0x02 */ 3080 U32 PhyEventInfo; /*0x04 */ 3081 } MPI2_SASPHY2_PHY_EVENT, *PTR_MPI2_SASPHY2_PHY_EVENT, 3082 Mpi2SasPhy2PhyEvent_t, *pMpi2SasPhy2PhyEvent_t; 3083 3084 /*use MPI2_SASPHY3_EVENT_CODE_ for the PhyEventCode field */ 3085 3086 3087 /* 3088 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 3089 *one and check the value returned for NumPhyEvents at runtime. 3090 */ 3091 #ifndef MPI2_SASPHY2_PHY_EVENT_MAX 3092 #define MPI2_SASPHY2_PHY_EVENT_MAX (1) 3093 #endif 3094 3095 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_2 { 3096 MPI2_CONFIG_EXTENDED_PAGE_HEADER 3097 Header; /*0x00 */ 3098 U32 3099 Reserved1; /*0x08 */ 3100 U8 3101 NumPhyEvents; /*0x0C */ 3102 U8 3103 Reserved2; /*0x0D */ 3104 U16 3105 Reserved3; /*0x0E */ 3106 MPI2_SASPHY2_PHY_EVENT 3107 PhyEvent[MPI2_SASPHY2_PHY_EVENT_MAX]; /*0x10 */ 3108 } MPI2_CONFIG_PAGE_SAS_PHY_2, 3109 *PTR_MPI2_CONFIG_PAGE_SAS_PHY_2, 3110 Mpi2SasPhyPage2_t, 3111 *pMpi2SasPhyPage2_t; 3112 3113 #define MPI2_SASPHY2_PAGEVERSION (0x00) 3114 3115 3116 /*SAS PHY Page 3 */ 3117 3118 typedef struct _MPI2_SASPHY3_PHY_EVENT_CONFIG { 3119 U8 PhyEventCode; /*0x00 */ 3120 U8 Reserved1; /*0x01 */ 3121 U16 Reserved2; /*0x02 */ 3122 U8 CounterType; /*0x04 */ 3123 U8 ThresholdWindow; /*0x05 */ 3124 U8 TimeUnits; /*0x06 */ 3125 U8 Reserved3; /*0x07 */ 3126 U32 EventThreshold; /*0x08 */ 3127 U16 ThresholdFlags; /*0x0C */ 3128 U16 Reserved4; /*0x0E */ 3129 } MPI2_SASPHY3_PHY_EVENT_CONFIG, 3130 *PTR_MPI2_SASPHY3_PHY_EVENT_CONFIG, 3131 Mpi2SasPhy3PhyEventConfig_t, 3132 *pMpi2SasPhy3PhyEventConfig_t; 3133 3134 /*values for PhyEventCode field */ 3135 #define MPI2_SASPHY3_EVENT_CODE_NO_EVENT (0x00) 3136 #define MPI2_SASPHY3_EVENT_CODE_INVALID_DWORD (0x01) 3137 #define MPI2_SASPHY3_EVENT_CODE_RUNNING_DISPARITY_ERROR (0x02) 3138 #define MPI2_SASPHY3_EVENT_CODE_LOSS_DWORD_SYNC (0x03) 3139 #define MPI2_SASPHY3_EVENT_CODE_PHY_RESET_PROBLEM (0x04) 3140 #define MPI2_SASPHY3_EVENT_CODE_ELASTICITY_BUF_OVERFLOW (0x05) 3141 #define MPI2_SASPHY3_EVENT_CODE_RX_ERROR (0x06) 3142 #define MPI2_SASPHY3_EVENT_CODE_RX_ADDR_FRAME_ERROR (0x20) 3143 #define MPI2_SASPHY3_EVENT_CODE_TX_AC_OPEN_REJECT (0x21) 3144 #define MPI2_SASPHY3_EVENT_CODE_RX_AC_OPEN_REJECT (0x22) 3145 #define MPI2_SASPHY3_EVENT_CODE_TX_RC_OPEN_REJECT (0x23) 3146 #define MPI2_SASPHY3_EVENT_CODE_RX_RC_OPEN_REJECT (0x24) 3147 #define MPI2_SASPHY3_EVENT_CODE_RX_AIP_PARTIAL_WAITING_ON (0x25) 3148 #define MPI2_SASPHY3_EVENT_CODE_RX_AIP_CONNECT_WAITING_ON (0x26) 3149 #define MPI2_SASPHY3_EVENT_CODE_TX_BREAK (0x27) 3150 #define MPI2_SASPHY3_EVENT_CODE_RX_BREAK (0x28) 3151 #define MPI2_SASPHY3_EVENT_CODE_BREAK_TIMEOUT (0x29) 3152 #define MPI2_SASPHY3_EVENT_CODE_CONNECTION (0x2A) 3153 #define MPI2_SASPHY3_EVENT_CODE_PEAKTX_PATHWAY_BLOCKED (0x2B) 3154 #define MPI2_SASPHY3_EVENT_CODE_PEAKTX_ARB_WAIT_TIME (0x2C) 3155 #define MPI2_SASPHY3_EVENT_CODE_PEAK_ARB_WAIT_TIME (0x2D) 3156 #define MPI2_SASPHY3_EVENT_CODE_PEAK_CONNECT_TIME (0x2E) 3157 #define MPI2_SASPHY3_EVENT_CODE_TX_SSP_FRAMES (0x40) 3158 #define MPI2_SASPHY3_EVENT_CODE_RX_SSP_FRAMES (0x41) 3159 #define MPI2_SASPHY3_EVENT_CODE_TX_SSP_ERROR_FRAMES (0x42) 3160 #define MPI2_SASPHY3_EVENT_CODE_RX_SSP_ERROR_FRAMES (0x43) 3161 #define MPI2_SASPHY3_EVENT_CODE_TX_CREDIT_BLOCKED (0x44) 3162 #define MPI2_SASPHY3_EVENT_CODE_RX_CREDIT_BLOCKED (0x45) 3163 #define MPI2_SASPHY3_EVENT_CODE_TX_SATA_FRAMES (0x50) 3164 #define MPI2_SASPHY3_EVENT_CODE_RX_SATA_FRAMES (0x51) 3165 #define MPI2_SASPHY3_EVENT_CODE_SATA_OVERFLOW (0x52) 3166 #define MPI2_SASPHY3_EVENT_CODE_TX_SMP_FRAMES (0x60) 3167 #define MPI2_SASPHY3_EVENT_CODE_RX_SMP_FRAMES (0x61) 3168 #define MPI2_SASPHY3_EVENT_CODE_RX_SMP_ERROR_FRAMES (0x63) 3169 #define MPI2_SASPHY3_EVENT_CODE_HOTPLUG_TIMEOUT (0xD0) 3170 #define MPI2_SASPHY3_EVENT_CODE_MISALIGNED_MUX_PRIMITIVE (0xD1) 3171 #define MPI2_SASPHY3_EVENT_CODE_RX_AIP (0xD2) 3172 3173 /*Following codes are product specific and in MPI v2.6 and later */ 3174 #define MPI2_SASPHY3_EVENT_CODE_LCARB_WAIT_TIME (0xD3) 3175 #define MPI2_SASPHY3_EVENT_CODE_RCVD_CONN_RESP_WAIT_TIME (0xD4) 3176 #define MPI2_SASPHY3_EVENT_CODE_LCCONN_TIME (0xD5) 3177 #define MPI2_SASPHY3_EVENT_CODE_SSP_TX_START_TRANSMIT (0xD6) 3178 #define MPI2_SASPHY3_EVENT_CODE_SATA_TX_START (0xD7) 3179 #define MPI2_SASPHY3_EVENT_CODE_SMP_TX_START_TRANSMT (0xD8) 3180 #define MPI2_SASPHY3_EVENT_CODE_TX_SMP_BREAK_CONN (0xD9) 3181 #define MPI2_SASPHY3_EVENT_CODE_SSP_RX_START_RECEIVE (0xDA) 3182 #define MPI2_SASPHY3_EVENT_CODE_SATA_RX_START_RECEIVE (0xDB) 3183 #define MPI2_SASPHY3_EVENT_CODE_SMP_RX_START_RECEIVE (0xDC) 3184 3185 3186 /*values for the CounterType field */ 3187 #define MPI2_SASPHY3_COUNTER_TYPE_WRAPPING (0x00) 3188 #define MPI2_SASPHY3_COUNTER_TYPE_SATURATING (0x01) 3189 #define MPI2_SASPHY3_COUNTER_TYPE_PEAK_VALUE (0x02) 3190 3191 /*values for the TimeUnits field */ 3192 #define MPI2_SASPHY3_TIME_UNITS_10_MICROSECONDS (0x00) 3193 #define MPI2_SASPHY3_TIME_UNITS_100_MICROSECONDS (0x01) 3194 #define MPI2_SASPHY3_TIME_UNITS_1_MILLISECOND (0x02) 3195 #define MPI2_SASPHY3_TIME_UNITS_10_MILLISECONDS (0x03) 3196 3197 /*values for the ThresholdFlags field */ 3198 #define MPI2_SASPHY3_TFLAGS_PHY_RESET (0x0002) 3199 #define MPI2_SASPHY3_TFLAGS_EVENT_NOTIFY (0x0001) 3200 3201 /* 3202 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 3203 *one and check the value returned for NumPhyEvents at runtime. 3204 */ 3205 #ifndef MPI2_SASPHY3_PHY_EVENT_MAX 3206 #define MPI2_SASPHY3_PHY_EVENT_MAX (1) 3207 #endif 3208 3209 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_3 { 3210 MPI2_CONFIG_EXTENDED_PAGE_HEADER 3211 Header; /*0x00 */ 3212 U32 3213 Reserved1; /*0x08 */ 3214 U8 3215 NumPhyEvents; /*0x0C */ 3216 U8 3217 Reserved2; /*0x0D */ 3218 U16 3219 Reserved3; /*0x0E */ 3220 MPI2_SASPHY3_PHY_EVENT_CONFIG 3221 PhyEventConfig[MPI2_SASPHY3_PHY_EVENT_MAX]; /*0x10 */ 3222 } MPI2_CONFIG_PAGE_SAS_PHY_3, 3223 *PTR_MPI2_CONFIG_PAGE_SAS_PHY_3, 3224 Mpi2SasPhyPage3_t, *pMpi2SasPhyPage3_t; 3225 3226 #define MPI2_SASPHY3_PAGEVERSION (0x00) 3227 3228 3229 /*SAS PHY Page 4 */ 3230 3231 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_4 { 3232 MPI2_CONFIG_EXTENDED_PAGE_HEADER 3233 Header; /*0x00 */ 3234 U16 3235 Reserved1; /*0x08 */ 3236 U8 3237 Reserved2; /*0x0A */ 3238 U8 3239 Flags; /*0x0B */ 3240 U8 3241 InitialFrame[28]; /*0x0C */ 3242 } MPI2_CONFIG_PAGE_SAS_PHY_4, 3243 *PTR_MPI2_CONFIG_PAGE_SAS_PHY_4, 3244 Mpi2SasPhyPage4_t, *pMpi2SasPhyPage4_t; 3245 3246 #define MPI2_SASPHY4_PAGEVERSION (0x00) 3247 3248 /*values for the Flags field */ 3249 #define MPI2_SASPHY4_FLAGS_FRAME_VALID (0x02) 3250 #define MPI2_SASPHY4_FLAGS_SATA_FRAME (0x01) 3251 3252 3253 3254 3255 /**************************************************************************** 3256 * SAS Port Config Pages 3257 ****************************************************************************/ 3258 3259 /*SAS Port Page 0 */ 3260 3261 typedef struct _MPI2_CONFIG_PAGE_SAS_PORT_0 { 3262 MPI2_CONFIG_EXTENDED_PAGE_HEADER 3263 Header; /*0x00 */ 3264 U8 3265 PortNumber; /*0x08 */ 3266 U8 3267 PhysicalPort; /*0x09 */ 3268 U8 3269 PortWidth; /*0x0A */ 3270 U8 3271 PhysicalPortWidth; /*0x0B */ 3272 U8 3273 ZoneGroup; /*0x0C */ 3274 U8 3275 Reserved1; /*0x0D */ 3276 U16 3277 Reserved2; /*0x0E */ 3278 U64 3279 SASAddress; /*0x10 */ 3280 U32 3281 DeviceInfo; /*0x18 */ 3282 U32 3283 Reserved3; /*0x1C */ 3284 U32 3285 Reserved4; /*0x20 */ 3286 } MPI2_CONFIG_PAGE_SAS_PORT_0, 3287 *PTR_MPI2_CONFIG_PAGE_SAS_PORT_0, 3288 Mpi2SasPortPage0_t, *pMpi2SasPortPage0_t; 3289 3290 #define MPI2_SASPORT0_PAGEVERSION (0x00) 3291 3292 /*see mpi2_sas.h for values for SAS Port Page 0 DeviceInfo values */ 3293 3294 3295 /**************************************************************************** 3296 * SAS Enclosure Config Pages 3297 ****************************************************************************/ 3298 3299 /*SAS Enclosure Page 0 */ 3300 3301 typedef struct _MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0 { 3302 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */ 3303 U32 Reserved1; /*0x08 */ 3304 U64 EnclosureLogicalID; /*0x0C */ 3305 U16 Flags; /*0x14 */ 3306 U16 EnclosureHandle; /*0x16 */ 3307 U16 NumSlots; /*0x18 */ 3308 U16 StartSlot; /*0x1A */ 3309 U8 ChassisSlot; /*0x1C */ 3310 U8 EnclosureLevel; /*0x1D */ 3311 U16 SEPDevHandle; /*0x1E */ 3312 U8 OEMRD; /*0x20 */ 3313 U8 Reserved1a; /*0x21 */ 3314 U16 Reserved2; /*0x22 */ 3315 U32 Reserved3; /*0x24 */ 3316 } MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0, 3317 *PTR_MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0, 3318 Mpi2SasEnclosurePage0_t, *pMpi2SasEnclosurePage0_t, 3319 MPI26_CONFIG_PAGE_ENCLOSURE_0, 3320 *PTR_MPI26_CONFIG_PAGE_ENCLOSURE_0, 3321 Mpi26EnclosurePage0_t, *pMpi26EnclosurePage0_t; 3322 3323 #define MPI2_SASENCLOSURE0_PAGEVERSION (0x04) 3324 3325 /*values for SAS Enclosure Page 0 Flags field */ 3326 #define MPI26_SAS_ENCLS0_FLAGS_OEMRD_VALID (0x0080) 3327 #define MPI26_SAS_ENCLS0_FLAGS_OEMRD_COLLECTING (0x0040) 3328 #define MPI2_SAS_ENCLS0_FLAGS_CHASSIS_SLOT_VALID (0x0020) 3329 #define MPI2_SAS_ENCLS0_FLAGS_ENCL_LEVEL_VALID (0x0010) 3330 #define MPI2_SAS_ENCLS0_FLAGS_MNG_MASK (0x000F) 3331 #define MPI2_SAS_ENCLS0_FLAGS_MNG_UNKNOWN (0x0000) 3332 #define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_SES (0x0001) 3333 #define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_SGPIO (0x0002) 3334 #define MPI2_SAS_ENCLS0_FLAGS_MNG_EXP_SGPIO (0x0003) 3335 #define MPI2_SAS_ENCLS0_FLAGS_MNG_SES_ENCLOSURE (0x0004) 3336 #define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_GPIO (0x0005) 3337 3338 #define MPI26_ENCLOSURE0_PAGEVERSION (0x04) 3339 3340 /*Values for Enclosure Page 0 Flags field */ 3341 #define MPI26_ENCLS0_FLAGS_OEMRD_VALID (0x0080) 3342 #define MPI26_ENCLS0_FLAGS_OEMRD_COLLECTING (0x0040) 3343 #define MPI26_ENCLS0_FLAGS_CHASSIS_SLOT_VALID (0x0020) 3344 #define MPI26_ENCLS0_FLAGS_ENCL_LEVEL_VALID (0x0010) 3345 #define MPI26_ENCLS0_FLAGS_MNG_MASK (0x000F) 3346 #define MPI26_ENCLS0_FLAGS_MNG_UNKNOWN (0x0000) 3347 #define MPI26_ENCLS0_FLAGS_MNG_IOC_SES (0x0001) 3348 #define MPI26_ENCLS0_FLAGS_MNG_IOC_SGPIO (0x0002) 3349 #define MPI26_ENCLS0_FLAGS_MNG_EXP_SGPIO (0x0003) 3350 #define MPI26_ENCLS0_FLAGS_MNG_SES_ENCLOSURE (0x0004) 3351 #define MPI26_ENCLS0_FLAGS_MNG_IOC_GPIO (0x0005) 3352 3353 /**************************************************************************** 3354 * Log Config Page 3355 ****************************************************************************/ 3356 3357 /*Log Page 0 */ 3358 3359 /* 3360 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 3361 *one and check the value returned for NumLogEntries at runtime. 3362 */ 3363 #ifndef MPI2_LOG_0_NUM_LOG_ENTRIES 3364 #define MPI2_LOG_0_NUM_LOG_ENTRIES (1) 3365 #endif 3366 3367 #define MPI2_LOG_0_LOG_DATA_LENGTH (0x1C) 3368 3369 typedef struct _MPI2_LOG_0_ENTRY { 3370 U64 TimeStamp; /*0x00 */ 3371 U32 Reserved1; /*0x08 */ 3372 U16 LogSequence; /*0x0C */ 3373 U16 LogEntryQualifier; /*0x0E */ 3374 U8 VP_ID; /*0x10 */ 3375 U8 VF_ID; /*0x11 */ 3376 U16 Reserved2; /*0x12 */ 3377 U8 3378 LogData[MPI2_LOG_0_LOG_DATA_LENGTH];/*0x14 */ 3379 } MPI2_LOG_0_ENTRY, *PTR_MPI2_LOG_0_ENTRY, 3380 Mpi2Log0Entry_t, *pMpi2Log0Entry_t; 3381 3382 /*values for Log Page 0 LogEntry LogEntryQualifier field */ 3383 #define MPI2_LOG_0_ENTRY_QUAL_ENTRY_UNUSED (0x0000) 3384 #define MPI2_LOG_0_ENTRY_QUAL_POWER_ON_RESET (0x0001) 3385 #define MPI2_LOG_0_ENTRY_QUAL_TIMESTAMP_UPDATE (0x0002) 3386 #define MPI2_LOG_0_ENTRY_QUAL_MIN_IMPLEMENT_SPEC (0x8000) 3387 #define MPI2_LOG_0_ENTRY_QUAL_MAX_IMPLEMENT_SPEC (0xFFFF) 3388 3389 typedef struct _MPI2_CONFIG_PAGE_LOG_0 { 3390 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */ 3391 U32 Reserved1; /*0x08 */ 3392 U32 Reserved2; /*0x0C */ 3393 U16 NumLogEntries;/*0x10 */ 3394 U16 Reserved3; /*0x12 */ 3395 MPI2_LOG_0_ENTRY 3396 LogEntry[MPI2_LOG_0_NUM_LOG_ENTRIES]; /*0x14 */ 3397 } MPI2_CONFIG_PAGE_LOG_0, *PTR_MPI2_CONFIG_PAGE_LOG_0, 3398 Mpi2LogPage0_t, *pMpi2LogPage0_t; 3399 3400 #define MPI2_LOG_0_PAGEVERSION (0x02) 3401 3402 3403 /**************************************************************************** 3404 * RAID Config Page 3405 ****************************************************************************/ 3406 3407 /*RAID Page 0 */ 3408 3409 /* 3410 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 3411 *one and check the value returned for NumElements at runtime. 3412 */ 3413 #ifndef MPI2_RAIDCONFIG0_MAX_ELEMENTS 3414 #define MPI2_RAIDCONFIG0_MAX_ELEMENTS (1) 3415 #endif 3416 3417 typedef struct _MPI2_RAIDCONFIG0_CONFIG_ELEMENT { 3418 U16 ElementFlags; /*0x00 */ 3419 U16 VolDevHandle; /*0x02 */ 3420 U8 HotSparePool; /*0x04 */ 3421 U8 PhysDiskNum; /*0x05 */ 3422 U16 PhysDiskDevHandle; /*0x06 */ 3423 } MPI2_RAIDCONFIG0_CONFIG_ELEMENT, 3424 *PTR_MPI2_RAIDCONFIG0_CONFIG_ELEMENT, 3425 Mpi2RaidConfig0ConfigElement_t, 3426 *pMpi2RaidConfig0ConfigElement_t; 3427 3428 /*values for the ElementFlags field */ 3429 #define MPI2_RAIDCONFIG0_EFLAGS_MASK_ELEMENT_TYPE (0x000F) 3430 #define MPI2_RAIDCONFIG0_EFLAGS_VOLUME_ELEMENT (0x0000) 3431 #define MPI2_RAIDCONFIG0_EFLAGS_VOL_PHYS_DISK_ELEMENT (0x0001) 3432 #define MPI2_RAIDCONFIG0_EFLAGS_HOT_SPARE_ELEMENT (0x0002) 3433 #define MPI2_RAIDCONFIG0_EFLAGS_OCE_ELEMENT (0x0003) 3434 3435 3436 typedef struct _MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0 { 3437 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */ 3438 U8 NumHotSpares; /*0x08 */ 3439 U8 NumPhysDisks; /*0x09 */ 3440 U8 NumVolumes; /*0x0A */ 3441 U8 ConfigNum; /*0x0B */ 3442 U32 Flags; /*0x0C */ 3443 U8 ConfigGUID[24]; /*0x10 */ 3444 U32 Reserved1; /*0x28 */ 3445 U8 NumElements; /*0x2C */ 3446 U8 Reserved2; /*0x2D */ 3447 U16 Reserved3; /*0x2E */ 3448 MPI2_RAIDCONFIG0_CONFIG_ELEMENT 3449 ConfigElement[MPI2_RAIDCONFIG0_MAX_ELEMENTS]; /*0x30 */ 3450 } MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0, 3451 *PTR_MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0, 3452 Mpi2RaidConfigurationPage0_t, 3453 *pMpi2RaidConfigurationPage0_t; 3454 3455 #define MPI2_RAIDCONFIG0_PAGEVERSION (0x00) 3456 3457 /*values for RAID Configuration Page 0 Flags field */ 3458 #define MPI2_RAIDCONFIG0_FLAG_FOREIGN_CONFIG (0x00000001) 3459 3460 3461 /**************************************************************************** 3462 * Driver Persistent Mapping Config Pages 3463 ****************************************************************************/ 3464 3465 /*Driver Persistent Mapping Page 0 */ 3466 3467 typedef struct _MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY { 3468 U64 PhysicalIdentifier; /*0x00 */ 3469 U16 MappingInformation; /*0x08 */ 3470 U16 DeviceIndex; /*0x0A */ 3471 U32 PhysicalBitsMapping; /*0x0C */ 3472 U32 Reserved1; /*0x10 */ 3473 } MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY, 3474 *PTR_MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY, 3475 Mpi2DriverMap0Entry_t, *pMpi2DriverMap0Entry_t; 3476 3477 typedef struct _MPI2_CONFIG_PAGE_DRIVER_MAPPING_0 { 3478 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */ 3479 MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY Entry; /*0x08 */ 3480 } MPI2_CONFIG_PAGE_DRIVER_MAPPING_0, 3481 *PTR_MPI2_CONFIG_PAGE_DRIVER_MAPPING_0, 3482 Mpi2DriverMappingPage0_t, *pMpi2DriverMappingPage0_t; 3483 3484 #define MPI2_DRIVERMAPPING0_PAGEVERSION (0x00) 3485 3486 /*values for Driver Persistent Mapping Page 0 MappingInformation field */ 3487 #define MPI2_DRVMAP0_MAPINFO_SLOT_MASK (0x07F0) 3488 #define MPI2_DRVMAP0_MAPINFO_SLOT_SHIFT (4) 3489 #define MPI2_DRVMAP0_MAPINFO_MISSING_MASK (0x000F) 3490 3491 3492 /**************************************************************************** 3493 * Ethernet Config Pages 3494 ****************************************************************************/ 3495 3496 /*Ethernet Page 0 */ 3497 3498 /*IP address (union of IPv4 and IPv6) */ 3499 typedef union _MPI2_ETHERNET_IP_ADDR { 3500 U32 IPv4Addr; 3501 U32 IPv6Addr[4]; 3502 } MPI2_ETHERNET_IP_ADDR, *PTR_MPI2_ETHERNET_IP_ADDR, 3503 Mpi2EthernetIpAddr_t, *pMpi2EthernetIpAddr_t; 3504 3505 #define MPI2_ETHERNET_HOST_NAME_LENGTH (32) 3506 3507 typedef struct _MPI2_CONFIG_PAGE_ETHERNET_0 { 3508 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */ 3509 U8 NumInterfaces; /*0x08 */ 3510 U8 Reserved0; /*0x09 */ 3511 U16 Reserved1; /*0x0A */ 3512 U32 Status; /*0x0C */ 3513 U8 MediaState; /*0x10 */ 3514 U8 Reserved2; /*0x11 */ 3515 U16 Reserved3; /*0x12 */ 3516 U8 MacAddress[6]; /*0x14 */ 3517 U8 Reserved4; /*0x1A */ 3518 U8 Reserved5; /*0x1B */ 3519 MPI2_ETHERNET_IP_ADDR IpAddress; /*0x1C */ 3520 MPI2_ETHERNET_IP_ADDR SubnetMask; /*0x2C */ 3521 MPI2_ETHERNET_IP_ADDR GatewayIpAddress;/*0x3C */ 3522 MPI2_ETHERNET_IP_ADDR DNS1IpAddress; /*0x4C */ 3523 MPI2_ETHERNET_IP_ADDR DNS2IpAddress; /*0x5C */ 3524 MPI2_ETHERNET_IP_ADDR DhcpIpAddress; /*0x6C */ 3525 U8 3526 HostName[MPI2_ETHERNET_HOST_NAME_LENGTH];/*0x7C */ 3527 } MPI2_CONFIG_PAGE_ETHERNET_0, 3528 *PTR_MPI2_CONFIG_PAGE_ETHERNET_0, 3529 Mpi2EthernetPage0_t, *pMpi2EthernetPage0_t; 3530 3531 #define MPI2_ETHERNETPAGE0_PAGEVERSION (0x00) 3532 3533 /*values for Ethernet Page 0 Status field */ 3534 #define MPI2_ETHPG0_STATUS_IPV6_CAPABLE (0x80000000) 3535 #define MPI2_ETHPG0_STATUS_IPV4_CAPABLE (0x40000000) 3536 #define MPI2_ETHPG0_STATUS_CONSOLE_CONNECTED (0x20000000) 3537 #define MPI2_ETHPG0_STATUS_DEFAULT_IF (0x00000100) 3538 #define MPI2_ETHPG0_STATUS_FW_DWNLD_ENABLED (0x00000080) 3539 #define MPI2_ETHPG0_STATUS_TELNET_ENABLED (0x00000040) 3540 #define MPI2_ETHPG0_STATUS_SSH2_ENABLED (0x00000020) 3541 #define MPI2_ETHPG0_STATUS_DHCP_CLIENT_ENABLED (0x00000010) 3542 #define MPI2_ETHPG0_STATUS_IPV6_ENABLED (0x00000008) 3543 #define MPI2_ETHPG0_STATUS_IPV4_ENABLED (0x00000004) 3544 #define MPI2_ETHPG0_STATUS_IPV6_ADDRESSES (0x00000002) 3545 #define MPI2_ETHPG0_STATUS_ETH_IF_ENABLED (0x00000001) 3546 3547 /*values for Ethernet Page 0 MediaState field */ 3548 #define MPI2_ETHPG0_MS_DUPLEX_MASK (0x80) 3549 #define MPI2_ETHPG0_MS_HALF_DUPLEX (0x00) 3550 #define MPI2_ETHPG0_MS_FULL_DUPLEX (0x80) 3551 3552 #define MPI2_ETHPG0_MS_CONNECT_SPEED_MASK (0x07) 3553 #define MPI2_ETHPG0_MS_NOT_CONNECTED (0x00) 3554 #define MPI2_ETHPG0_MS_10MBIT (0x01) 3555 #define MPI2_ETHPG0_MS_100MBIT (0x02) 3556 #define MPI2_ETHPG0_MS_1GBIT (0x03) 3557 3558 3559 /*Ethernet Page 1 */ 3560 3561 typedef struct _MPI2_CONFIG_PAGE_ETHERNET_1 { 3562 MPI2_CONFIG_EXTENDED_PAGE_HEADER 3563 Header; /*0x00 */ 3564 U32 3565 Reserved0; /*0x08 */ 3566 U32 3567 Flags; /*0x0C */ 3568 U8 3569 MediaState; /*0x10 */ 3570 U8 3571 Reserved1; /*0x11 */ 3572 U16 3573 Reserved2; /*0x12 */ 3574 U8 3575 MacAddress[6]; /*0x14 */ 3576 U8 3577 Reserved3; /*0x1A */ 3578 U8 3579 Reserved4; /*0x1B */ 3580 MPI2_ETHERNET_IP_ADDR 3581 StaticIpAddress; /*0x1C */ 3582 MPI2_ETHERNET_IP_ADDR 3583 StaticSubnetMask; /*0x2C */ 3584 MPI2_ETHERNET_IP_ADDR 3585 StaticGatewayIpAddress; /*0x3C */ 3586 MPI2_ETHERNET_IP_ADDR 3587 StaticDNS1IpAddress; /*0x4C */ 3588 MPI2_ETHERNET_IP_ADDR 3589 StaticDNS2IpAddress; /*0x5C */ 3590 U32 3591 Reserved5; /*0x6C */ 3592 U32 3593 Reserved6; /*0x70 */ 3594 U32 3595 Reserved7; /*0x74 */ 3596 U32 3597 Reserved8; /*0x78 */ 3598 U8 3599 HostName[MPI2_ETHERNET_HOST_NAME_LENGTH];/*0x7C */ 3600 } MPI2_CONFIG_PAGE_ETHERNET_1, 3601 *PTR_MPI2_CONFIG_PAGE_ETHERNET_1, 3602 Mpi2EthernetPage1_t, *pMpi2EthernetPage1_t; 3603 3604 #define MPI2_ETHERNETPAGE1_PAGEVERSION (0x00) 3605 3606 /*values for Ethernet Page 1 Flags field */ 3607 #define MPI2_ETHPG1_FLAG_SET_DEFAULT_IF (0x00000100) 3608 #define MPI2_ETHPG1_FLAG_ENABLE_FW_DOWNLOAD (0x00000080) 3609 #define MPI2_ETHPG1_FLAG_ENABLE_TELNET (0x00000040) 3610 #define MPI2_ETHPG1_FLAG_ENABLE_SSH2 (0x00000020) 3611 #define MPI2_ETHPG1_FLAG_ENABLE_DHCP_CLIENT (0x00000010) 3612 #define MPI2_ETHPG1_FLAG_ENABLE_IPV6 (0x00000008) 3613 #define MPI2_ETHPG1_FLAG_ENABLE_IPV4 (0x00000004) 3614 #define MPI2_ETHPG1_FLAG_USE_IPV6_ADDRESSES (0x00000002) 3615 #define MPI2_ETHPG1_FLAG_ENABLE_ETH_IF (0x00000001) 3616 3617 /*values for Ethernet Page 1 MediaState field */ 3618 #define MPI2_ETHPG1_MS_DUPLEX_MASK (0x80) 3619 #define MPI2_ETHPG1_MS_HALF_DUPLEX (0x00) 3620 #define MPI2_ETHPG1_MS_FULL_DUPLEX (0x80) 3621 3622 #define MPI2_ETHPG1_MS_DATA_RATE_MASK (0x07) 3623 #define MPI2_ETHPG1_MS_DATA_RATE_AUTO (0x00) 3624 #define MPI2_ETHPG1_MS_DATA_RATE_10MBIT (0x01) 3625 #define MPI2_ETHPG1_MS_DATA_RATE_100MBIT (0x02) 3626 #define MPI2_ETHPG1_MS_DATA_RATE_1GBIT (0x03) 3627 3628 3629 /**************************************************************************** 3630 * Extended Manufacturing Config Pages 3631 ****************************************************************************/ 3632 3633 /* 3634 *Generic structure to use for product-specific extended manufacturing pages 3635 *(currently Extended Manufacturing Page 40 through Extended Manufacturing 3636 *Page 60). 3637 */ 3638 3639 typedef struct _MPI2_CONFIG_PAGE_EXT_MAN_PS { 3640 MPI2_CONFIG_EXTENDED_PAGE_HEADER 3641 Header; /*0x00 */ 3642 U32 3643 ProductSpecificInfo; /*0x08 */ 3644 } MPI2_CONFIG_PAGE_EXT_MAN_PS, 3645 *PTR_MPI2_CONFIG_PAGE_EXT_MAN_PS, 3646 Mpi2ExtManufacturingPagePS_t, 3647 *pMpi2ExtManufacturingPagePS_t; 3648 3649 /*PageVersion should be provided by product-specific code */ 3650 3651 3652 3653 /**************************************************************************** 3654 * values for fields used by several types of PCIe Config Pages 3655 ****************************************************************************/ 3656 3657 /*values for NegotiatedLinkRates fields */ 3658 #define MPI26_PCIE_NEG_LINK_RATE_MASK_PHYSICAL (0x0F) 3659 /*link rates used for Negotiated Physical Link Rate */ 3660 #define MPI26_PCIE_NEG_LINK_RATE_UNKNOWN (0x00) 3661 #define MPI26_PCIE_NEG_LINK_RATE_PHY_DISABLED (0x01) 3662 #define MPI26_PCIE_NEG_LINK_RATE_2_5 (0x02) 3663 #define MPI26_PCIE_NEG_LINK_RATE_5_0 (0x03) 3664 #define MPI26_PCIE_NEG_LINK_RATE_8_0 (0x04) 3665 #define MPI26_PCIE_NEG_LINK_RATE_16_0 (0x05) 3666 3667 3668 /**************************************************************************** 3669 * PCIe IO Unit Config Pages (MPI v2.6 and later) 3670 ****************************************************************************/ 3671 3672 /*PCIe IO Unit Page 0 */ 3673 3674 typedef struct _MPI26_PCIE_IO_UNIT0_PHY_DATA { 3675 U8 Link; /*0x00 */ 3676 U8 LinkFlags; /*0x01 */ 3677 U8 PhyFlags; /*0x02 */ 3678 U8 NegotiatedLinkRate; /*0x03 */ 3679 U32 ControllerPhyDeviceInfo;/*0x04 */ 3680 U16 AttachedDevHandle; /*0x08 */ 3681 U16 ControllerDevHandle; /*0x0A */ 3682 U32 EnumerationStatus; /*0x0C */ 3683 U32 Reserved1; /*0x10 */ 3684 } MPI26_PCIE_IO_UNIT0_PHY_DATA, 3685 *PTR_MPI26_PCIE_IO_UNIT0_PHY_DATA, 3686 Mpi26PCIeIOUnit0PhyData_t, *pMpi26PCIeIOUnit0PhyData_t; 3687 3688 /* 3689 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 3690 *one and check the value returned for NumPhys at runtime. 3691 */ 3692 #ifndef MPI26_PCIE_IOUNIT0_PHY_MAX 3693 #define MPI26_PCIE_IOUNIT0_PHY_MAX (1) 3694 #endif 3695 3696 typedef struct _MPI26_CONFIG_PAGE_PIOUNIT_0 { 3697 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */ 3698 U32 Reserved1; /*0x08 */ 3699 U8 NumPhys; /*0x0C */ 3700 U8 InitStatus; /*0x0D */ 3701 U16 Reserved3; /*0x0E */ 3702 MPI26_PCIE_IO_UNIT0_PHY_DATA 3703 PhyData[MPI26_PCIE_IOUNIT0_PHY_MAX]; /*0x10 */ 3704 } MPI26_CONFIG_PAGE_PIOUNIT_0, 3705 *PTR_MPI26_CONFIG_PAGE_PIOUNIT_0, 3706 Mpi26PCIeIOUnitPage0_t, *pMpi26PCIeIOUnitPage0_t; 3707 3708 #define MPI26_PCIEIOUNITPAGE0_PAGEVERSION (0x00) 3709 3710 /*values for PCIe IO Unit Page 0 LinkFlags */ 3711 #define MPI26_PCIEIOUNIT0_LINKFLAGS_ENUMERATION_IN_PROGRESS (0x08) 3712 3713 /*values for PCIe IO Unit Page 0 PhyFlags */ 3714 #define MPI26_PCIEIOUNIT0_PHYFLAGS_PHY_DISABLED (0x08) 3715 3716 /*use MPI26_PCIE_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */ 3717 3718 /*see mpi2_pci.h for values for PCIe IO Unit Page 0 ControllerPhyDeviceInfo 3719 *values 3720 */ 3721 3722 /*values for PCIe IO Unit Page 0 EnumerationStatus */ 3723 #define MPI26_PCIEIOUNIT0_ES_MAX_SWITCHES_EXCEEDED (0x40000000) 3724 #define MPI26_PCIEIOUNIT0_ES_MAX_DEVICES_EXCEEDED (0x20000000) 3725 3726 3727 /*PCIe IO Unit Page 1 */ 3728 3729 typedef struct _MPI26_PCIE_IO_UNIT1_PHY_DATA { 3730 U8 Link; /*0x00 */ 3731 U8 LinkFlags; /*0x01 */ 3732 U8 PhyFlags; /*0x02 */ 3733 U8 MaxMinLinkRate; /*0x03 */ 3734 U32 ControllerPhyDeviceInfo; /*0x04 */ 3735 U32 Reserved1; /*0x08 */ 3736 } MPI26_PCIE_IO_UNIT1_PHY_DATA, 3737 *PTR_MPI26_PCIE_IO_UNIT1_PHY_DATA, 3738 Mpi26PCIeIOUnit1PhyData_t, *pMpi26PCIeIOUnit1PhyData_t; 3739 3740 /*values for LinkFlags */ 3741 #define MPI26_PCIEIOUNIT1_LINKFLAGS_DIS_SEPARATE_REFCLK (0x00) 3742 #define MPI26_PCIEIOUNIT1_LINKFLAGS_SRIS_EN (0x01) 3743 #define MPI26_PCIEIOUNIT1_LINKFLAGS_SRNS_EN (0x02) 3744 3745 /* 3746 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 3747 *one and check the value returned for NumPhys at runtime. 3748 */ 3749 #ifndef MPI26_PCIE_IOUNIT1_PHY_MAX 3750 #define MPI26_PCIE_IOUNIT1_PHY_MAX (1) 3751 #endif 3752 3753 typedef struct _MPI26_CONFIG_PAGE_PIOUNIT_1 { 3754 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */ 3755 U16 ControlFlags; /*0x08 */ 3756 U16 Reserved; /*0x0A */ 3757 U16 AdditionalControlFlags; /*0x0C */ 3758 U16 NVMeMaxQueueDepth; /*0x0E */ 3759 U8 NumPhys; /*0x10 */ 3760 U8 DMDReportPCIe; /*0x11 */ 3761 U16 Reserved2; /*0x12 */ 3762 MPI26_PCIE_IO_UNIT1_PHY_DATA 3763 PhyData[MPI26_PCIE_IOUNIT1_PHY_MAX];/*0x14 */ 3764 } MPI26_CONFIG_PAGE_PIOUNIT_1, 3765 *PTR_MPI26_CONFIG_PAGE_PIOUNIT_1, 3766 Mpi26PCIeIOUnitPage1_t, *pMpi26PCIeIOUnitPage1_t; 3767 3768 #define MPI26_PCIEIOUNITPAGE1_PAGEVERSION (0x00) 3769 3770 /*values for PCIe IO Unit Page 1 PhyFlags */ 3771 #define MPI26_PCIEIOUNIT1_PHYFLAGS_PHY_DISABLE (0x08) 3772 #define MPI26_PCIEIOUNIT1_PHYFLAGS_ENDPOINT_ONLY (0x01) 3773 3774 /*values for PCIe IO Unit Page 1 MaxMinLinkRate */ 3775 #define MPI26_PCIEIOUNIT1_MAX_RATE_MASK (0xF0) 3776 #define MPI26_PCIEIOUNIT1_MAX_RATE_SHIFT (4) 3777 #define MPI26_PCIEIOUNIT1_MAX_RATE_2_5 (0x20) 3778 #define MPI26_PCIEIOUNIT1_MAX_RATE_5_0 (0x30) 3779 #define MPI26_PCIEIOUNIT1_MAX_RATE_8_0 (0x40) 3780 #define MPI26_PCIEIOUNIT1_MAX_RATE_16_0 (0x50) 3781 3782 /*values for PCIe IO Unit Page 1 DMDReportPCIe */ 3783 #define MPI26_PCIEIOUNIT1_DMDRPT_UNIT_MASK (0x80) 3784 #define MPI26_PCIEIOUNIT1_DMDRPT_UNIT_1_SEC (0x00) 3785 #define MPI26_PCIEIOUNIT1_DMDRPT_UNIT_16_SEC (0x80) 3786 #define MPI26_PCIEIOUNIT1_DMDRPT_DELAY_TIME_MASK (0x7F) 3787 3788 /*see mpi2_pci.h for values for PCIe IO Unit Page 0 ControllerPhyDeviceInfo 3789 *values 3790 */ 3791 3792 3793 /**************************************************************************** 3794 * PCIe Switch Config Pages (MPI v2.6 and later) 3795 ****************************************************************************/ 3796 3797 /*PCIe Switch Page 0 */ 3798 3799 typedef struct _MPI26_CONFIG_PAGE_PSWITCH_0 { 3800 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */ 3801 U8 PhysicalPort; /*0x08 */ 3802 U8 Reserved1; /*0x09 */ 3803 U16 Reserved2; /*0x0A */ 3804 U16 DevHandle; /*0x0C */ 3805 U16 ParentDevHandle; /*0x0E */ 3806 U8 NumPorts; /*0x10 */ 3807 U8 PCIeLevel; /*0x11 */ 3808 U16 Reserved3; /*0x12 */ 3809 U32 Reserved4; /*0x14 */ 3810 U32 Reserved5; /*0x18 */ 3811 U32 Reserved6; /*0x1C */ 3812 } MPI26_CONFIG_PAGE_PSWITCH_0, *PTR_MPI26_CONFIG_PAGE_PSWITCH_0, 3813 Mpi26PCIeSwitchPage0_t, *pMpi26PCIeSwitchPage0_t; 3814 3815 #define MPI26_PCIESWITCH0_PAGEVERSION (0x00) 3816 3817 3818 /*PCIe Switch Page 1 */ 3819 3820 typedef struct _MPI26_CONFIG_PAGE_PSWITCH_1 { 3821 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */ 3822 U8 PhysicalPort; /*0x08 */ 3823 U8 Reserved1; /*0x09 */ 3824 U16 Reserved2; /*0x0A */ 3825 U8 NumPorts; /*0x0C */ 3826 U8 PortNum; /*0x0D */ 3827 U16 AttachedDevHandle; /*0x0E */ 3828 U16 SwitchDevHandle; /*0x10 */ 3829 U8 NegotiatedPortWidth; /*0x12 */ 3830 U8 NegotiatedLinkRate; /*0x13 */ 3831 U32 Reserved4; /*0x14 */ 3832 U32 Reserved5; /*0x18 */ 3833 } MPI26_CONFIG_PAGE_PSWITCH_1, *PTR_MPI26_CONFIG_PAGE_PSWITCH_1, 3834 Mpi26PCIeSwitchPage1_t, *pMpi26PCIeSwitchPage1_t; 3835 3836 #define MPI26_PCIESWITCH1_PAGEVERSION (0x00) 3837 3838 /*use MPI26_PCIE_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */ 3839 3840 /* defines for the Flags field */ 3841 #define MPI26_PCIESWITCH1_2_RETIMER_PRESENCE (0x0002) 3842 #define MPI26_PCIESWITCH1_RETIMER_PRESENCE (0x0001) 3843 3844 /**************************************************************************** 3845 * PCIe Device Config Pages (MPI v2.6 and later) 3846 ****************************************************************************/ 3847 3848 /*PCIe Device Page 0 */ 3849 3850 typedef struct _MPI26_CONFIG_PAGE_PCIEDEV_0 { 3851 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */ 3852 U16 Slot; /*0x08 */ 3853 U16 EnclosureHandle; /*0x0A */ 3854 U64 WWID; /*0x0C */ 3855 U16 ParentDevHandle; /*0x14 */ 3856 U8 PortNum; /*0x16 */ 3857 U8 AccessStatus; /*0x17 */ 3858 U16 DevHandle; /*0x18 */ 3859 U8 PhysicalPort; /*0x1A */ 3860 U8 Reserved1; /*0x1B */ 3861 U32 DeviceInfo; /*0x1C */ 3862 U32 Flags; /*0x20 */ 3863 U8 SupportedLinkRates; /*0x24 */ 3864 U8 MaxPortWidth; /*0x25 */ 3865 U8 NegotiatedPortWidth; /*0x26 */ 3866 U8 NegotiatedLinkRate; /*0x27 */ 3867 U8 EnclosureLevel; /*0x28 */ 3868 U8 Reserved2; /*0x29 */ 3869 U16 Reserved3; /*0x2A */ 3870 U8 ConnectorName[4]; /*0x2C */ 3871 U32 Reserved4; /*0x30 */ 3872 U32 Reserved5; /*0x34 */ 3873 } MPI26_CONFIG_PAGE_PCIEDEV_0, *PTR_MPI26_CONFIG_PAGE_PCIEDEV_0, 3874 Mpi26PCIeDevicePage0_t, *pMpi26PCIeDevicePage0_t; 3875 3876 #define MPI26_PCIEDEVICE0_PAGEVERSION (0x01) 3877 3878 /*values for PCIe Device Page 0 AccessStatus field */ 3879 #define MPI26_PCIEDEV0_ASTATUS_NO_ERRORS (0x00) 3880 #define MPI26_PCIEDEV0_ASTATUS_NEEDS_INITIALIZATION (0x04) 3881 #define MPI26_PCIEDEV0_ASTATUS_CAPABILITY_FAILED (0x02) 3882 #define MPI26_PCIEDEV0_ASTATUS_DEVICE_BLOCKED (0x07) 3883 #define MPI26_PCIEDEV0_ASTATUS_MEMORY_SPACE_ACCESS_FAILED (0x08) 3884 #define MPI26_PCIEDEV0_ASTATUS_UNSUPPORTED_DEVICE (0x09) 3885 #define MPI26_PCIEDEV0_ASTATUS_MSIX_REQUIRED (0x0A) 3886 #define MPI26_PCIEDEV0_ASTATUS_UNKNOWN (0x10) 3887 3888 #define MPI26_PCIEDEV0_ASTATUS_NVME_READY_TIMEOUT (0x30) 3889 #define MPI26_PCIEDEV0_ASTATUS_NVME_DEVCFG_UNSUPPORTED (0x31) 3890 #define MPI26_PCIEDEV0_ASTATUS_NVME_IDENTIFY_FAILED (0x32) 3891 #define MPI26_PCIEDEV0_ASTATUS_NVME_QCONFIG_FAILED (0x33) 3892 #define MPI26_PCIEDEV0_ASTATUS_NVME_QCREATION_FAILED (0x34) 3893 #define MPI26_PCIEDEV0_ASTATUS_NVME_EVENTCFG_FAILED (0x35) 3894 #define MPI26_PCIEDEV0_ASTATUS_NVME_GET_FEATURE_STAT_FAILED (0x36) 3895 #define MPI26_PCIEDEV0_ASTATUS_NVME_IDLE_TIMEOUT (0x37) 3896 #define MPI26_PCIEDEV0_ASTATUS_NVME_FAILURE_STATUS (0x38) 3897 3898 #define MPI26_PCIEDEV0_ASTATUS_INIT_FAIL_MAX (0x3F) 3899 3900 /*see mpi2_pci.h for the MPI26_PCIE_DEVINFO_ defines used for the DeviceInfo 3901 *field 3902 */ 3903 3904 /*values for PCIe Device Page 0 Flags field*/ 3905 #define MPI26_PCIEDEV0_FLAGS_2_RETIMER_PRESENCE (0x00020000) 3906 #define MPI26_PCIEDEV0_FLAGS_RETIMER_PRESENCE (0x00010000) 3907 #define MPI26_PCIEDEV0_FLAGS_UNAUTHORIZED_DEVICE (0x00008000) 3908 #define MPI26_PCIEDEV0_FLAGS_ENABLED_FAST_PATH (0x00004000) 3909 #define MPI26_PCIEDEV0_FLAGS_FAST_PATH_CAPABLE (0x00002000) 3910 #define MPI26_PCIEDEV0_FLAGS_ASYNCHRONOUS_NOTIFICATION (0x00000400) 3911 #define MPI26_PCIEDEV0_FLAGS_ATA_SW_PRESERVATION (0x00000200) 3912 #define MPI26_PCIEDEV0_FLAGS_UNSUPPORTED_DEVICE (0x00000100) 3913 #define MPI26_PCIEDEV0_FLAGS_ATA_48BIT_LBA_SUPPORTED (0x00000080) 3914 #define MPI26_PCIEDEV0_FLAGS_ATA_SMART_SUPPORTED (0x00000040) 3915 #define MPI26_PCIEDEV0_FLAGS_ATA_NCQ_SUPPORTED (0x00000020) 3916 #define MPI26_PCIEDEV0_FLAGS_ATA_FUA_SUPPORTED (0x00000010) 3917 #define MPI26_PCIEDEV0_FLAGS_ENCL_LEVEL_VALID (0x00000002) 3918 #define MPI26_PCIEDEV0_FLAGS_DEVICE_PRESENT (0x00000001) 3919 3920 /* values for PCIe Device Page 0 SupportedLinkRates field */ 3921 #define MPI26_PCIEDEV0_LINK_RATE_16_0_SUPPORTED (0x08) 3922 #define MPI26_PCIEDEV0_LINK_RATE_8_0_SUPPORTED (0x04) 3923 #define MPI26_PCIEDEV0_LINK_RATE_5_0_SUPPORTED (0x02) 3924 #define MPI26_PCIEDEV0_LINK_RATE_2_5_SUPPORTED (0x01) 3925 3926 /*use MPI26_PCIE_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */ 3927 3928 3929 /*PCIe Device Page 2 */ 3930 3931 typedef struct _MPI26_CONFIG_PAGE_PCIEDEV_2 { 3932 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */ 3933 U16 DevHandle; /*0x08 */ 3934 U8 ControllerResetTO; /* 0x0A */ 3935 U8 Reserved1; /* 0x0B */ 3936 U32 MaximumDataTransferSize; /*0x0C */ 3937 U32 Capabilities; /*0x10 */ 3938 U16 NOIOB; /* 0x14 */ 3939 U16 ShutdownLatency; /* 0x16 */ 3940 U16 VendorID; /* 0x18 */ 3941 U16 DeviceID; /* 0x1A */ 3942 U16 SubsystemVendorID; /* 0x1C */ 3943 U16 SubsystemID; /* 0x1E */ 3944 U8 RevisionID; /* 0x20 */ 3945 U8 Reserved21[3]; /* 0x21 */ 3946 } MPI26_CONFIG_PAGE_PCIEDEV_2, *PTR_MPI26_CONFIG_PAGE_PCIEDEV_2, 3947 Mpi26PCIeDevicePage2_t, *pMpi26PCIeDevicePage2_t; 3948 3949 #define MPI26_PCIEDEVICE2_PAGEVERSION (0x01) 3950 3951 /*defines for PCIe Device Page 2 Capabilities field */ 3952 #define MPI26_PCIEDEV2_CAP_DATA_BLK_ALIGN_AND_GRAN (0x00000008) 3953 #define MPI26_PCIEDEV2_CAP_SGL_FORMAT (0x00000004) 3954 #define MPI26_PCIEDEV2_CAP_BIT_BUCKET_SUPPORT (0x00000002) 3955 #define MPI26_PCIEDEV2_CAP_SGL_SUPPORT (0x00000001) 3956 3957 /* Defines for the NOIOB field */ 3958 #define MPI26_PCIEDEV2_NOIOB_UNSUPPORTED (0x0000) 3959 3960 /**************************************************************************** 3961 * PCIe Link Config Pages (MPI v2.6 and later) 3962 ****************************************************************************/ 3963 3964 /*PCIe Link Page 1 */ 3965 3966 typedef struct _MPI26_CONFIG_PAGE_PCIELINK_1 { 3967 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */ 3968 U8 Link; /*0x08 */ 3969 U8 Reserved1; /*0x09 */ 3970 U16 Reserved2; /*0x0A */ 3971 U32 CorrectableErrorCount; /*0x0C */ 3972 U16 NonFatalErrorCount; /*0x10 */ 3973 U16 Reserved3; /*0x12 */ 3974 U16 FatalErrorCount; /*0x14 */ 3975 U16 Reserved4; /*0x16 */ 3976 } MPI26_CONFIG_PAGE_PCIELINK_1, *PTR_MPI26_CONFIG_PAGE_PCIELINK_1, 3977 Mpi26PcieLinkPage1_t, *pMpi26PcieLinkPage1_t; 3978 3979 #define MPI26_PCIELINK1_PAGEVERSION (0x00) 3980 3981 /*PCIe Link Page 2 */ 3982 3983 typedef struct _MPI26_PCIELINK2_LINK_EVENT { 3984 U8 LinkEventCode; /*0x00 */ 3985 U8 Reserved1; /*0x01 */ 3986 U16 Reserved2; /*0x02 */ 3987 U32 LinkEventInfo; /*0x04 */ 3988 } MPI26_PCIELINK2_LINK_EVENT, *PTR_MPI26_PCIELINK2_LINK_EVENT, 3989 Mpi26PcieLink2LinkEvent_t, *pMpi26PcieLink2LinkEvent_t; 3990 3991 /*use MPI26_PCIELINK3_EVTCODE_ for the LinkEventCode field */ 3992 3993 3994 /* 3995 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 3996 *one and check the value returned for NumLinkEvents at runtime. 3997 */ 3998 #ifndef MPI26_PCIELINK2_LINK_EVENT_MAX 3999 #define MPI26_PCIELINK2_LINK_EVENT_MAX (1) 4000 #endif 4001 4002 typedef struct _MPI26_CONFIG_PAGE_PCIELINK_2 { 4003 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */ 4004 U8 Link; /*0x08 */ 4005 U8 Reserved1; /*0x09 */ 4006 U16 Reserved2; /*0x0A */ 4007 U8 NumLinkEvents; /*0x0C */ 4008 U8 Reserved3; /*0x0D */ 4009 U16 Reserved4; /*0x0E */ 4010 MPI26_PCIELINK2_LINK_EVENT 4011 LinkEvent[MPI26_PCIELINK2_LINK_EVENT_MAX]; /*0x10 */ 4012 } MPI26_CONFIG_PAGE_PCIELINK_2, *PTR_MPI26_CONFIG_PAGE_PCIELINK_2, 4013 Mpi26PcieLinkPage2_t, *pMpi26PcieLinkPage2_t; 4014 4015 #define MPI26_PCIELINK2_PAGEVERSION (0x00) 4016 4017 /*PCIe Link Page 3 */ 4018 4019 typedef struct _MPI26_PCIELINK3_LINK_EVENT_CONFIG { 4020 U8 LinkEventCode; /*0x00 */ 4021 U8 Reserved1; /*0x01 */ 4022 U16 Reserved2; /*0x02 */ 4023 U8 CounterType; /*0x04 */ 4024 U8 ThresholdWindow; /*0x05 */ 4025 U8 TimeUnits; /*0x06 */ 4026 U8 Reserved3; /*0x07 */ 4027 U32 EventThreshold; /*0x08 */ 4028 U16 ThresholdFlags; /*0x0C */ 4029 U16 Reserved4; /*0x0E */ 4030 } MPI26_PCIELINK3_LINK_EVENT_CONFIG, *PTR_MPI26_PCIELINK3_LINK_EVENT_CONFIG, 4031 Mpi26PcieLink3LinkEventConfig_t, *pMpi26PcieLink3LinkEventConfig_t; 4032 4033 /*values for LinkEventCode field */ 4034 #define MPI26_PCIELINK3_EVTCODE_NO_EVENT (0x00) 4035 #define MPI26_PCIELINK3_EVTCODE_CORRECTABLE_ERROR_RECEIVED (0x01) 4036 #define MPI26_PCIELINK3_EVTCODE_NON_FATAL_ERROR_RECEIVED (0x02) 4037 #define MPI26_PCIELINK3_EVTCODE_FATAL_ERROR_RECEIVED (0x03) 4038 #define MPI26_PCIELINK3_EVTCODE_DATA_LINK_ERROR_DETECTED (0x04) 4039 #define MPI26_PCIELINK3_EVTCODE_TRANSACTION_LAYER_ERROR_DETECTED (0x05) 4040 #define MPI26_PCIELINK3_EVTCODE_TLP_ECRC_ERROR_DETECTED (0x06) 4041 #define MPI26_PCIELINK3_EVTCODE_POISONED_TLP (0x07) 4042 #define MPI26_PCIELINK3_EVTCODE_RECEIVED_NAK_DLLP (0x08) 4043 #define MPI26_PCIELINK3_EVTCODE_SENT_NAK_DLLP (0x09) 4044 #define MPI26_PCIELINK3_EVTCODE_LTSSM_RECOVERY_STATE (0x0A) 4045 #define MPI26_PCIELINK3_EVTCODE_LTSSM_RXL0S_STATE (0x0B) 4046 #define MPI26_PCIELINK3_EVTCODE_LTSSM_TXL0S_STATE (0x0C) 4047 #define MPI26_PCIELINK3_EVTCODE_LTSSM_L1_STATE (0x0D) 4048 #define MPI26_PCIELINK3_EVTCODE_LTSSM_DISABLED_STATE (0x0E) 4049 #define MPI26_PCIELINK3_EVTCODE_LTSSM_HOT_RESET_STATE (0x0F) 4050 #define MPI26_PCIELINK3_EVTCODE_SYSTEM_ERROR (0x10) 4051 #define MPI26_PCIELINK3_EVTCODE_DECODE_ERROR (0x11) 4052 #define MPI26_PCIELINK3_EVTCODE_DISPARITY_ERROR (0x12) 4053 4054 /*values for the CounterType field */ 4055 #define MPI26_PCIELINK3_COUNTER_TYPE_WRAPPING (0x00) 4056 #define MPI26_PCIELINK3_COUNTER_TYPE_SATURATING (0x01) 4057 #define MPI26_PCIELINK3_COUNTER_TYPE_PEAK_VALUE (0x02) 4058 4059 /*values for the TimeUnits field */ 4060 #define MPI26_PCIELINK3_TM_UNITS_10_MICROSECONDS (0x00) 4061 #define MPI26_PCIELINK3_TM_UNITS_100_MICROSECONDS (0x01) 4062 #define MPI26_PCIELINK3_TM_UNITS_1_MILLISECOND (0x02) 4063 #define MPI26_PCIELINK3_TM_UNITS_10_MILLISECONDS (0x03) 4064 4065 /*values for the ThresholdFlags field */ 4066 #define MPI26_PCIELINK3_TFLAGS_EVENT_NOTIFY (0x0001) 4067 4068 /* 4069 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 4070 *one and check the value returned for NumLinkEvents at runtime. 4071 */ 4072 #ifndef MPI26_PCIELINK3_LINK_EVENT_MAX 4073 #define MPI26_PCIELINK3_LINK_EVENT_MAX (1) 4074 #endif 4075 4076 typedef struct _MPI26_CONFIG_PAGE_PCIELINK_3 { 4077 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */ 4078 U8 Link; /*0x08 */ 4079 U8 Reserved1; /*0x09 */ 4080 U16 Reserved2; /*0x0A */ 4081 U8 NumLinkEvents; /*0x0C */ 4082 U8 Reserved3; /*0x0D */ 4083 U16 Reserved4; /*0x0E */ 4084 MPI26_PCIELINK3_LINK_EVENT_CONFIG 4085 LinkEventConfig[MPI26_PCIELINK3_LINK_EVENT_MAX]; /*0x10 */ 4086 } MPI26_CONFIG_PAGE_PCIELINK_3, *PTR_MPI26_CONFIG_PAGE_PCIELINK_3, 4087 Mpi26PcieLinkPage3_t, *pMpi26PcieLinkPage3_t; 4088 4089 #define MPI26_PCIELINK3_PAGEVERSION (0x00) 4090 4091 4092 #endif 4093
