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Searched refs:WREG32_SOC15_RLC (Results 1 – 4 of 4) sorted by relevance

/Linux-v5.10/drivers/gpu/drm/amd/amdgpu/
Dgfxhub_v1_0.c74 WREG32_SOC15_RLC(GC, 0, mmMC_VM_AGP_BASE, 0); in gfxhub_v1_0_init_system_aperture_regs()
75 WREG32_SOC15_RLC(GC, 0, mmMC_VM_AGP_BOT, adev->gmc.agp_start >> 24); in gfxhub_v1_0_init_system_aperture_regs()
76 WREG32_SOC15_RLC(GC, 0, mmMC_VM_AGP_TOP, adev->gmc.agp_end >> 24); in gfxhub_v1_0_init_system_aperture_regs()
80 WREG32_SOC15_RLC(GC, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR, in gfxhub_v1_0_init_system_aperture_regs()
91 WREG32_SOC15_RLC(GC, 0, in gfxhub_v1_0_init_system_aperture_regs()
96 WREG32_SOC15_RLC( in gfxhub_v1_0_init_system_aperture_regs()
137 WREG32_SOC15_RLC(GC, 0, mmMC_VM_MX_L1_TLB_CNTL, tmp); in gfxhub_v1_0_init_tlb_regs()
154 WREG32_SOC15_RLC(GC, 0, mmVM_L2_CNTL, tmp); in gfxhub_v1_0_init_cache_regs()
159 WREG32_SOC15_RLC(GC, 0, mmVM_L2_CNTL2, tmp); in gfxhub_v1_0_init_cache_regs()
171 WREG32_SOC15_RLC(GC, 0, mmVM_L2_CNTL3, tmp); in gfxhub_v1_0_init_cache_regs()
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Dgfx_v9_0.c1998 WREG32_SOC15_RLC(GC, 0, mmSQ_IND_INDEX, in wave_read_ind()
2010 WREG32_SOC15_RLC(GC, 0, mmSQ_IND_INDEX, in wave_read_regs()
2496 WREG32_SOC15_RLC(GC, 0, mmSH_MEM_CONFIG, sh_mem_config); in gfx_v9_0_init_compute_vmid()
2497 WREG32_SOC15_RLC(GC, 0, mmSH_MEM_BASES, sh_mem_bases); in gfx_v9_0_init_compute_vmid()
2570 WREG32_SOC15_RLC(GC, 0, mmSH_MEM_CONFIG, tmp); in gfx_v9_0_constants_init()
2571 WREG32_SOC15_RLC(GC, 0, mmSH_MEM_BASES, 0); in gfx_v9_0_constants_init()
2577 WREG32_SOC15_RLC(GC, 0, mmSH_MEM_CONFIG, tmp); in gfx_v9_0_constants_init()
2582 WREG32_SOC15_RLC(GC, 0, mmSH_MEM_BASES, tmp); in gfx_v9_0_constants_init()
3119 WREG32_SOC15_RLC(GC, 0, mmCP_ME_CNTL, tmp); in gfx_v9_0_cp_gfx_enable()
3315 WREG32_SOC15_RLC(GC, 0, mmCP_MEC_CNTL, 0); in gfx_v9_0_cp_compute_enable()
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Dsoc15_common.h121 #define WREG32_SOC15_RLC(ip, inst, reg, value) \ macro
Dgfx_v10_0.c4854 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_HI, in gfx_v10_0_init_csb()
4856 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_LO, in gfx_v10_0_init_csb()
4858 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size); in gfx_v10_0_init_csb()
5475 WREG32_SOC15_RLC(GC, 0, mmCP_ME_CNTL, tmp); in gfx_v10_0_cp_gfx_enable()