1 // SPDX-License-Identifier: GPL-2.0-only
2 /* CAN bus driver for Microchip 251x/25625 CAN Controller with SPI Interface
3 *
4 * MCP2510 support and bug fixes by Christian Pellegrin
5 * <chripell@evolware.org>
6 *
7 * Copyright 2009 Christian Pellegrin EVOL S.r.l.
8 *
9 * Copyright 2007 Raymarine UK, Ltd. All Rights Reserved.
10 * Written under contract by:
11 * Chris Elston, Katalix Systems, Ltd.
12 *
13 * Based on Microchip MCP251x CAN controller driver written by
14 * David Vrabel, Copyright 2006 Arcom Control Systems Ltd.
15 *
16 * Based on CAN bus driver for the CCAN controller written by
17 * - Sascha Hauer, Marc Kleine-Budde, Pengutronix
18 * - Simon Kallweit, intefo AG
19 * Copyright 2007
20 */
21
22 #include <linux/bitfield.h>
23 #include <linux/can/core.h>
24 #include <linux/can/dev.h>
25 #include <linux/can/led.h>
26 #include <linux/clk.h>
27 #include <linux/completion.h>
28 #include <linux/delay.h>
29 #include <linux/device.h>
30 #include <linux/freezer.h>
31 #include <linux/gpio.h>
32 #include <linux/gpio/driver.h>
33 #include <linux/interrupt.h>
34 #include <linux/io.h>
35 #include <linux/iopoll.h>
36 #include <linux/kernel.h>
37 #include <linux/module.h>
38 #include <linux/netdevice.h>
39 #include <linux/platform_device.h>
40 #include <linux/property.h>
41 #include <linux/regulator/consumer.h>
42 #include <linux/slab.h>
43 #include <linux/spi/spi.h>
44 #include <linux/uaccess.h>
45
46 /* SPI interface instruction set */
47 #define INSTRUCTION_WRITE 0x02
48 #define INSTRUCTION_READ 0x03
49 #define INSTRUCTION_BIT_MODIFY 0x05
50 #define INSTRUCTION_LOAD_TXB(n) (0x40 + 2 * (n))
51 #define INSTRUCTION_READ_RXB(n) (((n) == 0) ? 0x90 : 0x94)
52 #define INSTRUCTION_RESET 0xC0
53 #define RTS_TXB0 0x01
54 #define RTS_TXB1 0x02
55 #define RTS_TXB2 0x04
56 #define INSTRUCTION_RTS(n) (0x80 | ((n) & 0x07))
57
58 /* MPC251x registers */
59 #define BFPCTRL 0x0c
60 # define BFPCTRL_B0BFM BIT(0)
61 # define BFPCTRL_B1BFM BIT(1)
62 # define BFPCTRL_BFM(n) (BFPCTRL_B0BFM << (n))
63 # define BFPCTRL_BFM_MASK GENMASK(1, 0)
64 # define BFPCTRL_B0BFE BIT(2)
65 # define BFPCTRL_B1BFE BIT(3)
66 # define BFPCTRL_BFE(n) (BFPCTRL_B0BFE << (n))
67 # define BFPCTRL_BFE_MASK GENMASK(3, 2)
68 # define BFPCTRL_B0BFS BIT(4)
69 # define BFPCTRL_B1BFS BIT(5)
70 # define BFPCTRL_BFS(n) (BFPCTRL_B0BFS << (n))
71 # define BFPCTRL_BFS_MASK GENMASK(5, 4)
72 #define TXRTSCTRL 0x0d
73 # define TXRTSCTRL_B0RTSM BIT(0)
74 # define TXRTSCTRL_B1RTSM BIT(1)
75 # define TXRTSCTRL_B2RTSM BIT(2)
76 # define TXRTSCTRL_RTSM(n) (TXRTSCTRL_B0RTSM << (n))
77 # define TXRTSCTRL_RTSM_MASK GENMASK(2, 0)
78 # define TXRTSCTRL_B0RTS BIT(3)
79 # define TXRTSCTRL_B1RTS BIT(4)
80 # define TXRTSCTRL_B2RTS BIT(5)
81 # define TXRTSCTRL_RTS(n) (TXRTSCTRL_B0RTS << (n))
82 # define TXRTSCTRL_RTS_MASK GENMASK(5, 3)
83 #define CANSTAT 0x0e
84 #define CANCTRL 0x0f
85 # define CANCTRL_REQOP_MASK 0xe0
86 # define CANCTRL_REQOP_CONF 0x80
87 # define CANCTRL_REQOP_LISTEN_ONLY 0x60
88 # define CANCTRL_REQOP_LOOPBACK 0x40
89 # define CANCTRL_REQOP_SLEEP 0x20
90 # define CANCTRL_REQOP_NORMAL 0x00
91 # define CANCTRL_OSM 0x08
92 # define CANCTRL_ABAT 0x10
93 #define TEC 0x1c
94 #define REC 0x1d
95 #define CNF1 0x2a
96 # define CNF1_SJW_SHIFT 6
97 #define CNF2 0x29
98 # define CNF2_BTLMODE 0x80
99 # define CNF2_SAM 0x40
100 # define CNF2_PS1_SHIFT 3
101 #define CNF3 0x28
102 # define CNF3_SOF 0x08
103 # define CNF3_WAKFIL 0x04
104 # define CNF3_PHSEG2_MASK 0x07
105 #define CANINTE 0x2b
106 # define CANINTE_MERRE 0x80
107 # define CANINTE_WAKIE 0x40
108 # define CANINTE_ERRIE 0x20
109 # define CANINTE_TX2IE 0x10
110 # define CANINTE_TX1IE 0x08
111 # define CANINTE_TX0IE 0x04
112 # define CANINTE_RX1IE 0x02
113 # define CANINTE_RX0IE 0x01
114 #define CANINTF 0x2c
115 # define CANINTF_MERRF 0x80
116 # define CANINTF_WAKIF 0x40
117 # define CANINTF_ERRIF 0x20
118 # define CANINTF_TX2IF 0x10
119 # define CANINTF_TX1IF 0x08
120 # define CANINTF_TX0IF 0x04
121 # define CANINTF_RX1IF 0x02
122 # define CANINTF_RX0IF 0x01
123 # define CANINTF_RX (CANINTF_RX0IF | CANINTF_RX1IF)
124 # define CANINTF_TX (CANINTF_TX2IF | CANINTF_TX1IF | CANINTF_TX0IF)
125 # define CANINTF_ERR (CANINTF_ERRIF)
126 #define EFLG 0x2d
127 # define EFLG_EWARN 0x01
128 # define EFLG_RXWAR 0x02
129 # define EFLG_TXWAR 0x04
130 # define EFLG_RXEP 0x08
131 # define EFLG_TXEP 0x10
132 # define EFLG_TXBO 0x20
133 # define EFLG_RX0OVR 0x40
134 # define EFLG_RX1OVR 0x80
135 #define TXBCTRL(n) (((n) * 0x10) + 0x30 + TXBCTRL_OFF)
136 # define TXBCTRL_ABTF 0x40
137 # define TXBCTRL_MLOA 0x20
138 # define TXBCTRL_TXERR 0x10
139 # define TXBCTRL_TXREQ 0x08
140 #define TXBSIDH(n) (((n) * 0x10) + 0x30 + TXBSIDH_OFF)
141 # define SIDH_SHIFT 3
142 #define TXBSIDL(n) (((n) * 0x10) + 0x30 + TXBSIDL_OFF)
143 # define SIDL_SID_MASK 7
144 # define SIDL_SID_SHIFT 5
145 # define SIDL_EXIDE_SHIFT 3
146 # define SIDL_EID_SHIFT 16
147 # define SIDL_EID_MASK 3
148 #define TXBEID8(n) (((n) * 0x10) + 0x30 + TXBEID8_OFF)
149 #define TXBEID0(n) (((n) * 0x10) + 0x30 + TXBEID0_OFF)
150 #define TXBDLC(n) (((n) * 0x10) + 0x30 + TXBDLC_OFF)
151 # define DLC_RTR_SHIFT 6
152 #define TXBCTRL_OFF 0
153 #define TXBSIDH_OFF 1
154 #define TXBSIDL_OFF 2
155 #define TXBEID8_OFF 3
156 #define TXBEID0_OFF 4
157 #define TXBDLC_OFF 5
158 #define TXBDAT_OFF 6
159 #define RXBCTRL(n) (((n) * 0x10) + 0x60 + RXBCTRL_OFF)
160 # define RXBCTRL_BUKT 0x04
161 # define RXBCTRL_RXM0 0x20
162 # define RXBCTRL_RXM1 0x40
163 #define RXBSIDH(n) (((n) * 0x10) + 0x60 + RXBSIDH_OFF)
164 # define RXBSIDH_SHIFT 3
165 #define RXBSIDL(n) (((n) * 0x10) + 0x60 + RXBSIDL_OFF)
166 # define RXBSIDL_IDE 0x08
167 # define RXBSIDL_SRR 0x10
168 # define RXBSIDL_EID 3
169 # define RXBSIDL_SHIFT 5
170 #define RXBEID8(n) (((n) * 0x10) + 0x60 + RXBEID8_OFF)
171 #define RXBEID0(n) (((n) * 0x10) + 0x60 + RXBEID0_OFF)
172 #define RXBDLC(n) (((n) * 0x10) + 0x60 + RXBDLC_OFF)
173 # define RXBDLC_LEN_MASK 0x0f
174 # define RXBDLC_RTR 0x40
175 #define RXBCTRL_OFF 0
176 #define RXBSIDH_OFF 1
177 #define RXBSIDL_OFF 2
178 #define RXBEID8_OFF 3
179 #define RXBEID0_OFF 4
180 #define RXBDLC_OFF 5
181 #define RXBDAT_OFF 6
182 #define RXFSID(n) ((n < 3) ? 0 : 4)
183 #define RXFSIDH(n) ((n) * 4 + RXFSID(n))
184 #define RXFSIDL(n) ((n) * 4 + 1 + RXFSID(n))
185 #define RXFEID8(n) ((n) * 4 + 2 + RXFSID(n))
186 #define RXFEID0(n) ((n) * 4 + 3 + RXFSID(n))
187 #define RXMSIDH(n) ((n) * 4 + 0x20)
188 #define RXMSIDL(n) ((n) * 4 + 0x21)
189 #define RXMEID8(n) ((n) * 4 + 0x22)
190 #define RXMEID0(n) ((n) * 4 + 0x23)
191
192 #define GET_BYTE(val, byte) \
193 (((val) >> ((byte) * 8)) & 0xff)
194 #define SET_BYTE(val, byte) \
195 (((val) & 0xff) << ((byte) * 8))
196
197 /* Buffer size required for the largest SPI transfer (i.e., reading a
198 * frame)
199 */
200 #define CAN_FRAME_MAX_DATA_LEN 8
201 #define SPI_TRANSFER_BUF_LEN (6 + CAN_FRAME_MAX_DATA_LEN)
202 #define CAN_FRAME_MAX_BITS 128
203
204 #define TX_ECHO_SKB_MAX 1
205
206 #define MCP251X_OST_DELAY_MS (5)
207
208 #define DEVICE_NAME "mcp251x"
209
210 static const struct can_bittiming_const mcp251x_bittiming_const = {
211 .name = DEVICE_NAME,
212 .tseg1_min = 3,
213 .tseg1_max = 16,
214 .tseg2_min = 2,
215 .tseg2_max = 8,
216 .sjw_max = 4,
217 .brp_min = 1,
218 .brp_max = 64,
219 .brp_inc = 1,
220 };
221
222 enum mcp251x_model {
223 CAN_MCP251X_MCP2510 = 0x2510,
224 CAN_MCP251X_MCP2515 = 0x2515,
225 CAN_MCP251X_MCP25625 = 0x25625,
226 };
227
228 struct mcp251x_priv {
229 struct can_priv can;
230 struct net_device *net;
231 struct spi_device *spi;
232 enum mcp251x_model model;
233
234 struct mutex mcp_lock; /* SPI device lock */
235
236 u8 *spi_tx_buf;
237 u8 *spi_rx_buf;
238
239 struct sk_buff *tx_skb;
240 int tx_len;
241
242 struct workqueue_struct *wq;
243 struct work_struct tx_work;
244 struct work_struct restart_work;
245
246 int force_quit;
247 int after_suspend;
248 #define AFTER_SUSPEND_UP 1
249 #define AFTER_SUSPEND_DOWN 2
250 #define AFTER_SUSPEND_POWER 4
251 #define AFTER_SUSPEND_RESTART 8
252 int restart_tx;
253 struct regulator *power;
254 struct regulator *transceiver;
255 struct clk *clk;
256 #ifdef CONFIG_GPIOLIB
257 struct gpio_chip gpio;
258 u8 reg_bfpctrl;
259 #endif
260 };
261
262 #define MCP251X_IS(_model) \
263 static inline int mcp251x_is_##_model(struct spi_device *spi) \
264 { \
265 struct mcp251x_priv *priv = spi_get_drvdata(spi); \
266 return priv->model == CAN_MCP251X_MCP##_model; \
267 }
268
269 MCP251X_IS(2510);
270
mcp251x_clean(struct net_device * net)271 static void mcp251x_clean(struct net_device *net)
272 {
273 struct mcp251x_priv *priv = netdev_priv(net);
274
275 if (priv->tx_skb || priv->tx_len)
276 net->stats.tx_errors++;
277 dev_kfree_skb(priv->tx_skb);
278 if (priv->tx_len)
279 can_free_echo_skb(priv->net, 0);
280 priv->tx_skb = NULL;
281 priv->tx_len = 0;
282 }
283
284 /* Note about handling of error return of mcp251x_spi_trans: accessing
285 * registers via SPI is not really different conceptually than using
286 * normal I/O assembler instructions, although it's much more
287 * complicated from a practical POV. So it's not advisable to always
288 * check the return value of this function. Imagine that every
289 * read{b,l}, write{b,l} and friends would be bracketed in "if ( < 0)
290 * error();", it would be a great mess (well there are some situation
291 * when exception handling C++ like could be useful after all). So we
292 * just check that transfers are OK at the beginning of our
293 * conversation with the chip and to avoid doing really nasty things
294 * (like injecting bogus packets in the network stack).
295 */
mcp251x_spi_trans(struct spi_device * spi,int len)296 static int mcp251x_spi_trans(struct spi_device *spi, int len)
297 {
298 struct mcp251x_priv *priv = spi_get_drvdata(spi);
299 struct spi_transfer t = {
300 .tx_buf = priv->spi_tx_buf,
301 .rx_buf = priv->spi_rx_buf,
302 .len = len,
303 .cs_change = 0,
304 };
305 struct spi_message m;
306 int ret;
307
308 spi_message_init(&m);
309 spi_message_add_tail(&t, &m);
310
311 ret = spi_sync(spi, &m);
312 if (ret)
313 dev_err(&spi->dev, "spi transfer failed: ret = %d\n", ret);
314 return ret;
315 }
316
mcp251x_read_reg(struct spi_device * spi,u8 reg)317 static u8 mcp251x_read_reg(struct spi_device *spi, u8 reg)
318 {
319 struct mcp251x_priv *priv = spi_get_drvdata(spi);
320 u8 val = 0;
321
322 priv->spi_tx_buf[0] = INSTRUCTION_READ;
323 priv->spi_tx_buf[1] = reg;
324
325 if (spi->controller->flags & SPI_CONTROLLER_HALF_DUPLEX) {
326 spi_write_then_read(spi, priv->spi_tx_buf, 2, &val, 1);
327 } else {
328 mcp251x_spi_trans(spi, 3);
329 val = priv->spi_rx_buf[2];
330 }
331
332 return val;
333 }
334
mcp251x_read_2regs(struct spi_device * spi,u8 reg,u8 * v1,u8 * v2)335 static void mcp251x_read_2regs(struct spi_device *spi, u8 reg, u8 *v1, u8 *v2)
336 {
337 struct mcp251x_priv *priv = spi_get_drvdata(spi);
338
339 priv->spi_tx_buf[0] = INSTRUCTION_READ;
340 priv->spi_tx_buf[1] = reg;
341
342 if (spi->controller->flags & SPI_CONTROLLER_HALF_DUPLEX) {
343 u8 val[2] = { 0 };
344
345 spi_write_then_read(spi, priv->spi_tx_buf, 2, val, 2);
346 *v1 = val[0];
347 *v2 = val[1];
348 } else {
349 mcp251x_spi_trans(spi, 4);
350
351 *v1 = priv->spi_rx_buf[2];
352 *v2 = priv->spi_rx_buf[3];
353 }
354 }
355
mcp251x_write_reg(struct spi_device * spi,u8 reg,u8 val)356 static void mcp251x_write_reg(struct spi_device *spi, u8 reg, u8 val)
357 {
358 struct mcp251x_priv *priv = spi_get_drvdata(spi);
359
360 priv->spi_tx_buf[0] = INSTRUCTION_WRITE;
361 priv->spi_tx_buf[1] = reg;
362 priv->spi_tx_buf[2] = val;
363
364 mcp251x_spi_trans(spi, 3);
365 }
366
mcp251x_write_2regs(struct spi_device * spi,u8 reg,u8 v1,u8 v2)367 static void mcp251x_write_2regs(struct spi_device *spi, u8 reg, u8 v1, u8 v2)
368 {
369 struct mcp251x_priv *priv = spi_get_drvdata(spi);
370
371 priv->spi_tx_buf[0] = INSTRUCTION_WRITE;
372 priv->spi_tx_buf[1] = reg;
373 priv->spi_tx_buf[2] = v1;
374 priv->spi_tx_buf[3] = v2;
375
376 mcp251x_spi_trans(spi, 4);
377 }
378
mcp251x_write_bits(struct spi_device * spi,u8 reg,u8 mask,u8 val)379 static void mcp251x_write_bits(struct spi_device *spi, u8 reg,
380 u8 mask, u8 val)
381 {
382 struct mcp251x_priv *priv = spi_get_drvdata(spi);
383
384 priv->spi_tx_buf[0] = INSTRUCTION_BIT_MODIFY;
385 priv->spi_tx_buf[1] = reg;
386 priv->spi_tx_buf[2] = mask;
387 priv->spi_tx_buf[3] = val;
388
389 mcp251x_spi_trans(spi, 4);
390 }
391
mcp251x_read_stat(struct spi_device * spi)392 static u8 mcp251x_read_stat(struct spi_device *spi)
393 {
394 return mcp251x_read_reg(spi, CANSTAT) & CANCTRL_REQOP_MASK;
395 }
396
397 #define mcp251x_read_stat_poll_timeout(addr, val, cond, delay_us, timeout_us) \
398 readx_poll_timeout(mcp251x_read_stat, addr, val, cond, \
399 delay_us, timeout_us)
400
401 #ifdef CONFIG_GPIOLIB
402 enum {
403 MCP251X_GPIO_TX0RTS = 0, /* inputs */
404 MCP251X_GPIO_TX1RTS,
405 MCP251X_GPIO_TX2RTS,
406 MCP251X_GPIO_RX0BF, /* outputs */
407 MCP251X_GPIO_RX1BF,
408 };
409
410 #define MCP251X_GPIO_INPUT_MASK \
411 GENMASK(MCP251X_GPIO_TX2RTS, MCP251X_GPIO_TX0RTS)
412 #define MCP251X_GPIO_OUTPUT_MASK \
413 GENMASK(MCP251X_GPIO_RX1BF, MCP251X_GPIO_RX0BF)
414
415 static const char * const mcp251x_gpio_names[] = {
416 [MCP251X_GPIO_TX0RTS] = "TX0RTS", /* inputs */
417 [MCP251X_GPIO_TX1RTS] = "TX1RTS",
418 [MCP251X_GPIO_TX2RTS] = "TX2RTS",
419 [MCP251X_GPIO_RX0BF] = "RX0BF", /* outputs */
420 [MCP251X_GPIO_RX1BF] = "RX1BF",
421 };
422
mcp251x_gpio_is_input(unsigned int offset)423 static inline bool mcp251x_gpio_is_input(unsigned int offset)
424 {
425 return offset <= MCP251X_GPIO_TX2RTS;
426 }
427
mcp251x_gpio_request(struct gpio_chip * chip,unsigned int offset)428 static int mcp251x_gpio_request(struct gpio_chip *chip,
429 unsigned int offset)
430 {
431 struct mcp251x_priv *priv = gpiochip_get_data(chip);
432 u8 val;
433
434 /* nothing to be done for inputs */
435 if (mcp251x_gpio_is_input(offset))
436 return 0;
437
438 val = BFPCTRL_BFE(offset - MCP251X_GPIO_RX0BF);
439
440 mutex_lock(&priv->mcp_lock);
441 mcp251x_write_bits(priv->spi, BFPCTRL, val, val);
442 mutex_unlock(&priv->mcp_lock);
443
444 priv->reg_bfpctrl |= val;
445
446 return 0;
447 }
448
mcp251x_gpio_free(struct gpio_chip * chip,unsigned int offset)449 static void mcp251x_gpio_free(struct gpio_chip *chip,
450 unsigned int offset)
451 {
452 struct mcp251x_priv *priv = gpiochip_get_data(chip);
453 u8 val;
454
455 /* nothing to be done for inputs */
456 if (mcp251x_gpio_is_input(offset))
457 return;
458
459 val = BFPCTRL_BFE(offset - MCP251X_GPIO_RX0BF);
460
461 mutex_lock(&priv->mcp_lock);
462 mcp251x_write_bits(priv->spi, BFPCTRL, val, 0);
463 mutex_unlock(&priv->mcp_lock);
464
465 priv->reg_bfpctrl &= ~val;
466 }
467
mcp251x_gpio_get_direction(struct gpio_chip * chip,unsigned int offset)468 static int mcp251x_gpio_get_direction(struct gpio_chip *chip,
469 unsigned int offset)
470 {
471 if (mcp251x_gpio_is_input(offset))
472 return GPIOF_DIR_IN;
473
474 return GPIOF_DIR_OUT;
475 }
476
mcp251x_gpio_get(struct gpio_chip * chip,unsigned int offset)477 static int mcp251x_gpio_get(struct gpio_chip *chip, unsigned int offset)
478 {
479 struct mcp251x_priv *priv = gpiochip_get_data(chip);
480 u8 reg, mask, val;
481
482 if (mcp251x_gpio_is_input(offset)) {
483 reg = TXRTSCTRL;
484 mask = TXRTSCTRL_RTS(offset);
485 } else {
486 reg = BFPCTRL;
487 mask = BFPCTRL_BFS(offset - MCP251X_GPIO_RX0BF);
488 }
489
490 mutex_lock(&priv->mcp_lock);
491 val = mcp251x_read_reg(priv->spi, reg);
492 mutex_unlock(&priv->mcp_lock);
493
494 return !!(val & mask);
495 }
496
mcp251x_gpio_get_multiple(struct gpio_chip * chip,unsigned long * maskp,unsigned long * bitsp)497 static int mcp251x_gpio_get_multiple(struct gpio_chip *chip,
498 unsigned long *maskp, unsigned long *bitsp)
499 {
500 struct mcp251x_priv *priv = gpiochip_get_data(chip);
501 unsigned long bits = 0;
502 u8 val;
503
504 mutex_lock(&priv->mcp_lock);
505 if (maskp[0] & MCP251X_GPIO_INPUT_MASK) {
506 val = mcp251x_read_reg(priv->spi, TXRTSCTRL);
507 val = FIELD_GET(TXRTSCTRL_RTS_MASK, val);
508 bits |= FIELD_PREP(MCP251X_GPIO_INPUT_MASK, val);
509 }
510 if (maskp[0] & MCP251X_GPIO_OUTPUT_MASK) {
511 val = mcp251x_read_reg(priv->spi, BFPCTRL);
512 val = FIELD_GET(BFPCTRL_BFS_MASK, val);
513 bits |= FIELD_PREP(MCP251X_GPIO_OUTPUT_MASK, val);
514 }
515 mutex_unlock(&priv->mcp_lock);
516
517 bitsp[0] = bits;
518 return 0;
519 }
520
mcp251x_gpio_set(struct gpio_chip * chip,unsigned int offset,int value)521 static void mcp251x_gpio_set(struct gpio_chip *chip, unsigned int offset,
522 int value)
523 {
524 struct mcp251x_priv *priv = gpiochip_get_data(chip);
525 u8 mask, val;
526
527 mask = BFPCTRL_BFS(offset - MCP251X_GPIO_RX0BF);
528 val = value ? mask : 0;
529
530 mutex_lock(&priv->mcp_lock);
531 mcp251x_write_bits(priv->spi, BFPCTRL, mask, val);
532 mutex_unlock(&priv->mcp_lock);
533
534 priv->reg_bfpctrl &= ~mask;
535 priv->reg_bfpctrl |= val;
536 }
537
538 static void
mcp251x_gpio_set_multiple(struct gpio_chip * chip,unsigned long * maskp,unsigned long * bitsp)539 mcp251x_gpio_set_multiple(struct gpio_chip *chip,
540 unsigned long *maskp, unsigned long *bitsp)
541 {
542 struct mcp251x_priv *priv = gpiochip_get_data(chip);
543 u8 mask, val;
544
545 mask = FIELD_GET(MCP251X_GPIO_OUTPUT_MASK, maskp[0]);
546 mask = FIELD_PREP(BFPCTRL_BFS_MASK, mask);
547
548 val = FIELD_GET(MCP251X_GPIO_OUTPUT_MASK, bitsp[0]);
549 val = FIELD_PREP(BFPCTRL_BFS_MASK, val);
550
551 if (!mask)
552 return;
553
554 mutex_lock(&priv->mcp_lock);
555 mcp251x_write_bits(priv->spi, BFPCTRL, mask, val);
556 mutex_unlock(&priv->mcp_lock);
557
558 priv->reg_bfpctrl &= ~mask;
559 priv->reg_bfpctrl |= val;
560 }
561
mcp251x_gpio_restore(struct spi_device * spi)562 static void mcp251x_gpio_restore(struct spi_device *spi)
563 {
564 struct mcp251x_priv *priv = spi_get_drvdata(spi);
565
566 mcp251x_write_reg(spi, BFPCTRL, priv->reg_bfpctrl);
567 }
568
mcp251x_gpio_setup(struct mcp251x_priv * priv)569 static int mcp251x_gpio_setup(struct mcp251x_priv *priv)
570 {
571 struct gpio_chip *gpio = &priv->gpio;
572
573 if (!device_property_present(&priv->spi->dev, "gpio-controller"))
574 return 0;
575
576 /* gpiochip handles TX[0..2]RTS and RX[0..1]BF */
577 gpio->label = priv->spi->modalias;
578 gpio->parent = &priv->spi->dev;
579 gpio->owner = THIS_MODULE;
580 gpio->request = mcp251x_gpio_request;
581 gpio->free = mcp251x_gpio_free;
582 gpio->get_direction = mcp251x_gpio_get_direction;
583 gpio->get = mcp251x_gpio_get;
584 gpio->get_multiple = mcp251x_gpio_get_multiple;
585 gpio->set = mcp251x_gpio_set;
586 gpio->set_multiple = mcp251x_gpio_set_multiple;
587 gpio->base = -1;
588 gpio->ngpio = ARRAY_SIZE(mcp251x_gpio_names);
589 gpio->names = mcp251x_gpio_names;
590 gpio->can_sleep = true;
591 #ifdef CONFIG_OF_GPIO
592 gpio->of_node = priv->spi->dev.of_node;
593 #endif
594
595 return devm_gpiochip_add_data(&priv->spi->dev, gpio, priv);
596 }
597 #else
mcp251x_gpio_restore(struct spi_device * spi)598 static inline void mcp251x_gpio_restore(struct spi_device *spi)
599 {
600 }
601
mcp251x_gpio_setup(struct mcp251x_priv * priv)602 static inline int mcp251x_gpio_setup(struct mcp251x_priv *priv)
603 {
604 return 0;
605 }
606 #endif
607
mcp251x_hw_tx_frame(struct spi_device * spi,u8 * buf,int len,int tx_buf_idx)608 static void mcp251x_hw_tx_frame(struct spi_device *spi, u8 *buf,
609 int len, int tx_buf_idx)
610 {
611 struct mcp251x_priv *priv = spi_get_drvdata(spi);
612
613 if (mcp251x_is_2510(spi)) {
614 int i;
615
616 for (i = 1; i < TXBDAT_OFF + len; i++)
617 mcp251x_write_reg(spi, TXBCTRL(tx_buf_idx) + i,
618 buf[i]);
619 } else {
620 memcpy(priv->spi_tx_buf, buf, TXBDAT_OFF + len);
621 mcp251x_spi_trans(spi, TXBDAT_OFF + len);
622 }
623 }
624
mcp251x_hw_tx(struct spi_device * spi,struct can_frame * frame,int tx_buf_idx)625 static void mcp251x_hw_tx(struct spi_device *spi, struct can_frame *frame,
626 int tx_buf_idx)
627 {
628 struct mcp251x_priv *priv = spi_get_drvdata(spi);
629 u32 sid, eid, exide, rtr;
630 u8 buf[SPI_TRANSFER_BUF_LEN];
631
632 exide = (frame->can_id & CAN_EFF_FLAG) ? 1 : 0; /* Extended ID Enable */
633 if (exide)
634 sid = (frame->can_id & CAN_EFF_MASK) >> 18;
635 else
636 sid = frame->can_id & CAN_SFF_MASK; /* Standard ID */
637 eid = frame->can_id & CAN_EFF_MASK; /* Extended ID */
638 rtr = (frame->can_id & CAN_RTR_FLAG) ? 1 : 0; /* Remote transmission */
639
640 buf[TXBCTRL_OFF] = INSTRUCTION_LOAD_TXB(tx_buf_idx);
641 buf[TXBSIDH_OFF] = sid >> SIDH_SHIFT;
642 buf[TXBSIDL_OFF] = ((sid & SIDL_SID_MASK) << SIDL_SID_SHIFT) |
643 (exide << SIDL_EXIDE_SHIFT) |
644 ((eid >> SIDL_EID_SHIFT) & SIDL_EID_MASK);
645 buf[TXBEID8_OFF] = GET_BYTE(eid, 1);
646 buf[TXBEID0_OFF] = GET_BYTE(eid, 0);
647 buf[TXBDLC_OFF] = (rtr << DLC_RTR_SHIFT) | frame->can_dlc;
648 memcpy(buf + TXBDAT_OFF, frame->data, frame->can_dlc);
649 mcp251x_hw_tx_frame(spi, buf, frame->can_dlc, tx_buf_idx);
650
651 /* use INSTRUCTION_RTS, to avoid "repeated frame problem" */
652 priv->spi_tx_buf[0] = INSTRUCTION_RTS(1 << tx_buf_idx);
653 mcp251x_spi_trans(priv->spi, 1);
654 }
655
mcp251x_hw_rx_frame(struct spi_device * spi,u8 * buf,int buf_idx)656 static void mcp251x_hw_rx_frame(struct spi_device *spi, u8 *buf,
657 int buf_idx)
658 {
659 struct mcp251x_priv *priv = spi_get_drvdata(spi);
660
661 if (mcp251x_is_2510(spi)) {
662 int i, len;
663
664 for (i = 1; i < RXBDAT_OFF; i++)
665 buf[i] = mcp251x_read_reg(spi, RXBCTRL(buf_idx) + i);
666
667 len = get_can_dlc(buf[RXBDLC_OFF] & RXBDLC_LEN_MASK);
668 for (; i < (RXBDAT_OFF + len); i++)
669 buf[i] = mcp251x_read_reg(spi, RXBCTRL(buf_idx) + i);
670 } else {
671 priv->spi_tx_buf[RXBCTRL_OFF] = INSTRUCTION_READ_RXB(buf_idx);
672 if (spi->controller->flags & SPI_CONTROLLER_HALF_DUPLEX) {
673 spi_write_then_read(spi, priv->spi_tx_buf, 1,
674 priv->spi_rx_buf,
675 SPI_TRANSFER_BUF_LEN);
676 memcpy(buf + 1, priv->spi_rx_buf,
677 SPI_TRANSFER_BUF_LEN - 1);
678 } else {
679 mcp251x_spi_trans(spi, SPI_TRANSFER_BUF_LEN);
680 memcpy(buf, priv->spi_rx_buf, SPI_TRANSFER_BUF_LEN);
681 }
682 }
683 }
684
mcp251x_hw_rx(struct spi_device * spi,int buf_idx)685 static void mcp251x_hw_rx(struct spi_device *spi, int buf_idx)
686 {
687 struct mcp251x_priv *priv = spi_get_drvdata(spi);
688 struct sk_buff *skb;
689 struct can_frame *frame;
690 u8 buf[SPI_TRANSFER_BUF_LEN];
691
692 skb = alloc_can_skb(priv->net, &frame);
693 if (!skb) {
694 dev_err(&spi->dev, "cannot allocate RX skb\n");
695 priv->net->stats.rx_dropped++;
696 return;
697 }
698
699 mcp251x_hw_rx_frame(spi, buf, buf_idx);
700 if (buf[RXBSIDL_OFF] & RXBSIDL_IDE) {
701 /* Extended ID format */
702 frame->can_id = CAN_EFF_FLAG;
703 frame->can_id |=
704 /* Extended ID part */
705 SET_BYTE(buf[RXBSIDL_OFF] & RXBSIDL_EID, 2) |
706 SET_BYTE(buf[RXBEID8_OFF], 1) |
707 SET_BYTE(buf[RXBEID0_OFF], 0) |
708 /* Standard ID part */
709 (((buf[RXBSIDH_OFF] << RXBSIDH_SHIFT) |
710 (buf[RXBSIDL_OFF] >> RXBSIDL_SHIFT)) << 18);
711 /* Remote transmission request */
712 if (buf[RXBDLC_OFF] & RXBDLC_RTR)
713 frame->can_id |= CAN_RTR_FLAG;
714 } else {
715 /* Standard ID format */
716 frame->can_id =
717 (buf[RXBSIDH_OFF] << RXBSIDH_SHIFT) |
718 (buf[RXBSIDL_OFF] >> RXBSIDL_SHIFT);
719 if (buf[RXBSIDL_OFF] & RXBSIDL_SRR)
720 frame->can_id |= CAN_RTR_FLAG;
721 }
722 /* Data length */
723 frame->can_dlc = get_can_dlc(buf[RXBDLC_OFF] & RXBDLC_LEN_MASK);
724 memcpy(frame->data, buf + RXBDAT_OFF, frame->can_dlc);
725
726 priv->net->stats.rx_packets++;
727 priv->net->stats.rx_bytes += frame->can_dlc;
728
729 can_led_event(priv->net, CAN_LED_EVENT_RX);
730
731 netif_rx_ni(skb);
732 }
733
mcp251x_hw_sleep(struct spi_device * spi)734 static void mcp251x_hw_sleep(struct spi_device *spi)
735 {
736 mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_SLEEP);
737 }
738
739 /* May only be called when device is sleeping! */
mcp251x_hw_wake(struct spi_device * spi)740 static int mcp251x_hw_wake(struct spi_device *spi)
741 {
742 u8 value;
743 int ret;
744
745 /* Force wakeup interrupt to wake device, but don't execute IST */
746 disable_irq(spi->irq);
747 mcp251x_write_2regs(spi, CANINTE, CANINTE_WAKIE, CANINTF_WAKIF);
748
749 /* Wait for oscillator startup timer after wake up */
750 mdelay(MCP251X_OST_DELAY_MS);
751
752 /* Put device into config mode */
753 mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_CONF);
754
755 /* Wait for the device to enter config mode */
756 ret = mcp251x_read_stat_poll_timeout(spi, value, value == CANCTRL_REQOP_CONF,
757 MCP251X_OST_DELAY_MS * 1000,
758 USEC_PER_SEC);
759 if (ret) {
760 dev_err(&spi->dev, "MCP251x didn't enter in config mode\n");
761 return ret;
762 }
763
764 /* Disable and clear pending interrupts */
765 mcp251x_write_2regs(spi, CANINTE, 0x00, 0x00);
766 enable_irq(spi->irq);
767
768 return 0;
769 }
770
mcp251x_hard_start_xmit(struct sk_buff * skb,struct net_device * net)771 static netdev_tx_t mcp251x_hard_start_xmit(struct sk_buff *skb,
772 struct net_device *net)
773 {
774 struct mcp251x_priv *priv = netdev_priv(net);
775 struct spi_device *spi = priv->spi;
776
777 if (priv->tx_skb || priv->tx_len) {
778 dev_warn(&spi->dev, "hard_xmit called while tx busy\n");
779 return NETDEV_TX_BUSY;
780 }
781
782 if (can_dropped_invalid_skb(net, skb))
783 return NETDEV_TX_OK;
784
785 netif_stop_queue(net);
786 priv->tx_skb = skb;
787 queue_work(priv->wq, &priv->tx_work);
788
789 return NETDEV_TX_OK;
790 }
791
mcp251x_do_set_mode(struct net_device * net,enum can_mode mode)792 static int mcp251x_do_set_mode(struct net_device *net, enum can_mode mode)
793 {
794 struct mcp251x_priv *priv = netdev_priv(net);
795
796 switch (mode) {
797 case CAN_MODE_START:
798 mcp251x_clean(net);
799 /* We have to delay work since SPI I/O may sleep */
800 priv->can.state = CAN_STATE_ERROR_ACTIVE;
801 priv->restart_tx = 1;
802 if (priv->can.restart_ms == 0)
803 priv->after_suspend = AFTER_SUSPEND_RESTART;
804 queue_work(priv->wq, &priv->restart_work);
805 break;
806 default:
807 return -EOPNOTSUPP;
808 }
809
810 return 0;
811 }
812
mcp251x_set_normal_mode(struct spi_device * spi)813 static int mcp251x_set_normal_mode(struct spi_device *spi)
814 {
815 struct mcp251x_priv *priv = spi_get_drvdata(spi);
816 u8 value;
817 int ret;
818
819 /* Enable interrupts */
820 mcp251x_write_reg(spi, CANINTE,
821 CANINTE_ERRIE | CANINTE_TX2IE | CANINTE_TX1IE |
822 CANINTE_TX0IE | CANINTE_RX1IE | CANINTE_RX0IE);
823
824 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) {
825 /* Put device into loopback mode */
826 mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_LOOPBACK);
827 } else if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) {
828 /* Put device into listen-only mode */
829 mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_LISTEN_ONLY);
830 } else {
831 /* Put device into normal mode */
832 mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_NORMAL);
833
834 /* Wait for the device to enter normal mode */
835 ret = mcp251x_read_stat_poll_timeout(spi, value, value == 0,
836 MCP251X_OST_DELAY_MS * 1000,
837 USEC_PER_SEC);
838 if (ret) {
839 dev_err(&spi->dev, "MCP251x didn't enter in normal mode\n");
840 return ret;
841 }
842 }
843 priv->can.state = CAN_STATE_ERROR_ACTIVE;
844 return 0;
845 }
846
mcp251x_do_set_bittiming(struct net_device * net)847 static int mcp251x_do_set_bittiming(struct net_device *net)
848 {
849 struct mcp251x_priv *priv = netdev_priv(net);
850 struct can_bittiming *bt = &priv->can.bittiming;
851 struct spi_device *spi = priv->spi;
852
853 mcp251x_write_reg(spi, CNF1, ((bt->sjw - 1) << CNF1_SJW_SHIFT) |
854 (bt->brp - 1));
855 mcp251x_write_reg(spi, CNF2, CNF2_BTLMODE |
856 (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES ?
857 CNF2_SAM : 0) |
858 ((bt->phase_seg1 - 1) << CNF2_PS1_SHIFT) |
859 (bt->prop_seg - 1));
860 mcp251x_write_bits(spi, CNF3, CNF3_PHSEG2_MASK,
861 (bt->phase_seg2 - 1));
862 dev_dbg(&spi->dev, "CNF: 0x%02x 0x%02x 0x%02x\n",
863 mcp251x_read_reg(spi, CNF1),
864 mcp251x_read_reg(spi, CNF2),
865 mcp251x_read_reg(spi, CNF3));
866
867 return 0;
868 }
869
mcp251x_setup(struct net_device * net,struct spi_device * spi)870 static int mcp251x_setup(struct net_device *net, struct spi_device *spi)
871 {
872 mcp251x_do_set_bittiming(net);
873
874 mcp251x_write_reg(spi, RXBCTRL(0),
875 RXBCTRL_BUKT | RXBCTRL_RXM0 | RXBCTRL_RXM1);
876 mcp251x_write_reg(spi, RXBCTRL(1),
877 RXBCTRL_RXM0 | RXBCTRL_RXM1);
878 return 0;
879 }
880
mcp251x_hw_reset(struct spi_device * spi)881 static int mcp251x_hw_reset(struct spi_device *spi)
882 {
883 struct mcp251x_priv *priv = spi_get_drvdata(spi);
884 u8 value;
885 int ret;
886
887 /* Wait for oscillator startup timer after power up */
888 mdelay(MCP251X_OST_DELAY_MS);
889
890 priv->spi_tx_buf[0] = INSTRUCTION_RESET;
891 ret = mcp251x_spi_trans(spi, 1);
892 if (ret)
893 return ret;
894
895 /* Wait for oscillator startup timer after reset */
896 mdelay(MCP251X_OST_DELAY_MS);
897
898 /* Wait for reset to finish */
899 ret = mcp251x_read_stat_poll_timeout(spi, value, value == CANCTRL_REQOP_CONF,
900 MCP251X_OST_DELAY_MS * 1000,
901 USEC_PER_SEC);
902 if (ret)
903 dev_err(&spi->dev, "MCP251x didn't enter in conf mode after reset\n");
904 return ret;
905 }
906
mcp251x_hw_probe(struct spi_device * spi)907 static int mcp251x_hw_probe(struct spi_device *spi)
908 {
909 u8 ctrl;
910 int ret;
911
912 ret = mcp251x_hw_reset(spi);
913 if (ret)
914 return ret;
915
916 ctrl = mcp251x_read_reg(spi, CANCTRL);
917
918 dev_dbg(&spi->dev, "CANCTRL 0x%02x\n", ctrl);
919
920 /* Check for power up default value */
921 if ((ctrl & 0x17) != 0x07)
922 return -ENODEV;
923
924 return 0;
925 }
926
mcp251x_power_enable(struct regulator * reg,int enable)927 static int mcp251x_power_enable(struct regulator *reg, int enable)
928 {
929 if (IS_ERR_OR_NULL(reg))
930 return 0;
931
932 if (enable)
933 return regulator_enable(reg);
934 else
935 return regulator_disable(reg);
936 }
937
mcp251x_stop(struct net_device * net)938 static int mcp251x_stop(struct net_device *net)
939 {
940 struct mcp251x_priv *priv = netdev_priv(net);
941 struct spi_device *spi = priv->spi;
942
943 close_candev(net);
944
945 priv->force_quit = 1;
946 free_irq(spi->irq, priv);
947 destroy_workqueue(priv->wq);
948 priv->wq = NULL;
949
950 mutex_lock(&priv->mcp_lock);
951
952 /* Disable and clear pending interrupts */
953 mcp251x_write_2regs(spi, CANINTE, 0x00, 0x00);
954
955 mcp251x_write_reg(spi, TXBCTRL(0), 0);
956 mcp251x_clean(net);
957
958 mcp251x_hw_sleep(spi);
959
960 mcp251x_power_enable(priv->transceiver, 0);
961
962 priv->can.state = CAN_STATE_STOPPED;
963
964 mutex_unlock(&priv->mcp_lock);
965
966 can_led_event(net, CAN_LED_EVENT_STOP);
967
968 return 0;
969 }
970
mcp251x_error_skb(struct net_device * net,int can_id,int data1)971 static void mcp251x_error_skb(struct net_device *net, int can_id, int data1)
972 {
973 struct sk_buff *skb;
974 struct can_frame *frame;
975
976 skb = alloc_can_err_skb(net, &frame);
977 if (skb) {
978 frame->can_id |= can_id;
979 frame->data[1] = data1;
980 netif_rx_ni(skb);
981 } else {
982 netdev_err(net, "cannot allocate error skb\n");
983 }
984 }
985
mcp251x_tx_work_handler(struct work_struct * ws)986 static void mcp251x_tx_work_handler(struct work_struct *ws)
987 {
988 struct mcp251x_priv *priv = container_of(ws, struct mcp251x_priv,
989 tx_work);
990 struct spi_device *spi = priv->spi;
991 struct net_device *net = priv->net;
992 struct can_frame *frame;
993
994 mutex_lock(&priv->mcp_lock);
995 if (priv->tx_skb) {
996 if (priv->can.state == CAN_STATE_BUS_OFF) {
997 mcp251x_clean(net);
998 } else {
999 frame = (struct can_frame *)priv->tx_skb->data;
1000
1001 if (frame->can_dlc > CAN_FRAME_MAX_DATA_LEN)
1002 frame->can_dlc = CAN_FRAME_MAX_DATA_LEN;
1003 mcp251x_hw_tx(spi, frame, 0);
1004 priv->tx_len = 1 + frame->can_dlc;
1005 can_put_echo_skb(priv->tx_skb, net, 0);
1006 priv->tx_skb = NULL;
1007 }
1008 }
1009 mutex_unlock(&priv->mcp_lock);
1010 }
1011
mcp251x_restart_work_handler(struct work_struct * ws)1012 static void mcp251x_restart_work_handler(struct work_struct *ws)
1013 {
1014 struct mcp251x_priv *priv = container_of(ws, struct mcp251x_priv,
1015 restart_work);
1016 struct spi_device *spi = priv->spi;
1017 struct net_device *net = priv->net;
1018
1019 mutex_lock(&priv->mcp_lock);
1020 if (priv->after_suspend) {
1021 if (priv->after_suspend & AFTER_SUSPEND_POWER) {
1022 mcp251x_hw_reset(spi);
1023 mcp251x_setup(net, spi);
1024 mcp251x_gpio_restore(spi);
1025 } else {
1026 mcp251x_hw_wake(spi);
1027 }
1028 priv->force_quit = 0;
1029 if (priv->after_suspend & AFTER_SUSPEND_RESTART) {
1030 mcp251x_set_normal_mode(spi);
1031 } else if (priv->after_suspend & AFTER_SUSPEND_UP) {
1032 netif_device_attach(net);
1033 mcp251x_clean(net);
1034 mcp251x_set_normal_mode(spi);
1035 netif_wake_queue(net);
1036 } else {
1037 mcp251x_hw_sleep(spi);
1038 }
1039 priv->after_suspend = 0;
1040 }
1041
1042 if (priv->restart_tx) {
1043 priv->restart_tx = 0;
1044 mcp251x_write_reg(spi, TXBCTRL(0), 0);
1045 mcp251x_clean(net);
1046 netif_wake_queue(net);
1047 mcp251x_error_skb(net, CAN_ERR_RESTARTED, 0);
1048 }
1049 mutex_unlock(&priv->mcp_lock);
1050 }
1051
mcp251x_can_ist(int irq,void * dev_id)1052 static irqreturn_t mcp251x_can_ist(int irq, void *dev_id)
1053 {
1054 struct mcp251x_priv *priv = dev_id;
1055 struct spi_device *spi = priv->spi;
1056 struct net_device *net = priv->net;
1057
1058 mutex_lock(&priv->mcp_lock);
1059 while (!priv->force_quit) {
1060 enum can_state new_state;
1061 u8 intf, eflag;
1062 u8 clear_intf = 0;
1063 int can_id = 0, data1 = 0;
1064
1065 mcp251x_read_2regs(spi, CANINTF, &intf, &eflag);
1066
1067 /* mask out flags we don't care about */
1068 intf &= CANINTF_RX | CANINTF_TX | CANINTF_ERR;
1069
1070 /* receive buffer 0 */
1071 if (intf & CANINTF_RX0IF) {
1072 mcp251x_hw_rx(spi, 0);
1073 /* Free one buffer ASAP
1074 * (The MCP2515/25625 does this automatically.)
1075 */
1076 if (mcp251x_is_2510(spi))
1077 mcp251x_write_bits(spi, CANINTF,
1078 CANINTF_RX0IF, 0x00);
1079 }
1080
1081 /* receive buffer 1 */
1082 if (intf & CANINTF_RX1IF) {
1083 mcp251x_hw_rx(spi, 1);
1084 /* The MCP2515/25625 does this automatically. */
1085 if (mcp251x_is_2510(spi))
1086 clear_intf |= CANINTF_RX1IF;
1087 }
1088
1089 /* any error or tx interrupt we need to clear? */
1090 if (intf & (CANINTF_ERR | CANINTF_TX))
1091 clear_intf |= intf & (CANINTF_ERR | CANINTF_TX);
1092 if (clear_intf)
1093 mcp251x_write_bits(spi, CANINTF, clear_intf, 0x00);
1094
1095 if (eflag & (EFLG_RX0OVR | EFLG_RX1OVR))
1096 mcp251x_write_bits(spi, EFLG, eflag, 0x00);
1097
1098 /* Update can state */
1099 if (eflag & EFLG_TXBO) {
1100 new_state = CAN_STATE_BUS_OFF;
1101 can_id |= CAN_ERR_BUSOFF;
1102 } else if (eflag & EFLG_TXEP) {
1103 new_state = CAN_STATE_ERROR_PASSIVE;
1104 can_id |= CAN_ERR_CRTL;
1105 data1 |= CAN_ERR_CRTL_TX_PASSIVE;
1106 } else if (eflag & EFLG_RXEP) {
1107 new_state = CAN_STATE_ERROR_PASSIVE;
1108 can_id |= CAN_ERR_CRTL;
1109 data1 |= CAN_ERR_CRTL_RX_PASSIVE;
1110 } else if (eflag & EFLG_TXWAR) {
1111 new_state = CAN_STATE_ERROR_WARNING;
1112 can_id |= CAN_ERR_CRTL;
1113 data1 |= CAN_ERR_CRTL_TX_WARNING;
1114 } else if (eflag & EFLG_RXWAR) {
1115 new_state = CAN_STATE_ERROR_WARNING;
1116 can_id |= CAN_ERR_CRTL;
1117 data1 |= CAN_ERR_CRTL_RX_WARNING;
1118 } else {
1119 new_state = CAN_STATE_ERROR_ACTIVE;
1120 }
1121
1122 /* Update can state statistics */
1123 switch (priv->can.state) {
1124 case CAN_STATE_ERROR_ACTIVE:
1125 if (new_state >= CAN_STATE_ERROR_WARNING &&
1126 new_state <= CAN_STATE_BUS_OFF)
1127 priv->can.can_stats.error_warning++;
1128 fallthrough;
1129 case CAN_STATE_ERROR_WARNING:
1130 if (new_state >= CAN_STATE_ERROR_PASSIVE &&
1131 new_state <= CAN_STATE_BUS_OFF)
1132 priv->can.can_stats.error_passive++;
1133 break;
1134 default:
1135 break;
1136 }
1137 priv->can.state = new_state;
1138
1139 if (intf & CANINTF_ERRIF) {
1140 /* Handle overflow counters */
1141 if (eflag & (EFLG_RX0OVR | EFLG_RX1OVR)) {
1142 if (eflag & EFLG_RX0OVR) {
1143 net->stats.rx_over_errors++;
1144 net->stats.rx_errors++;
1145 }
1146 if (eflag & EFLG_RX1OVR) {
1147 net->stats.rx_over_errors++;
1148 net->stats.rx_errors++;
1149 }
1150 can_id |= CAN_ERR_CRTL;
1151 data1 |= CAN_ERR_CRTL_RX_OVERFLOW;
1152 }
1153 mcp251x_error_skb(net, can_id, data1);
1154 }
1155
1156 if (priv->can.state == CAN_STATE_BUS_OFF) {
1157 if (priv->can.restart_ms == 0) {
1158 priv->force_quit = 1;
1159 priv->can.can_stats.bus_off++;
1160 can_bus_off(net);
1161 mcp251x_hw_sleep(spi);
1162 break;
1163 }
1164 }
1165
1166 if (intf == 0)
1167 break;
1168
1169 if (intf & CANINTF_TX) {
1170 net->stats.tx_packets++;
1171 net->stats.tx_bytes += priv->tx_len - 1;
1172 can_led_event(net, CAN_LED_EVENT_TX);
1173 if (priv->tx_len) {
1174 can_get_echo_skb(net, 0);
1175 priv->tx_len = 0;
1176 }
1177 netif_wake_queue(net);
1178 }
1179 }
1180 mutex_unlock(&priv->mcp_lock);
1181 return IRQ_HANDLED;
1182 }
1183
mcp251x_open(struct net_device * net)1184 static int mcp251x_open(struct net_device *net)
1185 {
1186 struct mcp251x_priv *priv = netdev_priv(net);
1187 struct spi_device *spi = priv->spi;
1188 unsigned long flags = 0;
1189 int ret;
1190
1191 ret = open_candev(net);
1192 if (ret) {
1193 dev_err(&spi->dev, "unable to set initial baudrate!\n");
1194 return ret;
1195 }
1196
1197 mutex_lock(&priv->mcp_lock);
1198 mcp251x_power_enable(priv->transceiver, 1);
1199
1200 priv->force_quit = 0;
1201 priv->tx_skb = NULL;
1202 priv->tx_len = 0;
1203
1204 if (!dev_fwnode(&spi->dev))
1205 flags = IRQF_TRIGGER_FALLING;
1206
1207 ret = request_threaded_irq(spi->irq, NULL, mcp251x_can_ist,
1208 flags | IRQF_ONESHOT, dev_name(&spi->dev),
1209 priv);
1210 if (ret) {
1211 dev_err(&spi->dev, "failed to acquire irq %d\n", spi->irq);
1212 goto out_close;
1213 }
1214
1215 priv->wq = alloc_workqueue("mcp251x_wq", WQ_FREEZABLE | WQ_MEM_RECLAIM,
1216 0);
1217 if (!priv->wq) {
1218 ret = -ENOMEM;
1219 goto out_clean;
1220 }
1221 INIT_WORK(&priv->tx_work, mcp251x_tx_work_handler);
1222 INIT_WORK(&priv->restart_work, mcp251x_restart_work_handler);
1223
1224 ret = mcp251x_hw_wake(spi);
1225 if (ret)
1226 goto out_free_wq;
1227 ret = mcp251x_setup(net, spi);
1228 if (ret)
1229 goto out_free_wq;
1230 ret = mcp251x_set_normal_mode(spi);
1231 if (ret)
1232 goto out_free_wq;
1233
1234 can_led_event(net, CAN_LED_EVENT_OPEN);
1235
1236 netif_wake_queue(net);
1237 mutex_unlock(&priv->mcp_lock);
1238
1239 return 0;
1240
1241 out_free_wq:
1242 destroy_workqueue(priv->wq);
1243 out_clean:
1244 free_irq(spi->irq, priv);
1245 mcp251x_hw_sleep(spi);
1246 out_close:
1247 mcp251x_power_enable(priv->transceiver, 0);
1248 close_candev(net);
1249 mutex_unlock(&priv->mcp_lock);
1250 return ret;
1251 }
1252
1253 static const struct net_device_ops mcp251x_netdev_ops = {
1254 .ndo_open = mcp251x_open,
1255 .ndo_stop = mcp251x_stop,
1256 .ndo_start_xmit = mcp251x_hard_start_xmit,
1257 .ndo_change_mtu = can_change_mtu,
1258 };
1259
1260 static const struct of_device_id mcp251x_of_match[] = {
1261 {
1262 .compatible = "microchip,mcp2510",
1263 .data = (void *)CAN_MCP251X_MCP2510,
1264 },
1265 {
1266 .compatible = "microchip,mcp2515",
1267 .data = (void *)CAN_MCP251X_MCP2515,
1268 },
1269 {
1270 .compatible = "microchip,mcp25625",
1271 .data = (void *)CAN_MCP251X_MCP25625,
1272 },
1273 { }
1274 };
1275 MODULE_DEVICE_TABLE(of, mcp251x_of_match);
1276
1277 static const struct spi_device_id mcp251x_id_table[] = {
1278 {
1279 .name = "mcp2510",
1280 .driver_data = (kernel_ulong_t)CAN_MCP251X_MCP2510,
1281 },
1282 {
1283 .name = "mcp2515",
1284 .driver_data = (kernel_ulong_t)CAN_MCP251X_MCP2515,
1285 },
1286 {
1287 .name = "mcp25625",
1288 .driver_data = (kernel_ulong_t)CAN_MCP251X_MCP25625,
1289 },
1290 { }
1291 };
1292 MODULE_DEVICE_TABLE(spi, mcp251x_id_table);
1293
mcp251x_can_probe(struct spi_device * spi)1294 static int mcp251x_can_probe(struct spi_device *spi)
1295 {
1296 const void *match = device_get_match_data(&spi->dev);
1297 struct net_device *net;
1298 struct mcp251x_priv *priv;
1299 struct clk *clk;
1300 u32 freq;
1301 int ret;
1302
1303 clk = devm_clk_get_optional(&spi->dev, NULL);
1304 if (IS_ERR(clk))
1305 return PTR_ERR(clk);
1306
1307 freq = clk_get_rate(clk);
1308 if (freq == 0)
1309 device_property_read_u32(&spi->dev, "clock-frequency", &freq);
1310
1311 /* Sanity check */
1312 if (freq < 1000000 || freq > 25000000)
1313 return -ERANGE;
1314
1315 /* Allocate can/net device */
1316 net = alloc_candev(sizeof(struct mcp251x_priv), TX_ECHO_SKB_MAX);
1317 if (!net)
1318 return -ENOMEM;
1319
1320 ret = clk_prepare_enable(clk);
1321 if (ret)
1322 goto out_free;
1323
1324 net->netdev_ops = &mcp251x_netdev_ops;
1325 net->flags |= IFF_ECHO;
1326
1327 priv = netdev_priv(net);
1328 priv->can.bittiming_const = &mcp251x_bittiming_const;
1329 priv->can.do_set_mode = mcp251x_do_set_mode;
1330 priv->can.clock.freq = freq / 2;
1331 priv->can.ctrlmode_supported = CAN_CTRLMODE_3_SAMPLES |
1332 CAN_CTRLMODE_LOOPBACK | CAN_CTRLMODE_LISTENONLY;
1333 if (match)
1334 priv->model = (enum mcp251x_model)match;
1335 else
1336 priv->model = spi_get_device_id(spi)->driver_data;
1337 priv->net = net;
1338 priv->clk = clk;
1339
1340 spi_set_drvdata(spi, priv);
1341
1342 /* Configure the SPI bus */
1343 spi->bits_per_word = 8;
1344 if (mcp251x_is_2510(spi))
1345 spi->max_speed_hz = spi->max_speed_hz ? : 5 * 1000 * 1000;
1346 else
1347 spi->max_speed_hz = spi->max_speed_hz ? : 10 * 1000 * 1000;
1348 ret = spi_setup(spi);
1349 if (ret)
1350 goto out_clk;
1351
1352 priv->power = devm_regulator_get_optional(&spi->dev, "vdd");
1353 priv->transceiver = devm_regulator_get_optional(&spi->dev, "xceiver");
1354 if ((PTR_ERR(priv->power) == -EPROBE_DEFER) ||
1355 (PTR_ERR(priv->transceiver) == -EPROBE_DEFER)) {
1356 ret = -EPROBE_DEFER;
1357 goto out_clk;
1358 }
1359
1360 ret = mcp251x_power_enable(priv->power, 1);
1361 if (ret)
1362 goto out_clk;
1363
1364 priv->spi = spi;
1365 mutex_init(&priv->mcp_lock);
1366
1367 priv->spi_tx_buf = devm_kzalloc(&spi->dev, SPI_TRANSFER_BUF_LEN,
1368 GFP_KERNEL);
1369 if (!priv->spi_tx_buf) {
1370 ret = -ENOMEM;
1371 goto error_probe;
1372 }
1373
1374 priv->spi_rx_buf = devm_kzalloc(&spi->dev, SPI_TRANSFER_BUF_LEN,
1375 GFP_KERNEL);
1376 if (!priv->spi_rx_buf) {
1377 ret = -ENOMEM;
1378 goto error_probe;
1379 }
1380
1381 SET_NETDEV_DEV(net, &spi->dev);
1382
1383 /* Here is OK to not lock the MCP, no one knows about it yet */
1384 ret = mcp251x_hw_probe(spi);
1385 if (ret) {
1386 if (ret == -ENODEV)
1387 dev_err(&spi->dev, "Cannot initialize MCP%x. Wrong wiring?\n",
1388 priv->model);
1389 goto error_probe;
1390 }
1391
1392 mcp251x_hw_sleep(spi);
1393
1394 ret = register_candev(net);
1395 if (ret)
1396 goto error_probe;
1397
1398 devm_can_led_init(net);
1399
1400 ret = mcp251x_gpio_setup(priv);
1401 if (ret)
1402 goto error_probe;
1403
1404 netdev_info(net, "MCP%x successfully initialized.\n", priv->model);
1405 return 0;
1406
1407 error_probe:
1408 mcp251x_power_enable(priv->power, 0);
1409
1410 out_clk:
1411 clk_disable_unprepare(clk);
1412
1413 out_free:
1414 free_candev(net);
1415
1416 dev_err(&spi->dev, "Probe failed, err=%d\n", -ret);
1417 return ret;
1418 }
1419
mcp251x_can_remove(struct spi_device * spi)1420 static int mcp251x_can_remove(struct spi_device *spi)
1421 {
1422 struct mcp251x_priv *priv = spi_get_drvdata(spi);
1423 struct net_device *net = priv->net;
1424
1425 unregister_candev(net);
1426
1427 mcp251x_power_enable(priv->power, 0);
1428
1429 clk_disable_unprepare(priv->clk);
1430
1431 free_candev(net);
1432
1433 return 0;
1434 }
1435
mcp251x_can_suspend(struct device * dev)1436 static int __maybe_unused mcp251x_can_suspend(struct device *dev)
1437 {
1438 struct spi_device *spi = to_spi_device(dev);
1439 struct mcp251x_priv *priv = spi_get_drvdata(spi);
1440 struct net_device *net = priv->net;
1441
1442 priv->force_quit = 1;
1443 disable_irq(spi->irq);
1444 /* Note: at this point neither IST nor workqueues are running.
1445 * open/stop cannot be called anyway so locking is not needed
1446 */
1447 if (netif_running(net)) {
1448 netif_device_detach(net);
1449
1450 mcp251x_hw_sleep(spi);
1451 mcp251x_power_enable(priv->transceiver, 0);
1452 priv->after_suspend = AFTER_SUSPEND_UP;
1453 } else {
1454 priv->after_suspend = AFTER_SUSPEND_DOWN;
1455 }
1456
1457 mcp251x_power_enable(priv->power, 0);
1458 priv->after_suspend |= AFTER_SUSPEND_POWER;
1459
1460 return 0;
1461 }
1462
mcp251x_can_resume(struct device * dev)1463 static int __maybe_unused mcp251x_can_resume(struct device *dev)
1464 {
1465 struct spi_device *spi = to_spi_device(dev);
1466 struct mcp251x_priv *priv = spi_get_drvdata(spi);
1467
1468 if (priv->after_suspend & AFTER_SUSPEND_POWER)
1469 mcp251x_power_enable(priv->power, 1);
1470 if (priv->after_suspend & AFTER_SUSPEND_UP)
1471 mcp251x_power_enable(priv->transceiver, 1);
1472
1473 if (priv->after_suspend & (AFTER_SUSPEND_POWER | AFTER_SUSPEND_UP))
1474 queue_work(priv->wq, &priv->restart_work);
1475 else
1476 priv->after_suspend = 0;
1477
1478 priv->force_quit = 0;
1479 enable_irq(spi->irq);
1480 return 0;
1481 }
1482
1483 static SIMPLE_DEV_PM_OPS(mcp251x_can_pm_ops, mcp251x_can_suspend,
1484 mcp251x_can_resume);
1485
1486 static struct spi_driver mcp251x_can_driver = {
1487 .driver = {
1488 .name = DEVICE_NAME,
1489 .of_match_table = mcp251x_of_match,
1490 .pm = &mcp251x_can_pm_ops,
1491 },
1492 .id_table = mcp251x_id_table,
1493 .probe = mcp251x_can_probe,
1494 .remove = mcp251x_can_remove,
1495 };
1496 module_spi_driver(mcp251x_can_driver);
1497
1498 MODULE_AUTHOR("Chris Elston <celston@katalix.com>, "
1499 "Christian Pellegrin <chripell@evolware.org>");
1500 MODULE_DESCRIPTION("Microchip 251x/25625 CAN driver");
1501 MODULE_LICENSE("GPL v2");
1502
