Searched refs:TEGRA194_CLK_PLLA_OUT0 (Results 1 – 2 of 2) sorted by relevance
151 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;212 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;226 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;240 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;254 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;268 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;282 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;295 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;308 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;321 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;[all …]
110 #define TEGRA194_CLK_PLLA_OUT0 104 macro
