1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * linux/arch/sh/boards/se/7724/setup.c
4 *
5 * Copyright (C) 2009 Renesas Solutions Corp.
6 *
7 * Kuninori Morimoto <morimoto.kuninori@renesas.com>
8 */
9 #include <asm/clock.h>
10 #include <asm/heartbeat.h>
11 #include <asm/io.h>
12 #include <asm/suspend.h>
13
14 #include <cpu/sh7724.h>
15
16 #include <linux/delay.h>
17 #include <linux/device.h>
18 #include <linux/gpio.h>
19 #include <linux/init.h>
20 #include <linux/input.h>
21 #include <linux/input/sh_keysc.h>
22 #include <linux/interrupt.h>
23 #include <linux/memblock.h>
24 #include <linux/mfd/tmio.h>
25 #include <linux/mmc/host.h>
26 #include <linux/mtd/physmap.h>
27 #include <linux/platform_device.h>
28 #include <linux/regulator/fixed.h>
29 #include <linux/regulator/machine.h>
30 #include <linux/sh_eth.h>
31 #include <linux/sh_intc.h>
32 #include <linux/smc91x.h>
33 #include <linux/usb/r8a66597.h>
34 #include <linux/videodev2.h>
35 #include <linux/dma-map-ops.h>
36
37 #include <mach-se/mach/se7724.h>
38 #include <media/drv-intf/renesas-ceu.h>
39
40 #include <sound/sh_fsi.h>
41 #include <sound/simple_card.h>
42
43 #include <video/sh_mobile_lcdc.h>
44
45 #define CEU_BUFFER_MEMORY_SIZE (4 << 20)
46 static phys_addr_t ceu0_dma_membase;
47 static phys_addr_t ceu1_dma_membase;
48
49 /*
50 * SWx 1234 5678
51 * ------------------------------------
52 * SW31 : 1001 1100 : default
53 * SW32 : 0111 1111 : use on board flash
54 *
55 * SW41 : abxx xxxx -> a = 0 : Analog monitor
56 * 1 : Digital monitor
57 * b = 0 : VGA
58 * 1 : 720p
59 */
60
61 /*
62 * about 720p
63 *
64 * When you use 1280 x 720 lcdc output,
65 * you should change OSC6 lcdc clock from 25.175MHz to 74.25MHz,
66 * and change SW41 to use 720p
67 */
68
69 /*
70 * about sound
71 *
72 * This setup.c supports FSI slave mode.
73 * Please change J20, J21, J22 pin to 1-2 connection.
74 */
75
76 /* Heartbeat */
77 static struct resource heartbeat_resource = {
78 .start = PA_LED,
79 .end = PA_LED,
80 .flags = IORESOURCE_MEM | IORESOURCE_MEM_16BIT,
81 };
82
83 static struct platform_device heartbeat_device = {
84 .name = "heartbeat",
85 .id = -1,
86 .num_resources = 1,
87 .resource = &heartbeat_resource,
88 };
89
90 /* LAN91C111 */
91 static struct smc91x_platdata smc91x_info = {
92 .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
93 };
94
95 static struct resource smc91x_eth_resources[] = {
96 [0] = {
97 .name = "SMC91C111" ,
98 .start = 0x1a300300,
99 .end = 0x1a30030f,
100 .flags = IORESOURCE_MEM,
101 },
102 [1] = {
103 .start = IRQ0_SMC,
104 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
105 },
106 };
107
108 static struct platform_device smc91x_eth_device = {
109 .name = "smc91x",
110 .num_resources = ARRAY_SIZE(smc91x_eth_resources),
111 .resource = smc91x_eth_resources,
112 .dev = {
113 .platform_data = &smc91x_info,
114 },
115 };
116
117 /* MTD */
118 static struct mtd_partition nor_flash_partitions[] = {
119 {
120 .name = "uboot",
121 .offset = 0,
122 .size = (1 * 1024 * 1024),
123 .mask_flags = MTD_WRITEABLE, /* Read-only */
124 }, {
125 .name = "kernel",
126 .offset = MTDPART_OFS_APPEND,
127 .size = (2 * 1024 * 1024),
128 }, {
129 .name = "free-area",
130 .offset = MTDPART_OFS_APPEND,
131 .size = MTDPART_SIZ_FULL,
132 },
133 };
134
135 static struct physmap_flash_data nor_flash_data = {
136 .width = 2,
137 .parts = nor_flash_partitions,
138 .nr_parts = ARRAY_SIZE(nor_flash_partitions),
139 };
140
141 static struct resource nor_flash_resources[] = {
142 [0] = {
143 .name = "NOR Flash",
144 .start = 0x00000000,
145 .end = 0x01ffffff,
146 .flags = IORESOURCE_MEM,
147 }
148 };
149
150 static struct platform_device nor_flash_device = {
151 .name = "physmap-flash",
152 .resource = nor_flash_resources,
153 .num_resources = ARRAY_SIZE(nor_flash_resources),
154 .dev = {
155 .platform_data = &nor_flash_data,
156 },
157 };
158
159 /* LCDC */
160 static const struct fb_videomode lcdc_720p_modes[] = {
161 {
162 .name = "LB070WV1",
163 .sync = 0, /* hsync and vsync are active low */
164 .xres = 1280,
165 .yres = 720,
166 .left_margin = 220,
167 .right_margin = 110,
168 .hsync_len = 40,
169 .upper_margin = 20,
170 .lower_margin = 5,
171 .vsync_len = 5,
172 },
173 };
174
175 static const struct fb_videomode lcdc_vga_modes[] = {
176 {
177 .name = "LB070WV1",
178 .sync = 0, /* hsync and vsync are active low */
179 .xres = 640,
180 .yres = 480,
181 .left_margin = 105,
182 .right_margin = 50,
183 .hsync_len = 96,
184 .upper_margin = 33,
185 .lower_margin = 10,
186 .vsync_len = 2,
187 },
188 };
189
190 static struct sh_mobile_lcdc_info lcdc_info = {
191 .clock_source = LCDC_CLK_EXTERNAL,
192 .ch[0] = {
193 .chan = LCDC_CHAN_MAINLCD,
194 .fourcc = V4L2_PIX_FMT_RGB565,
195 .clock_divider = 1,
196 .panel_cfg = { /* 7.0 inch */
197 .width = 152,
198 .height = 91,
199 },
200 }
201 };
202
203 static struct resource lcdc_resources[] = {
204 [0] = {
205 .name = "LCDC",
206 .start = 0xfe940000,
207 .end = 0xfe942fff,
208 .flags = IORESOURCE_MEM,
209 },
210 [1] = {
211 .start = evt2irq(0xf40),
212 .flags = IORESOURCE_IRQ,
213 },
214 };
215
216 static struct platform_device lcdc_device = {
217 .name = "sh_mobile_lcdc_fb",
218 .num_resources = ARRAY_SIZE(lcdc_resources),
219 .resource = lcdc_resources,
220 .dev = {
221 .platform_data = &lcdc_info,
222 },
223 };
224
225 /* CEU0 */
226 static struct ceu_platform_data ceu0_pdata = {
227 .num_subdevs = 0,
228 };
229
230 static struct resource ceu0_resources[] = {
231 [0] = {
232 .name = "CEU0",
233 .start = 0xfe910000,
234 .end = 0xfe91009f,
235 .flags = IORESOURCE_MEM,
236 },
237 [1] = {
238 .start = evt2irq(0x880),
239 .flags = IORESOURCE_IRQ,
240 },
241 };
242
243 static struct platform_device ceu0_device = {
244 .name = "renesas-ceu",
245 .id = 0, /* "ceu.0" clock */
246 .num_resources = ARRAY_SIZE(ceu0_resources),
247 .resource = ceu0_resources,
248 .dev = {
249 .platform_data = &ceu0_pdata,
250 },
251 };
252
253 /* CEU1 */
254 static struct ceu_platform_data ceu1_pdata = {
255 .num_subdevs = 0,
256 };
257
258 static struct resource ceu1_resources[] = {
259 [0] = {
260 .name = "CEU1",
261 .start = 0xfe914000,
262 .end = 0xfe91409f,
263 .flags = IORESOURCE_MEM,
264 },
265 [1] = {
266 .start = evt2irq(0x9e0),
267 .flags = IORESOURCE_IRQ,
268 },
269 };
270
271 static struct platform_device ceu1_device = {
272 .name = "renesas-ceu",
273 .id = 1, /* "ceu.1" clock */
274 .num_resources = ARRAY_SIZE(ceu1_resources),
275 .resource = ceu1_resources,
276 .dev = {
277 .platform_data = &ceu1_pdata,
278 },
279 };
280
281 /* FSI */
282 /* change J20, J21, J22 pin to 1-2 connection to use slave mode */
283 static struct resource fsi_resources[] = {
284 [0] = {
285 .name = "FSI",
286 .start = 0xFE3C0000,
287 .end = 0xFE3C021d,
288 .flags = IORESOURCE_MEM,
289 },
290 [1] = {
291 .start = evt2irq(0xf80),
292 .flags = IORESOURCE_IRQ,
293 },
294 };
295
296 static struct platform_device fsi_device = {
297 .name = "sh_fsi",
298 .id = 0,
299 .num_resources = ARRAY_SIZE(fsi_resources),
300 .resource = fsi_resources,
301 };
302
303 static struct asoc_simple_card_info fsi_ak4642_info = {
304 .name = "AK4642",
305 .card = "FSIA-AK4642",
306 .codec = "ak4642-codec.0-0012",
307 .platform = "sh_fsi.0",
308 .daifmt = SND_SOC_DAIFMT_LEFT_J | SND_SOC_DAIFMT_CBM_CFM,
309 .cpu_dai = {
310 .name = "fsia-dai",
311 },
312 .codec_dai = {
313 .name = "ak4642-hifi",
314 .sysclk = 11289600,
315 },
316 };
317
318 static struct platform_device fsi_ak4642_device = {
319 .name = "asoc-simple-card",
320 .dev = {
321 .platform_data = &fsi_ak4642_info,
322 },
323 };
324
325 /* KEYSC in SoC (Needs SW33-2 set to ON) */
326 static struct sh_keysc_info keysc_info = {
327 .mode = SH_KEYSC_MODE_1,
328 .scan_timing = 3,
329 .delay = 50,
330 .keycodes = {
331 KEY_1, KEY_2, KEY_3, KEY_4, KEY_5,
332 KEY_6, KEY_7, KEY_8, KEY_9, KEY_A,
333 KEY_B, KEY_C, KEY_D, KEY_E, KEY_F,
334 KEY_G, KEY_H, KEY_I, KEY_K, KEY_L,
335 KEY_M, KEY_N, KEY_O, KEY_P, KEY_Q,
336 KEY_R, KEY_S, KEY_T, KEY_U, KEY_V,
337 },
338 };
339
340 static struct resource keysc_resources[] = {
341 [0] = {
342 .name = "KEYSC",
343 .start = 0x044b0000,
344 .end = 0x044b000f,
345 .flags = IORESOURCE_MEM,
346 },
347 [1] = {
348 .start = evt2irq(0xbe0),
349 .flags = IORESOURCE_IRQ,
350 },
351 };
352
353 static struct platform_device keysc_device = {
354 .name = "sh_keysc",
355 .id = 0, /* "keysc0" clock */
356 .num_resources = ARRAY_SIZE(keysc_resources),
357 .resource = keysc_resources,
358 .dev = {
359 .platform_data = &keysc_info,
360 },
361 };
362
363 /* SH Eth */
364 static struct resource sh_eth_resources[] = {
365 [0] = {
366 .start = SH_ETH_ADDR,
367 .end = SH_ETH_ADDR + 0x1FC - 1,
368 .flags = IORESOURCE_MEM,
369 },
370 [1] = {
371 .start = evt2irq(0xd60),
372 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
373 },
374 };
375
376 static struct sh_eth_plat_data sh_eth_plat = {
377 .phy = 0x1f, /* SMSC LAN8187 */
378 .phy_interface = PHY_INTERFACE_MODE_MII,
379 };
380
381 static struct platform_device sh_eth_device = {
382 .name = "sh7724-ether",
383 .id = 0,
384 .dev = {
385 .platform_data = &sh_eth_plat,
386 },
387 .num_resources = ARRAY_SIZE(sh_eth_resources),
388 .resource = sh_eth_resources,
389 };
390
391 static struct r8a66597_platdata sh7724_usb0_host_data = {
392 .on_chip = 1,
393 };
394
395 static struct resource sh7724_usb0_host_resources[] = {
396 [0] = {
397 .start = 0xa4d80000,
398 .end = 0xa4d80124 - 1,
399 .flags = IORESOURCE_MEM,
400 },
401 [1] = {
402 .start = evt2irq(0xa20),
403 .end = evt2irq(0xa20),
404 .flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW,
405 },
406 };
407
408 static struct platform_device sh7724_usb0_host_device = {
409 .name = "r8a66597_hcd",
410 .id = 0,
411 .dev = {
412 .dma_mask = NULL, /* not use dma */
413 .coherent_dma_mask = 0xffffffff,
414 .platform_data = &sh7724_usb0_host_data,
415 },
416 .num_resources = ARRAY_SIZE(sh7724_usb0_host_resources),
417 .resource = sh7724_usb0_host_resources,
418 };
419
420 static struct r8a66597_platdata sh7724_usb1_gadget_data = {
421 .on_chip = 1,
422 };
423
424 static struct resource sh7724_usb1_gadget_resources[] = {
425 [0] = {
426 .start = 0xa4d90000,
427 .end = 0xa4d90123,
428 .flags = IORESOURCE_MEM,
429 },
430 [1] = {
431 .start = evt2irq(0xa40),
432 .end = evt2irq(0xa40),
433 .flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW,
434 },
435 };
436
437 static struct platform_device sh7724_usb1_gadget_device = {
438 .name = "r8a66597_udc",
439 .id = 1, /* USB1 */
440 .dev = {
441 .dma_mask = NULL, /* not use dma */
442 .coherent_dma_mask = 0xffffffff,
443 .platform_data = &sh7724_usb1_gadget_data,
444 },
445 .num_resources = ARRAY_SIZE(sh7724_usb1_gadget_resources),
446 .resource = sh7724_usb1_gadget_resources,
447 };
448
449 /* Fixed 3.3V regulator to be used by SDHI0, SDHI1 */
450 static struct regulator_consumer_supply fixed3v3_power_consumers[] =
451 {
452 REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.0"),
453 REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.0"),
454 REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.1"),
455 REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.1"),
456 };
457
458 static struct resource sdhi0_cn7_resources[] = {
459 [0] = {
460 .name = "SDHI0",
461 .start = 0x04ce0000,
462 .end = 0x04ce00ff,
463 .flags = IORESOURCE_MEM,
464 },
465 [1] = {
466 .start = evt2irq(0xe80),
467 .flags = IORESOURCE_IRQ,
468 },
469 };
470
471 static struct tmio_mmc_data sh7724_sdhi0_data = {
472 .chan_priv_tx = (void *)SHDMA_SLAVE_SDHI0_TX,
473 .chan_priv_rx = (void *)SHDMA_SLAVE_SDHI0_RX,
474 .capabilities = MMC_CAP_SDIO_IRQ,
475 };
476
477 static struct platform_device sdhi0_cn7_device = {
478 .name = "sh_mobile_sdhi",
479 .id = 0,
480 .num_resources = ARRAY_SIZE(sdhi0_cn7_resources),
481 .resource = sdhi0_cn7_resources,
482 .dev = {
483 .platform_data = &sh7724_sdhi0_data,
484 },
485 };
486
487 static struct resource sdhi1_cn8_resources[] = {
488 [0] = {
489 .name = "SDHI1",
490 .start = 0x04cf0000,
491 .end = 0x04cf00ff,
492 .flags = IORESOURCE_MEM,
493 },
494 [1] = {
495 .start = evt2irq(0x4e0),
496 .flags = IORESOURCE_IRQ,
497 },
498 };
499
500 static struct tmio_mmc_data sh7724_sdhi1_data = {
501 .chan_priv_tx = (void *)SHDMA_SLAVE_SDHI1_TX,
502 .chan_priv_rx = (void *)SHDMA_SLAVE_SDHI1_RX,
503 .capabilities = MMC_CAP_SDIO_IRQ,
504 };
505
506 static struct platform_device sdhi1_cn8_device = {
507 .name = "sh_mobile_sdhi",
508 .id = 1,
509 .num_resources = ARRAY_SIZE(sdhi1_cn8_resources),
510 .resource = sdhi1_cn8_resources,
511 .dev = {
512 .platform_data = &sh7724_sdhi1_data,
513 },
514 };
515
516 /* IrDA */
517 static struct resource irda_resources[] = {
518 [0] = {
519 .name = "IrDA",
520 .start = 0xA45D0000,
521 .end = 0xA45D0049,
522 .flags = IORESOURCE_MEM,
523 },
524 [1] = {
525 .start = evt2irq(0x480),
526 .flags = IORESOURCE_IRQ,
527 },
528 };
529
530 static struct platform_device irda_device = {
531 .name = "sh_sir",
532 .num_resources = ARRAY_SIZE(irda_resources),
533 .resource = irda_resources,
534 };
535
536 #include <media/i2c/ak881x.h>
537 #include <media/drv-intf/sh_vou.h>
538
539 static struct ak881x_pdata ak881x_pdata = {
540 .flags = AK881X_IF_MODE_SLAVE,
541 };
542
543 static struct i2c_board_info ak8813 = {
544 /* With open J18 jumper address is 0x21 */
545 I2C_BOARD_INFO("ak8813", 0x20),
546 .platform_data = &ak881x_pdata,
547 };
548
549 static struct sh_vou_pdata sh_vou_pdata = {
550 .bus_fmt = SH_VOU_BUS_8BIT,
551 .flags = SH_VOU_HSYNC_LOW | SH_VOU_VSYNC_LOW,
552 .board_info = &ak8813,
553 .i2c_adap = 0,
554 };
555
556 static struct resource sh_vou_resources[] = {
557 [0] = {
558 .start = 0xfe960000,
559 .end = 0xfe962043,
560 .flags = IORESOURCE_MEM,
561 },
562 [1] = {
563 .start = evt2irq(0x8e0),
564 .flags = IORESOURCE_IRQ,
565 },
566 };
567
568 static struct platform_device vou_device = {
569 .name = "sh-vou",
570 .id = -1,
571 .num_resources = ARRAY_SIZE(sh_vou_resources),
572 .resource = sh_vou_resources,
573 .dev = {
574 .platform_data = &sh_vou_pdata,
575 },
576 };
577
578 static struct platform_device *ms7724se_ceu_devices[] __initdata = {
579 &ceu0_device,
580 &ceu1_device,
581 };
582
583 static struct platform_device *ms7724se_devices[] __initdata = {
584 &heartbeat_device,
585 &smc91x_eth_device,
586 &lcdc_device,
587 &nor_flash_device,
588 &keysc_device,
589 &sh_eth_device,
590 &sh7724_usb0_host_device,
591 &sh7724_usb1_gadget_device,
592 &fsi_device,
593 &fsi_ak4642_device,
594 &sdhi0_cn7_device,
595 &sdhi1_cn8_device,
596 &irda_device,
597 &vou_device,
598 };
599
600 /* I2C device */
601 static struct i2c_board_info i2c0_devices[] = {
602 {
603 I2C_BOARD_INFO("ak4642", 0x12),
604 },
605 };
606
607 #define EEPROM_OP 0xBA206000
608 #define EEPROM_ADR 0xBA206004
609 #define EEPROM_DATA 0xBA20600C
610 #define EEPROM_STAT 0xBA206010
611 #define EEPROM_STRT 0xBA206014
612
sh_eth_is_eeprom_ready(void)613 static int __init sh_eth_is_eeprom_ready(void)
614 {
615 int t = 10000;
616
617 while (t--) {
618 if (!__raw_readw(EEPROM_STAT))
619 return 1;
620 udelay(1);
621 }
622
623 printk(KERN_ERR "ms7724se can not access to eeprom\n");
624 return 0;
625 }
626
sh_eth_init(void)627 static void __init sh_eth_init(void)
628 {
629 int i;
630 u16 mac;
631
632 /* check EEPROM status */
633 if (!sh_eth_is_eeprom_ready())
634 return;
635
636 /* read MAC addr from EEPROM */
637 for (i = 0 ; i < 3 ; i++) {
638 __raw_writew(0x0, EEPROM_OP); /* read */
639 __raw_writew(i*2, EEPROM_ADR);
640 __raw_writew(0x1, EEPROM_STRT);
641 if (!sh_eth_is_eeprom_ready())
642 return;
643
644 mac = __raw_readw(EEPROM_DATA);
645 sh_eth_plat.mac_addr[i << 1] = mac & 0xff;
646 sh_eth_plat.mac_addr[(i << 1) + 1] = mac >> 8;
647 }
648 }
649
650 #define SW4140 0xBA201000
651 #define FPGA_OUT 0xBA200400
652 #define PORT_HIZA 0xA4050158
653 #define PORT_MSELCRB 0xA4050182
654
655 #define SW41_A 0x0100
656 #define SW41_B 0x0200
657 #define SW41_C 0x0400
658 #define SW41_D 0x0800
659 #define SW41_E 0x1000
660 #define SW41_F 0x2000
661 #define SW41_G 0x4000
662 #define SW41_H 0x8000
663
664 extern char ms7724se_sdram_enter_start;
665 extern char ms7724se_sdram_enter_end;
666 extern char ms7724se_sdram_leave_start;
667 extern char ms7724se_sdram_leave_end;
668
arch_setup(void)669 static int __init arch_setup(void)
670 {
671 /* enable I2C device */
672 i2c_register_board_info(0, i2c0_devices,
673 ARRAY_SIZE(i2c0_devices));
674 return 0;
675 }
676 arch_initcall(arch_setup);
677
devices_setup(void)678 static int __init devices_setup(void)
679 {
680 u16 sw = __raw_readw(SW4140); /* select camera, monitor */
681 struct clk *clk;
682 u16 fpga_out;
683
684 /* register board specific self-refresh code */
685 sh_mobile_register_self_refresh(SUSP_SH_STANDBY | SUSP_SH_SF |
686 SUSP_SH_RSTANDBY,
687 &ms7724se_sdram_enter_start,
688 &ms7724se_sdram_enter_end,
689 &ms7724se_sdram_leave_start,
690 &ms7724se_sdram_leave_end);
691
692 regulator_register_always_on(0, "fixed-3.3V", fixed3v3_power_consumers,
693 ARRAY_SIZE(fixed3v3_power_consumers), 3300000);
694
695 /* Reset Release */
696 fpga_out = __raw_readw(FPGA_OUT);
697 /* bit4: NTSC_PDN, bit5: NTSC_RESET */
698 fpga_out &= ~((1 << 1) | /* LAN */
699 (1 << 4) | /* AK8813 PDN */
700 (1 << 5) | /* AK8813 RESET */
701 (1 << 6) | /* VIDEO DAC */
702 (1 << 7) | /* AK4643 */
703 (1 << 8) | /* IrDA */
704 (1 << 12) | /* USB0 */
705 (1 << 14)); /* RMII */
706 __raw_writew(fpga_out | (1 << 4), FPGA_OUT);
707
708 udelay(10);
709
710 /* AK8813 RESET */
711 __raw_writew(fpga_out | (1 << 5), FPGA_OUT);
712
713 udelay(10);
714
715 __raw_writew(fpga_out, FPGA_OUT);
716
717 /* turn on USB clocks, use external clock */
718 __raw_writew((__raw_readw(PORT_MSELCRB) & ~0xc000) | 0x8000, PORT_MSELCRB);
719
720 /* Let LED9 show STATUS2 */
721 gpio_request(GPIO_FN_STATUS2, NULL);
722
723 /* Lit LED10 show STATUS0 */
724 gpio_request(GPIO_FN_STATUS0, NULL);
725
726 /* Lit LED11 show PDSTATUS */
727 gpio_request(GPIO_FN_PDSTATUS, NULL);
728
729 /* enable USB0 port */
730 __raw_writew(0x0600, 0xa40501d4);
731
732 /* enable USB1 port */
733 __raw_writew(0x0600, 0xa4050192);
734
735 /* enable IRQ 0,1,2 */
736 gpio_request(GPIO_FN_INTC_IRQ0, NULL);
737 gpio_request(GPIO_FN_INTC_IRQ1, NULL);
738 gpio_request(GPIO_FN_INTC_IRQ2, NULL);
739
740 /* enable SCIFA3 */
741 gpio_request(GPIO_FN_SCIF3_I_SCK, NULL);
742 gpio_request(GPIO_FN_SCIF3_I_RXD, NULL);
743 gpio_request(GPIO_FN_SCIF3_I_TXD, NULL);
744 gpio_request(GPIO_FN_SCIF3_I_CTS, NULL);
745 gpio_request(GPIO_FN_SCIF3_I_RTS, NULL);
746
747 /* enable LCDC */
748 gpio_request(GPIO_FN_LCDD23, NULL);
749 gpio_request(GPIO_FN_LCDD22, NULL);
750 gpio_request(GPIO_FN_LCDD21, NULL);
751 gpio_request(GPIO_FN_LCDD20, NULL);
752 gpio_request(GPIO_FN_LCDD19, NULL);
753 gpio_request(GPIO_FN_LCDD18, NULL);
754 gpio_request(GPIO_FN_LCDD17, NULL);
755 gpio_request(GPIO_FN_LCDD16, NULL);
756 gpio_request(GPIO_FN_LCDD15, NULL);
757 gpio_request(GPIO_FN_LCDD14, NULL);
758 gpio_request(GPIO_FN_LCDD13, NULL);
759 gpio_request(GPIO_FN_LCDD12, NULL);
760 gpio_request(GPIO_FN_LCDD11, NULL);
761 gpio_request(GPIO_FN_LCDD10, NULL);
762 gpio_request(GPIO_FN_LCDD9, NULL);
763 gpio_request(GPIO_FN_LCDD8, NULL);
764 gpio_request(GPIO_FN_LCDD7, NULL);
765 gpio_request(GPIO_FN_LCDD6, NULL);
766 gpio_request(GPIO_FN_LCDD5, NULL);
767 gpio_request(GPIO_FN_LCDD4, NULL);
768 gpio_request(GPIO_FN_LCDD3, NULL);
769 gpio_request(GPIO_FN_LCDD2, NULL);
770 gpio_request(GPIO_FN_LCDD1, NULL);
771 gpio_request(GPIO_FN_LCDD0, NULL);
772 gpio_request(GPIO_FN_LCDDISP, NULL);
773 gpio_request(GPIO_FN_LCDHSYN, NULL);
774 gpio_request(GPIO_FN_LCDDCK, NULL);
775 gpio_request(GPIO_FN_LCDVSYN, NULL);
776 gpio_request(GPIO_FN_LCDDON, NULL);
777 gpio_request(GPIO_FN_LCDVEPWC, NULL);
778 gpio_request(GPIO_FN_LCDVCPWC, NULL);
779 gpio_request(GPIO_FN_LCDRD, NULL);
780 gpio_request(GPIO_FN_LCDLCLK, NULL);
781 __raw_writew((__raw_readw(PORT_HIZA) & ~0x0001), PORT_HIZA);
782
783 /* enable CEU0 */
784 gpio_request(GPIO_FN_VIO0_D15, NULL);
785 gpio_request(GPIO_FN_VIO0_D14, NULL);
786 gpio_request(GPIO_FN_VIO0_D13, NULL);
787 gpio_request(GPIO_FN_VIO0_D12, NULL);
788 gpio_request(GPIO_FN_VIO0_D11, NULL);
789 gpio_request(GPIO_FN_VIO0_D10, NULL);
790 gpio_request(GPIO_FN_VIO0_D9, NULL);
791 gpio_request(GPIO_FN_VIO0_D8, NULL);
792 gpio_request(GPIO_FN_VIO0_D7, NULL);
793 gpio_request(GPIO_FN_VIO0_D6, NULL);
794 gpio_request(GPIO_FN_VIO0_D5, NULL);
795 gpio_request(GPIO_FN_VIO0_D4, NULL);
796 gpio_request(GPIO_FN_VIO0_D3, NULL);
797 gpio_request(GPIO_FN_VIO0_D2, NULL);
798 gpio_request(GPIO_FN_VIO0_D1, NULL);
799 gpio_request(GPIO_FN_VIO0_D0, NULL);
800 gpio_request(GPIO_FN_VIO0_VD, NULL);
801 gpio_request(GPIO_FN_VIO0_CLK, NULL);
802 gpio_request(GPIO_FN_VIO0_FLD, NULL);
803 gpio_request(GPIO_FN_VIO0_HD, NULL);
804
805 /* enable CEU1 */
806 gpio_request(GPIO_FN_VIO1_D7, NULL);
807 gpio_request(GPIO_FN_VIO1_D6, NULL);
808 gpio_request(GPIO_FN_VIO1_D5, NULL);
809 gpio_request(GPIO_FN_VIO1_D4, NULL);
810 gpio_request(GPIO_FN_VIO1_D3, NULL);
811 gpio_request(GPIO_FN_VIO1_D2, NULL);
812 gpio_request(GPIO_FN_VIO1_D1, NULL);
813 gpio_request(GPIO_FN_VIO1_D0, NULL);
814 gpio_request(GPIO_FN_VIO1_FLD, NULL);
815 gpio_request(GPIO_FN_VIO1_HD, NULL);
816 gpio_request(GPIO_FN_VIO1_VD, NULL);
817 gpio_request(GPIO_FN_VIO1_CLK, NULL);
818
819 /* KEYSC */
820 gpio_request(GPIO_FN_KEYOUT5_IN5, NULL);
821 gpio_request(GPIO_FN_KEYOUT4_IN6, NULL);
822 gpio_request(GPIO_FN_KEYIN4, NULL);
823 gpio_request(GPIO_FN_KEYIN3, NULL);
824 gpio_request(GPIO_FN_KEYIN2, NULL);
825 gpio_request(GPIO_FN_KEYIN1, NULL);
826 gpio_request(GPIO_FN_KEYIN0, NULL);
827 gpio_request(GPIO_FN_KEYOUT3, NULL);
828 gpio_request(GPIO_FN_KEYOUT2, NULL);
829 gpio_request(GPIO_FN_KEYOUT1, NULL);
830 gpio_request(GPIO_FN_KEYOUT0, NULL);
831
832 /* enable FSI */
833 gpio_request(GPIO_FN_FSIMCKA, NULL);
834 gpio_request(GPIO_FN_FSIIASD, NULL);
835 gpio_request(GPIO_FN_FSIOASD, NULL);
836 gpio_request(GPIO_FN_FSIIABCK, NULL);
837 gpio_request(GPIO_FN_FSIIALRCK, NULL);
838 gpio_request(GPIO_FN_FSIOABCK, NULL);
839 gpio_request(GPIO_FN_FSIOALRCK, NULL);
840 gpio_request(GPIO_FN_CLKAUDIOAO, NULL);
841
842 /* set SPU2 clock to 83.4 MHz */
843 clk = clk_get(NULL, "spu_clk");
844 if (!IS_ERR(clk)) {
845 clk_set_rate(clk, clk_round_rate(clk, 83333333));
846 clk_put(clk);
847 }
848
849 /* change parent of FSI A */
850 clk = clk_get(NULL, "fsia_clk");
851 if (!IS_ERR(clk)) {
852 /* 48kHz dummy clock was used to make sure 1/1 divide */
853 clk_set_rate(&sh7724_fsimcka_clk, 48000);
854 clk_set_parent(clk, &sh7724_fsimcka_clk);
855 clk_set_rate(clk, 48000);
856 clk_put(clk);
857 }
858
859 /* SDHI0 connected to cn7 */
860 gpio_request(GPIO_FN_SDHI0CD, NULL);
861 gpio_request(GPIO_FN_SDHI0WP, NULL);
862 gpio_request(GPIO_FN_SDHI0D3, NULL);
863 gpio_request(GPIO_FN_SDHI0D2, NULL);
864 gpio_request(GPIO_FN_SDHI0D1, NULL);
865 gpio_request(GPIO_FN_SDHI0D0, NULL);
866 gpio_request(GPIO_FN_SDHI0CMD, NULL);
867 gpio_request(GPIO_FN_SDHI0CLK, NULL);
868
869 /* SDHI1 connected to cn8 */
870 gpio_request(GPIO_FN_SDHI1CD, NULL);
871 gpio_request(GPIO_FN_SDHI1WP, NULL);
872 gpio_request(GPIO_FN_SDHI1D3, NULL);
873 gpio_request(GPIO_FN_SDHI1D2, NULL);
874 gpio_request(GPIO_FN_SDHI1D1, NULL);
875 gpio_request(GPIO_FN_SDHI1D0, NULL);
876 gpio_request(GPIO_FN_SDHI1CMD, NULL);
877 gpio_request(GPIO_FN_SDHI1CLK, NULL);
878
879 /* enable IrDA */
880 gpio_request(GPIO_FN_IRDA_OUT, NULL);
881 gpio_request(GPIO_FN_IRDA_IN, NULL);
882
883 /*
884 * enable SH-Eth
885 *
886 * please remove J33 pin from your board !!
887 *
888 * ms7724 board should not use GPIO_FN_LNKSTA pin
889 * So, This time PTX5 is set to input pin
890 */
891 gpio_request(GPIO_FN_RMII_RXD0, NULL);
892 gpio_request(GPIO_FN_RMII_RXD1, NULL);
893 gpio_request(GPIO_FN_RMII_TXD0, NULL);
894 gpio_request(GPIO_FN_RMII_TXD1, NULL);
895 gpio_request(GPIO_FN_RMII_REF_CLK, NULL);
896 gpio_request(GPIO_FN_RMII_TX_EN, NULL);
897 gpio_request(GPIO_FN_RMII_RX_ER, NULL);
898 gpio_request(GPIO_FN_RMII_CRS_DV, NULL);
899 gpio_request(GPIO_FN_MDIO, NULL);
900 gpio_request(GPIO_FN_MDC, NULL);
901 gpio_request(GPIO_PTX5, NULL);
902 gpio_direction_input(GPIO_PTX5);
903 sh_eth_init();
904
905 if (sw & SW41_B) {
906 /* 720p */
907 lcdc_info.ch[0].lcd_modes = lcdc_720p_modes;
908 lcdc_info.ch[0].num_modes = ARRAY_SIZE(lcdc_720p_modes);
909 } else {
910 /* VGA */
911 lcdc_info.ch[0].lcd_modes = lcdc_vga_modes;
912 lcdc_info.ch[0].num_modes = ARRAY_SIZE(lcdc_vga_modes);
913 }
914
915 if (sw & SW41_A) {
916 /* Digital monitor */
917 lcdc_info.ch[0].interface_type = RGB18;
918 lcdc_info.ch[0].flags = 0;
919 } else {
920 /* Analog monitor */
921 lcdc_info.ch[0].interface_type = RGB24;
922 lcdc_info.ch[0].flags = LCDC_FLAGS_DWPOL;
923 }
924
925 /* VOU */
926 gpio_request(GPIO_FN_DV_D15, NULL);
927 gpio_request(GPIO_FN_DV_D14, NULL);
928 gpio_request(GPIO_FN_DV_D13, NULL);
929 gpio_request(GPIO_FN_DV_D12, NULL);
930 gpio_request(GPIO_FN_DV_D11, NULL);
931 gpio_request(GPIO_FN_DV_D10, NULL);
932 gpio_request(GPIO_FN_DV_D9, NULL);
933 gpio_request(GPIO_FN_DV_D8, NULL);
934 gpio_request(GPIO_FN_DV_CLKI, NULL);
935 gpio_request(GPIO_FN_DV_CLK, NULL);
936 gpio_request(GPIO_FN_DV_VSYNC, NULL);
937 gpio_request(GPIO_FN_DV_HSYNC, NULL);
938
939 /* Initialize CEU platform devices separately to map memory first */
940 device_initialize(&ms7724se_ceu_devices[0]->dev);
941 dma_declare_coherent_memory(&ms7724se_ceu_devices[0]->dev,
942 ceu0_dma_membase, ceu0_dma_membase,
943 ceu0_dma_membase +
944 CEU_BUFFER_MEMORY_SIZE - 1);
945 platform_device_add(ms7724se_ceu_devices[0]);
946
947 device_initialize(&ms7724se_ceu_devices[1]->dev);
948 dma_declare_coherent_memory(&ms7724se_ceu_devices[1]->dev,
949 ceu1_dma_membase, ceu1_dma_membase,
950 ceu1_dma_membase +
951 CEU_BUFFER_MEMORY_SIZE - 1);
952 platform_device_add(ms7724se_ceu_devices[1]);
953
954 return platform_add_devices(ms7724se_devices,
955 ARRAY_SIZE(ms7724se_devices));
956 }
957 device_initcall(devices_setup);
958
959 /* Reserve a portion of memory for CEU 0 and CEU 1 buffers */
ms7724se_mv_mem_reserve(void)960 static void __init ms7724se_mv_mem_reserve(void)
961 {
962 phys_addr_t phys;
963 phys_addr_t size = CEU_BUFFER_MEMORY_SIZE;
964
965 phys = memblock_phys_alloc(size, PAGE_SIZE);
966 if (!phys)
967 panic("Failed to allocate CEU0 memory\n");
968
969 memblock_free(phys, size);
970 memblock_remove(phys, size);
971 ceu0_dma_membase = phys;
972
973 phys = memblock_phys_alloc(size, PAGE_SIZE);
974 if (!phys)
975 panic("Failed to allocate CEU1 memory\n");
976
977 memblock_free(phys, size);
978 memblock_remove(phys, size);
979 ceu1_dma_membase = phys;
980 }
981
982 static struct sh_machine_vector mv_ms7724se __initmv = {
983 .mv_name = "ms7724se",
984 .mv_init_irq = init_se7724_IRQ,
985 .mv_mem_reserve = ms7724se_mv_mem_reserve,
986 };
987
