Searched refs:SSE (Results 1 – 9 of 9) sorted by relevance
124 jz .Lverify_cpu_no_longmode # only try to force SSE on AMD127 btr $15,%eax # enable SSE
2 # Implement fast CRC-T10DIF computation with SSE and PCLMULQDQ instructions
231 # the state matrix in SSE registers four times. As we need some scratch236 # which allows us to do XOR in SSE registers. 8/16-bit word rotation is
591 #define SSE 0x40 macro1942 if (status1 & SSE) { in ahc_pci_intr()1963 if ((status1 & (DPE|SSE|RMA|RTA|STA|DPR)) == 0) { in ahc_pci_intr()
1144 field SSE 0x401162 field SSE 0x401179 field SSE 0x401195 field SSE 0x401212 field SSE 0x401227 field SSE 0x401244 field SSE 0x40
732 #define SSE 0x40 macro
1309 #define SSE 0x40
251 of SSE and tells gcc to treat the CPU as a 686.
1704 D: Pentium III FXSR, SSE support
