Searched refs:SPRN_L1CSR0 (Results 1 – 4 of 4) sorted by relevance
30 mfspr r0, SPRN_L1CSR036 mtspr SPRN_L1CSR0, r0 /* Disable */40 mtspr SPRN_L1CSR0, r0 /* Invalidate */42 1: mfspr r0, SPRN_L1CSR049 mtspr SPRN_L1CSR0, r0 /* Enable */
227 tmp = mfspr(SPRN_L1CSR0); in flush_instruction_cache()229 mtspr(SPRN_L1CSR0, tmp); in flush_instruction_cache()
248 case SPRN_L1CSR0: in kvmppc_core_emulate_mtspr_e500()378 case SPRN_L1CSR0: in kvmppc_core_emulate_mfspr_e500()
173 #define SPRN_L1CSR0 0x3F2 /* L1 Cache Control and Status Register 0 */ macro
