Searched refs:SIMD (Results 1 – 10 of 10) sorted by relevance
23 fallback, e.g., for SIMD implementations. If no arch specific49 fallback, e.g., for SIMD implementations. If no arch specific74 fallback, e.g., for SIMD implementations. If no arch specific109 fallback, e.g., for SIMD implementations. If no arch specific
84 uint32_t SIMD:2; /* SIMD id */ member
507 reg_sq_cmd.bits.simd_id = pMsg->ui32.SIMD; in dbgdev_wave_control_set_registers()
137 tristate "Accelerated scalar and SIMD Poly1305 hash implementations"
483 * All SVE register bits that are not shared with FP/SIMD are caller-save.491 Appendix B. ARMv8-A FP/SIMD programmer's model499 ARMv8-A defines the following floating-point / SIMD register state:
334 bool "Support SIMD acceleration for AEGIS-128"770 in IETF protocols. This is the x86_64 assembler implementation using SIMD949 using powerpc SPE SIMD instruction set.971 implemented using powerpc SPE SIMD instruction set.
2546 bool "Support for the MIPS SIMD Architecture"2551 MIPS SIMD Architecture (MSA) introduces 128 bit wide vector registers2552 and a set of SIMD instructions to operate on them. When this option
2012 bool "Advanced SIMD (NEON) Extension support"2015 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
1698 execution state which complements and extends the SIMD functionality
2369 arm64 core/FP-SIMD registers have the following id bit patterns. Note2524 if the guest FPU mode is changed. MIPS SIMD Architecture (MSA) vector5541 This capability allows the use of the MIPS SIMD Architecture (MSA) by the guest.
