Searched refs:SDMA0_ME_CNTL (Results 1 – 3 of 3) sorted by relevance
346 me_cntl = RREG32(SDMA0_ME_CNTL + reg_offset); in cik_sdma_enable()351 WREG32(SDMA0_ME_CNTL + reg_offset, me_cntl); in cik_sdma_enable()
4964 tmp = RREG32(SDMA0_ME_CNTL + SDMA0_REGISTER_OFFSET); in cik_gpu_soft_reset()4966 WREG32(SDMA0_ME_CNTL + SDMA0_REGISTER_OFFSET, tmp); in cik_gpu_soft_reset()4970 tmp = RREG32(SDMA0_ME_CNTL + SDMA1_REGISTER_OFFSET); in cik_gpu_soft_reset()4972 WREG32(SDMA0_ME_CNTL + SDMA1_REGISTER_OFFSET, tmp); in cik_gpu_soft_reset()5167 tmp = RREG32(SDMA0_ME_CNTL + SDMA0_REGISTER_OFFSET); in cik_gpu_pci_config_reset()5169 WREG32(SDMA0_ME_CNTL + SDMA0_REGISTER_OFFSET, tmp); in cik_gpu_pci_config_reset()5171 tmp = RREG32(SDMA0_ME_CNTL + SDMA1_REGISTER_OFFSET); in cik_gpu_pci_config_reset()5173 WREG32(SDMA0_ME_CNTL + SDMA1_REGISTER_OFFSET, tmp); in cik_gpu_pci_config_reset()
1977 #define SDMA0_ME_CNTL 0xD048 macro
