1  /* SPDX-License-Identifier: GPL-2.0 */
2  /*
3   * Copyright 2007 Simtec Electronics <linux@simtec.co.uk>
4   *	http://armlinux.simtec.co.uk/
5   *
6   * S3C2412 IIS register definition
7   */
8  
9  #ifndef __ASM_ARCH_REGS_S3C2412_IIS_H
10  #define __ASM_ARCH_REGS_S3C2412_IIS_H
11  
12  #define S3C2412_IISCON			(0x00)
13  #define S3C2412_IISMOD			(0x04)
14  #define S3C2412_IISFIC			(0x08)
15  #define S3C2412_IISPSR			(0x0C)
16  #define S3C2412_IISTXD			(0x10)
17  #define S3C2412_IISRXD			(0x14)
18  
19  #define S5PC1XX_IISFICS		0x18
20  #define S5PC1XX_IISTXDS		0x1C
21  
22  #define S5PC1XX_IISCON_SW_RST		(1 << 31)
23  #define S5PC1XX_IISCON_FRXOFSTATUS	(1 << 26)
24  #define S5PC1XX_IISCON_FRXORINTEN	(1 << 25)
25  #define S5PC1XX_IISCON_FTXSURSTAT	(1 << 24)
26  #define S5PC1XX_IISCON_FTXSURINTEN	(1 << 23)
27  #define S5PC1XX_IISCON_TXSDMAPAUSE	(1 << 20)
28  #define S5PC1XX_IISCON_TXSDMACTIVE	(1 << 18)
29  
30  #define S3C64XX_IISCON_FTXURSTATUS	(1 << 17)
31  #define S3C64XX_IISCON_FTXURINTEN	(1 << 16)
32  #define S3C64XX_IISCON_TXFIFO2_EMPTY	(1 << 15)
33  #define S3C64XX_IISCON_TXFIFO1_EMPTY	(1 << 14)
34  #define S3C64XX_IISCON_TXFIFO2_FULL	(1 << 13)
35  #define S3C64XX_IISCON_TXFIFO1_FULL	(1 << 12)
36  
37  #define S3C2412_IISCON_LRINDEX		(1 << 11)
38  #define S3C2412_IISCON_TXFIFO_EMPTY	(1 << 10)
39  #define S3C2412_IISCON_RXFIFO_EMPTY	(1 << 9)
40  #define S3C2412_IISCON_TXFIFO_FULL	(1 << 8)
41  #define S3C2412_IISCON_RXFIFO_FULL	(1 << 7)
42  #define S3C2412_IISCON_TXDMA_PAUSE	(1 << 6)
43  #define S3C2412_IISCON_RXDMA_PAUSE	(1 << 5)
44  #define S3C2412_IISCON_TXCH_PAUSE	(1 << 4)
45  #define S3C2412_IISCON_RXCH_PAUSE	(1 << 3)
46  #define S3C2412_IISCON_TXDMA_ACTIVE	(1 << 2)
47  #define S3C2412_IISCON_RXDMA_ACTIVE	(1 << 1)
48  #define S3C2412_IISCON_IIS_ACTIVE	(1 << 0)
49  
50  #define S5PC1XX_IISMOD_OPCLK_CDCLK_OUT	(0 << 30)
51  #define S5PC1XX_IISMOD_OPCLK_CDCLK_IN	(1 << 30)
52  #define S5PC1XX_IISMOD_OPCLK_BCLK_OUT	(2 << 30)
53  #define S5PC1XX_IISMOD_OPCLK_PCLK	(3 << 30)
54  #define S5PC1XX_IISMOD_OPCLK_MASK	(3 << 30)
55  #define S5PC1XX_IISMOD_TXS_IDMA		(1 << 28) /* Sec_TXFIFO use I-DMA */
56  #define S5PC1XX_IISMOD_BLCS_MASK	0x3
57  #define S5PC1XX_IISMOD_BLCS_SHIFT	26
58  #define S5PC1XX_IISMOD_BLCP_MASK	0x3
59  #define S5PC1XX_IISMOD_BLCP_SHIFT	24
60  
61  #define S3C64XX_IISMOD_C2DD_HHALF	(1 << 21) /* Discard Higher-half */
62  #define S3C64XX_IISMOD_C2DD_LHALF	(1 << 20) /* Discard Lower-half */
63  #define S3C64XX_IISMOD_C1DD_HHALF	(1 << 19)
64  #define S3C64XX_IISMOD_C1DD_LHALF	(1 << 18)
65  #define S3C64XX_IISMOD_DC2_EN		(1 << 17)
66  #define S3C64XX_IISMOD_DC1_EN		(1 << 16)
67  #define S3C64XX_IISMOD_BLC_16BIT	(0 << 13)
68  #define S3C64XX_IISMOD_BLC_8BIT		(1 << 13)
69  #define S3C64XX_IISMOD_BLC_24BIT	(2 << 13)
70  #define S3C64XX_IISMOD_BLC_MASK		(3 << 13)
71  
72  #define S3C2412_IISMOD_IMS_SYSMUX	(1 << 10)
73  #define S3C2412_IISMOD_SLAVE		(1 << 11)
74  #define S3C2412_IISMOD_MODE_TXONLY	(0 << 8)
75  #define S3C2412_IISMOD_MODE_RXONLY	(1 << 8)
76  #define S3C2412_IISMOD_MODE_TXRX	(2 << 8)
77  #define S3C2412_IISMOD_MODE_MASK	(3 << 8)
78  #define S3C2412_IISMOD_LR_LLOW		(0 << 7)
79  #define S3C2412_IISMOD_LR_RLOW		(1 << 7)
80  #define S3C2412_IISMOD_SDF_IIS		(0 << 5)
81  #define S3C2412_IISMOD_SDF_MSB		(1 << 5)
82  #define S3C2412_IISMOD_SDF_LSB		(2 << 5)
83  #define S3C2412_IISMOD_SDF_MASK		(3 << 5)
84  #define S3C2412_IISMOD_RCLK_256FS	(0 << 3)
85  #define S3C2412_IISMOD_RCLK_512FS	(1 << 3)
86  #define S3C2412_IISMOD_RCLK_384FS	(2 << 3)
87  #define S3C2412_IISMOD_RCLK_768FS	(3 << 3)
88  #define S3C2412_IISMOD_RCLK_MASK 	(3 << 3)
89  #define S3C2412_IISMOD_BCLK_32FS	(0 << 1)
90  #define S3C2412_IISMOD_BCLK_48FS	(1 << 1)
91  #define S3C2412_IISMOD_BCLK_16FS	(2 << 1)
92  #define S3C2412_IISMOD_BCLK_24FS	(3 << 1)
93  #define S3C2412_IISMOD_BCLK_MASK	(3 << 1)
94  #define S3C2412_IISMOD_8BIT		(1 << 0)
95  
96  #define S3C64XX_IISMOD_CDCLKCON		(1 << 12)
97  
98  #define S3C2412_IISPSR_PSREN		(1 << 15)
99  
100  #define S3C64XX_IISFIC_TX2COUNT(x)	(((x) >>  24) & 0xf)
101  #define S3C64XX_IISFIC_TX1COUNT(x)	(((x) >>  16) & 0xf)
102  
103  #define S3C2412_IISFIC_TXFLUSH		(1 << 15)
104  #define S3C2412_IISFIC_RXFLUSH		(1 << 7)
105  #define S3C2412_IISFIC_TXCOUNT(x)	(((x) >>  8) & 0xf)
106  #define S3C2412_IISFIC_RXCOUNT(x)	(((x) >>  0) & 0xf)
107  
108  #define S5PC1XX_IISFICS_TXFLUSH		(1 << 15)
109  #define S5PC1XX_IISFICS_TXCOUNT(x)	(((x) >>  8) & 0x7f)
110  
111  #endif /* __ASM_ARCH_REGS_S3C2412_IIS_H */
112