Searched refs:R_IMR_MAILBOX_CLR_CPU (Results 1 – 3 of 3) sorted by relevance
26 IOADDR(A_IMR_CPU0_BASE + R_IMR_MAILBOX_CLR_CPU),27 IOADDR(A_IMR_CPU1_BASE + R_IMR_MAILBOX_CLR_CPU)
256 IOADDR(A_IMR_REGISTER(0, R_IMR_MAILBOX_CLR_CPU))); in arch_init_irq()258 IOADDR(A_IMR_REGISTER(1, R_IMR_MAILBOX_CLR_CPU))); in arch_init_irq()
718 #define R_IMR_MAILBOX_CLR_CPU 0x00D0 macro
