1 /*
2 * Copyright(c) 2015 - 2020 Intel Corporation.
3 *
4 * This file is provided under a dual BSD/GPLv2 license. When using or
5 * redistributing this file, you may do so under either license.
6 *
7 * GPL LICENSE SUMMARY
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of version 2 of the GNU General Public License as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 *
18 * BSD LICENSE
19 *
20 * Redistribution and use in source and binary forms, with or without
21 * modification, are permitted provided that the following conditions
22 * are met:
23 *
24 * - Redistributions of source code must retain the above copyright
25 * notice, this list of conditions and the following disclaimer.
26 * - Redistributions in binary form must reproduce the above copyright
27 * notice, this list of conditions and the following disclaimer in
28 * the documentation and/or other materials provided with the
29 * distribution.
30 * - Neither the name of Intel Corporation nor the names of its
31 * contributors may be used to endorse or promote products derived
32 * from this software without specific prior written permission.
33 *
34 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
35 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
36 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
37 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
38 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
39 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
40 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
41 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
42 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
43 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
44 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
45 *
46 */
47
48 #ifndef _COMMON_H
49 #define _COMMON_H
50
51 #include <rdma/hfi/hfi1_user.h>
52
53 /*
54 * This file contains defines, structures, etc. that are used
55 * to communicate between kernel and user code.
56 */
57
58 /* version of protocol header (known to chip also). In the long run,
59 * we should be able to generate and accept a range of version numbers;
60 * for now we only accept one, and it's compiled in.
61 */
62 #define IPS_PROTO_VERSION 2
63
64 /*
65 * These are compile time constants that you may want to enable or disable
66 * if you are trying to debug problems with code or performance.
67 * HFI1_VERBOSE_TRACING define as 1 if you want additional tracing in
68 * fast path code
69 * HFI1_TRACE_REGWRITES define as 1 if you want register writes to be
70 * traced in fast path code
71 * _HFI1_TRACING define as 0 if you want to remove all tracing in a
72 * compilation unit
73 */
74
75 /* driver/hw feature set bitmask */
76 #define HFI1_CAP_USER_SHIFT 24
77 #define HFI1_CAP_MASK ((1UL << HFI1_CAP_USER_SHIFT) - 1)
78 /* locked flag - if set, only HFI1_CAP_WRITABLE_MASK bits can be set */
79 #define HFI1_CAP_LOCKED_SHIFT 63
80 #define HFI1_CAP_LOCKED_MASK 0x1ULL
81 #define HFI1_CAP_LOCKED_SMASK (HFI1_CAP_LOCKED_MASK << HFI1_CAP_LOCKED_SHIFT)
82 /* extra bits used between kernel and user processes */
83 #define HFI1_CAP_MISC_SHIFT (HFI1_CAP_USER_SHIFT * 2)
84 #define HFI1_CAP_MISC_MASK ((1ULL << (HFI1_CAP_LOCKED_SHIFT - \
85 HFI1_CAP_MISC_SHIFT)) - 1)
86
87 #define HFI1_CAP_KSET(cap) ({ hfi1_cap_mask |= HFI1_CAP_##cap; hfi1_cap_mask; })
88 #define HFI1_CAP_KCLEAR(cap) \
89 ({ \
90 hfi1_cap_mask &= ~HFI1_CAP_##cap; \
91 hfi1_cap_mask; \
92 })
93 #define HFI1_CAP_USET(cap) \
94 ({ \
95 hfi1_cap_mask |= (HFI1_CAP_##cap << HFI1_CAP_USER_SHIFT); \
96 hfi1_cap_mask; \
97 })
98 #define HFI1_CAP_UCLEAR(cap) \
99 ({ \
100 hfi1_cap_mask &= ~(HFI1_CAP_##cap << HFI1_CAP_USER_SHIFT); \
101 hfi1_cap_mask; \
102 })
103 #define HFI1_CAP_SET(cap) \
104 ({ \
105 hfi1_cap_mask |= (HFI1_CAP_##cap | (HFI1_CAP_##cap << \
106 HFI1_CAP_USER_SHIFT)); \
107 hfi1_cap_mask; \
108 })
109 #define HFI1_CAP_CLEAR(cap) \
110 ({ \
111 hfi1_cap_mask &= ~(HFI1_CAP_##cap | \
112 (HFI1_CAP_##cap << HFI1_CAP_USER_SHIFT)); \
113 hfi1_cap_mask; \
114 })
115 #define HFI1_CAP_LOCK() \
116 ({ hfi1_cap_mask |= HFI1_CAP_LOCKED_SMASK; hfi1_cap_mask; })
117 #define HFI1_CAP_LOCKED() (!!(hfi1_cap_mask & HFI1_CAP_LOCKED_SMASK))
118 /*
119 * The set of capability bits that can be changed after initial load
120 * This set is the same for kernel and user contexts. However, for
121 * user contexts, the set can be further filtered by using the
122 * HFI1_CAP_RESERVED_MASK bits.
123 */
124 #define HFI1_CAP_WRITABLE_MASK (HFI1_CAP_SDMA_AHG | \
125 HFI1_CAP_HDRSUPP | \
126 HFI1_CAP_MULTI_PKT_EGR | \
127 HFI1_CAP_NODROP_RHQ_FULL | \
128 HFI1_CAP_NODROP_EGR_FULL | \
129 HFI1_CAP_ALLOW_PERM_JKEY | \
130 HFI1_CAP_STATIC_RATE_CTRL | \
131 HFI1_CAP_PRINT_UNIMPL | \
132 HFI1_CAP_TID_UNMAP | \
133 HFI1_CAP_OPFN)
134 /*
135 * A set of capability bits that are "global" and are not allowed to be
136 * set in the user bitmask.
137 */
138 #define HFI1_CAP_RESERVED_MASK ((HFI1_CAP_SDMA | \
139 HFI1_CAP_USE_SDMA_HEAD | \
140 HFI1_CAP_EXTENDED_PSN | \
141 HFI1_CAP_PRINT_UNIMPL | \
142 HFI1_CAP_NO_INTEGRITY | \
143 HFI1_CAP_PKEY_CHECK | \
144 HFI1_CAP_TID_RDMA | \
145 HFI1_CAP_OPFN | \
146 HFI1_CAP_AIP) << \
147 HFI1_CAP_USER_SHIFT)
148 /*
149 * Set of capabilities that need to be enabled for kernel context in
150 * order to be allowed for user contexts, as well.
151 */
152 #define HFI1_CAP_MUST_HAVE_KERN (HFI1_CAP_STATIC_RATE_CTRL)
153 /* Default enabled capabilities (both kernel and user) */
154 #define HFI1_CAP_MASK_DEFAULT (HFI1_CAP_HDRSUPP | \
155 HFI1_CAP_NODROP_RHQ_FULL | \
156 HFI1_CAP_NODROP_EGR_FULL | \
157 HFI1_CAP_SDMA | \
158 HFI1_CAP_PRINT_UNIMPL | \
159 HFI1_CAP_STATIC_RATE_CTRL | \
160 HFI1_CAP_PKEY_CHECK | \
161 HFI1_CAP_MULTI_PKT_EGR | \
162 HFI1_CAP_EXTENDED_PSN | \
163 HFI1_CAP_AIP | \
164 ((HFI1_CAP_HDRSUPP | \
165 HFI1_CAP_MULTI_PKT_EGR | \
166 HFI1_CAP_STATIC_RATE_CTRL | \
167 HFI1_CAP_PKEY_CHECK | \
168 HFI1_CAP_EARLY_CREDIT_RETURN) << \
169 HFI1_CAP_USER_SHIFT))
170 /*
171 * A bitmask of kernel/global capabilities that should be communicated
172 * to user level processes.
173 */
174 #define HFI1_CAP_K2U (HFI1_CAP_SDMA | \
175 HFI1_CAP_EXTENDED_PSN | \
176 HFI1_CAP_PKEY_CHECK | \
177 HFI1_CAP_NO_INTEGRITY)
178
179 #define HFI1_USER_SWVERSION ((HFI1_USER_SWMAJOR << HFI1_SWMAJOR_SHIFT) | \
180 HFI1_USER_SWMINOR)
181
182 #ifndef HFI1_KERN_TYPE
183 #define HFI1_KERN_TYPE 0
184 #endif
185
186 /*
187 * Similarly, this is the kernel version going back to the user. It's
188 * slightly different, in that we want to tell if the driver was built as
189 * part of a Intel release, or from the driver from openfabrics.org,
190 * kernel.org, or a standard distribution, for support reasons.
191 * The high bit is 0 for non-Intel and 1 for Intel-built/supplied.
192 *
193 * It's returned by the driver to the user code during initialization in the
194 * spi_sw_version field of hfi1_base_info, so the user code can in turn
195 * check for compatibility with the kernel.
196 */
197 #define HFI1_KERN_SWVERSION ((HFI1_KERN_TYPE << 31) | HFI1_USER_SWVERSION)
198
199 /*
200 * Define the driver version number. This is something that refers only
201 * to the driver itself, not the software interfaces it supports.
202 */
203 #ifndef HFI1_DRIVER_VERSION_BASE
204 #define HFI1_DRIVER_VERSION_BASE "0.9-294"
205 #endif
206
207 /* create the final driver version string */
208 #ifdef HFI1_IDSTR
209 #define HFI1_DRIVER_VERSION HFI1_DRIVER_VERSION_BASE " " HFI1_IDSTR
210 #else
211 #define HFI1_DRIVER_VERSION HFI1_DRIVER_VERSION_BASE
212 #endif
213
214 /*
215 * Diagnostics can send a packet by writing the following
216 * struct to the diag packet special file.
217 *
218 * This allows a custom PBC qword, so that special modes and deliberate
219 * changes to CRCs can be used.
220 */
221 #define _DIAG_PKT_VERS 1
222 struct diag_pkt {
223 __u16 version; /* structure version */
224 __u16 unit; /* which device */
225 __u16 sw_index; /* send sw index to use */
226 __u16 len; /* data length, in bytes */
227 __u16 port; /* port number */
228 __u16 unused;
229 __u32 flags; /* call flags */
230 __u64 data; /* user data pointer */
231 __u64 pbc; /* PBC for the packet */
232 };
233
234 /* diag_pkt flags */
235 #define F_DIAGPKT_WAIT 0x1 /* wait until packet is sent */
236
237 /*
238 * The next set of defines are for packet headers, and chip register
239 * and memory bits that are visible to and/or used by user-mode software.
240 */
241
242 /*
243 * Receive Header Flags
244 */
245 #define RHF_PKT_LEN_SHIFT 0
246 #define RHF_PKT_LEN_MASK 0xfffull
247 #define RHF_PKT_LEN_SMASK (RHF_PKT_LEN_MASK << RHF_PKT_LEN_SHIFT)
248
249 #define RHF_RCV_TYPE_SHIFT 12
250 #define RHF_RCV_TYPE_MASK 0x7ull
251 #define RHF_RCV_TYPE_SMASK (RHF_RCV_TYPE_MASK << RHF_RCV_TYPE_SHIFT)
252
253 #define RHF_USE_EGR_BFR_SHIFT 15
254 #define RHF_USE_EGR_BFR_MASK 0x1ull
255 #define RHF_USE_EGR_BFR_SMASK (RHF_USE_EGR_BFR_MASK << RHF_USE_EGR_BFR_SHIFT)
256
257 #define RHF_EGR_INDEX_SHIFT 16
258 #define RHF_EGR_INDEX_MASK 0x7ffull
259 #define RHF_EGR_INDEX_SMASK (RHF_EGR_INDEX_MASK << RHF_EGR_INDEX_SHIFT)
260
261 #define RHF_DC_INFO_SHIFT 27
262 #define RHF_DC_INFO_MASK 0x1ull
263 #define RHF_DC_INFO_SMASK (RHF_DC_INFO_MASK << RHF_DC_INFO_SHIFT)
264
265 #define RHF_RCV_SEQ_SHIFT 28
266 #define RHF_RCV_SEQ_MASK 0xfull
267 #define RHF_RCV_SEQ_SMASK (RHF_RCV_SEQ_MASK << RHF_RCV_SEQ_SHIFT)
268
269 #define RHF_EGR_OFFSET_SHIFT 32
270 #define RHF_EGR_OFFSET_MASK 0xfffull
271 #define RHF_EGR_OFFSET_SMASK (RHF_EGR_OFFSET_MASK << RHF_EGR_OFFSET_SHIFT)
272 #define RHF_HDRQ_OFFSET_SHIFT 44
273 #define RHF_HDRQ_OFFSET_MASK 0x1ffull
274 #define RHF_HDRQ_OFFSET_SMASK (RHF_HDRQ_OFFSET_MASK << RHF_HDRQ_OFFSET_SHIFT)
275 #define RHF_K_HDR_LEN_ERR (0x1ull << 53)
276 #define RHF_DC_UNC_ERR (0x1ull << 54)
277 #define RHF_DC_ERR (0x1ull << 55)
278 #define RHF_RCV_TYPE_ERR_SHIFT 56
279 #define RHF_RCV_TYPE_ERR_MASK 0x7ul
280 #define RHF_RCV_TYPE_ERR_SMASK (RHF_RCV_TYPE_ERR_MASK << RHF_RCV_TYPE_ERR_SHIFT)
281 #define RHF_TID_ERR (0x1ull << 59)
282 #define RHF_LEN_ERR (0x1ull << 60)
283 #define RHF_ECC_ERR (0x1ull << 61)
284 #define RHF_RESERVED (0x1ull << 62)
285 #define RHF_ICRC_ERR (0x1ull << 63)
286
287 #define RHF_ERROR_SMASK 0xffe0000000000000ull /* bits 63:53 */
288
289 /* RHF receive types */
290 #define RHF_RCV_TYPE_EXPECTED 0
291 #define RHF_RCV_TYPE_EAGER 1
292 #define RHF_RCV_TYPE_IB 2 /* normal IB, IB Raw, or IPv6 */
293 #define RHF_RCV_TYPE_ERROR 3
294 #define RHF_RCV_TYPE_BYPASS 4
295 #define RHF_RCV_TYPE_INVALID5 5
296 #define RHF_RCV_TYPE_INVALID6 6
297 #define RHF_RCV_TYPE_INVALID7 7
298
299 /* RHF receive type error - expected packet errors */
300 #define RHF_RTE_EXPECTED_FLOW_SEQ_ERR 0x2
301 #define RHF_RTE_EXPECTED_FLOW_GEN_ERR 0x4
302
303 /* RHF receive type error - eager packet errors */
304 #define RHF_RTE_EAGER_NO_ERR 0x0
305
306 /* RHF receive type error - IB packet errors */
307 #define RHF_RTE_IB_NO_ERR 0x0
308
309 /* RHF receive type error - error packet errors */
310 #define RHF_RTE_ERROR_NO_ERR 0x0
311 #define RHF_RTE_ERROR_OP_CODE_ERR 0x1
312 #define RHF_RTE_ERROR_KHDR_MIN_LEN_ERR 0x2
313 #define RHF_RTE_ERROR_KHDR_HCRC_ERR 0x3
314 #define RHF_RTE_ERROR_KHDR_KVER_ERR 0x4
315 #define RHF_RTE_ERROR_CONTEXT_ERR 0x5
316 #define RHF_RTE_ERROR_KHDR_TID_ERR 0x6
317
318 /* RHF receive type error - bypass packet errors */
319 #define RHF_RTE_BYPASS_NO_ERR 0x0
320
321 /* MAX RcvSEQ */
322 #define RHF_MAX_SEQ 13
323
324 /* IB - LRH header constants */
325 #define HFI1_LRH_GRH 0x0003 /* 1. word of IB LRH - next header: GRH */
326 #define HFI1_LRH_BTH 0x0002 /* 1. word of IB LRH - next header: BTH */
327
328 /* misc. */
329 #define SC15_PACKET 0xF
330 #define SIZE_OF_CRC 1
331 #define SIZE_OF_LT 1
332 #define MAX_16B_PADDING 12 /* CRC = 4, LT = 1, Pad = 0 to 7 bytes */
333
334 #define LIM_MGMT_P_KEY 0x7FFF
335 #define FULL_MGMT_P_KEY 0xFFFF
336
337 #define DEFAULT_P_KEY LIM_MGMT_P_KEY
338
339 #define HFI1_PSM_IOC_BASE_SEQ 0x0
340
341 /* Number of BTH.PSN bits used for sequence number in expected rcvs */
342 #define HFI1_KDETH_BTH_SEQ_SHIFT 11
343 #define HFI1_KDETH_BTH_SEQ_MASK (BIT(HFI1_KDETH_BTH_SEQ_SHIFT) - 1)
344
rhf_to_cpu(const __le32 * rbuf)345 static inline __u64 rhf_to_cpu(const __le32 *rbuf)
346 {
347 return __le64_to_cpu(*((__le64 *)rbuf));
348 }
349
rhf_err_flags(u64 rhf)350 static inline u64 rhf_err_flags(u64 rhf)
351 {
352 return rhf & RHF_ERROR_SMASK;
353 }
354
rhf_rcv_type(u64 rhf)355 static inline u32 rhf_rcv_type(u64 rhf)
356 {
357 return (rhf >> RHF_RCV_TYPE_SHIFT) & RHF_RCV_TYPE_MASK;
358 }
359
rhf_rcv_type_err(u64 rhf)360 static inline u32 rhf_rcv_type_err(u64 rhf)
361 {
362 return (rhf >> RHF_RCV_TYPE_ERR_SHIFT) & RHF_RCV_TYPE_ERR_MASK;
363 }
364
365 /* return size is in bytes, not DWORDs */
rhf_pkt_len(u64 rhf)366 static inline u32 rhf_pkt_len(u64 rhf)
367 {
368 return ((rhf & RHF_PKT_LEN_SMASK) >> RHF_PKT_LEN_SHIFT) << 2;
369 }
370
rhf_egr_index(u64 rhf)371 static inline u32 rhf_egr_index(u64 rhf)
372 {
373 return (rhf >> RHF_EGR_INDEX_SHIFT) & RHF_EGR_INDEX_MASK;
374 }
375
rhf_rcv_seq(u64 rhf)376 static inline u32 rhf_rcv_seq(u64 rhf)
377 {
378 return (rhf >> RHF_RCV_SEQ_SHIFT) & RHF_RCV_SEQ_MASK;
379 }
380
381 /* returned offset is in DWORDS */
rhf_hdrq_offset(u64 rhf)382 static inline u32 rhf_hdrq_offset(u64 rhf)
383 {
384 return (rhf >> RHF_HDRQ_OFFSET_SHIFT) & RHF_HDRQ_OFFSET_MASK;
385 }
386
rhf_use_egr_bfr(u64 rhf)387 static inline u64 rhf_use_egr_bfr(u64 rhf)
388 {
389 return rhf & RHF_USE_EGR_BFR_SMASK;
390 }
391
rhf_dc_info(u64 rhf)392 static inline u64 rhf_dc_info(u64 rhf)
393 {
394 return rhf & RHF_DC_INFO_SMASK;
395 }
396
rhf_egr_buf_offset(u64 rhf)397 static inline u32 rhf_egr_buf_offset(u64 rhf)
398 {
399 return (rhf >> RHF_EGR_OFFSET_SHIFT) & RHF_EGR_OFFSET_MASK;
400 }
401 #endif /* _COMMON_H */
402
