Searched refs:REG_DSI_7nm_PHY_CMN_CLK_CFG1 (Results 1 – 2 of 2) sorted by relevance
406 data = pll_read(pll->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_CLK_CFG1); in dsi_pll_disable_global_clk()407 pll_write(pll->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_CLK_CFG1, data & ~BIT(5)); in dsi_pll_disable_global_clk()416 data = pll_read(pll->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_CLK_CFG1); in dsi_pll_enable_global_clk()417 pll_write(pll->phy_cmn_mmio + REG_DSI_7nm_PHY_CMN_CLK_CFG1, in dsi_pll_enable_global_clk()574 cmn_clk_cfg1 = pll_read(phy_base + REG_DSI_7nm_PHY_CMN_CLK_CFG1); in dsi_pll_7nm_save_state()597 val = pll_read(phy_base + REG_DSI_7nm_PHY_CMN_CLK_CFG1); in dsi_pll_7nm_restore_state()600 pll_write(phy_base + REG_DSI_7nm_PHY_CMN_CLK_CFG1, val); in dsi_pll_7nm_restore_state()630 pll_write(base + REG_DSI_7nm_PHY_CMN_CLK_CFG1, (data << 2)); in dsi_pll_7nm_set_usecase()789 REG_DSI_7nm_PHY_CMN_CLK_CFG1, in pll_7nm_register()
1899 #define REG_DSI_7nm_PHY_CMN_CLK_CFG1 0x00000014 macro
