Searched refs:REG_DSI_28nm_PHY_PLL_PWRGEN_CFG (Results 1 – 2 of 2) sorted by relevance
228 pll_write(base + REG_DSI_28nm_PHY_PLL_PWRGEN_CFG, 0x00); in dsi_pll_28nm_clk_set_rate()
1152 #define REG_DSI_28nm_PHY_PLL_PWRGEN_CFG 0x00000014 macro
