Searched refs:REG_DSI_28nm_PHY_PLL_CAL_CFG10 (Results 1 – 2 of 2) sorted by relevance
236 pll_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG10, cal_cfg10 & 0xff); in dsi_pll_28nm_clk_set_rate()
1252 #define REG_DSI_28nm_PHY_PLL_CAL_CFG10 0x00000094 macro
