Searched refs:REG_DSI_28nm_PHY_PLL_CAL_CFG0 (Results 1 – 2 of 2) sorted by relevance
231 pll_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG0, 0x12); in dsi_pll_28nm_clk_set_rate()
1232 #define REG_DSI_28nm_PHY_PLL_CAL_CFG0 0x0000006c macro
