Searched refs:REG_DSI_28nm_8960_PHY_PLL_CTRL_3 (Results 1 – 2 of 2) sorted by relevance
133 val = pll_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_3); in dsi_pll_28nm_clk_set_rate()137 pll_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_3, in dsi_pll_28nm_clk_set_rate()180 ref_divider = pll_read(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_3); in dsi_pll_28nm_clk_recalc_rate()
921 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_3 0x0000000c macro
