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Searched refs:REG_BIT (Results 1 – 3 of 3) sorted by relevance

/Linux-v5.10/drivers/gpu/drm/i915/gt/
Dintel_gpu_commands.h141 #define MI_LRI_LRM_CS_MMIO REG_BIT(19)
159 #define MI_LRR_SOURCE_CS_MMIO REG_BIT(18)
169 #define MI_BATCH_RESOURCE_STREAMER REG_BIT(10)
170 #define MI_BATCH_PREDICATE REG_BIT(15) /* HSW+ on RCS only*/
240 #define PIPE_CONTROL0_HDC_PIPELINE_FLUSH REG_BIT(9) /* gen12 */
297 #define BASE_ADDRESS_MODIFY REG_BIT(0)
300 #define PIPELINE_SELECT_MEDIA REG_BIT(0)
Dintel_gtt.h74 #define GEN6_PTE_VALID REG_BIT(0)
80 #define GEN6_PDE_VALID REG_BIT(0)
85 #define BYT_PTE_SNOOPED_BY_CPU_CACHES REG_BIT(2)
86 #define BYT_PTE_WRITEABLE REG_BIT(1)
122 #define CHV_PPAT_SNOOP REG_BIT(6)
/Linux-v5.10/drivers/gpu/drm/i915/
Di915_reg.h127 #define REG_BIT(__n) \ macro
564 #define BCS_SRC_Y REG_BIT(0)
565 #define BCS_DST_Y REG_BIT(1)
2083 #define ICL_PORT_TX_DW8_ODCC_CLK_SEL REG_BIT(31)
2089 #define ICL_DPHY_CHKN_AFE_OVER_PPI_STRAP REG_BIT(7)
2534 #define RESET_CTL_CAT_ERROR REG_BIT(2)
2535 #define RESET_CTL_READY_TO_RESET REG_BIT(1)
2536 #define RESET_CTL_REQUEST_RESET REG_BIT(0)
2581 #define AUX_INV REG_BIT(0)
2927 #define HDPORT_PHY_USED_DP(phy) REG_BIT(2 * (phy) + 2)
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