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Searched refs:RALINK_PCIEPHY_P0_CTL_OFFSET (Results 1 – 1 of 1) sorted by relevance

/Linux-v5.10/arch/mips/pci/
Dpci-mt7620.c64 #define RALINK_PCIEPHY_P0_CTL_OFFSET 0x7498 macro
269 pcie_m32(~0xff, 0x5, RALINK_PCIEPHY_P0_CTL_OFFSET); in mt7628_pci_hw_init()