Searched refs:RADEON_TILING_MACRO (Results 1 – 10 of 10) sorted by relevance
221 if (reloc->tiling_flags & RADEON_TILING_MACRO) in r200_packet0_check()293 if (reloc->tiling_flags & RADEON_TILING_MACRO) in r200_packet0_check()
161 tiling_flags = RADEON_TILING_MACRO; in radeonfb_create_pinned_object()
1283 if (reloc->tiling_flags & RADEON_TILING_MACRO) in r100_reloc_pitch_offset()1625 if (reloc->tiling_flags & RADEON_TILING_MACRO) in r100_packet0_check()1706 if (reloc->tiling_flags & RADEON_TILING_MACRO) in r100_packet0_check()3101 if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO)) in r100_set_surface_reg()3102 == (RADEON_TILING_MACRO|RADEON_TILING_MICRO)) in r100_set_surface_reg()3104 if (tiling_flags & RADEON_TILING_MACRO) in r100_set_surface_reg()3107 if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO)) in r100_set_surface_reg()3111 if (tiling_flags & (RADEON_TILING_MACRO)) in r100_set_surface_reg()3116 if (tiling_flags & RADEON_TILING_MACRO) in r100_set_surface_reg()
483 if (tiling_flags & RADEON_TILING_MACRO) { in radeon_crtc_do_set_base()499 if (tiling_flags & RADEON_TILING_MACRO) { in radeon_crtc_do_set_base()
723 if (reloc->tiling_flags & RADEON_TILING_MACRO) in r300_packet0_check()792 if (reloc->tiling_flags & RADEON_TILING_MACRO) in r300_packet0_check()877 if (reloc->tiling_flags & RADEON_TILING_MACRO) in r300_packet0_check()
1042 if (reloc->tiling_flags & RADEON_TILING_MACRO) { in r600_cs_check_reg()1141 if (reloc->tiling_flags & RADEON_TILING_MACRO) { in r600_cs_check_reg()1494 if (tiling_flags & RADEON_TILING_MACRO) in r600_check_texture_resource()1965 if (reloc->tiling_flags & RADEON_TILING_MACRO) in r600_packet3_check()
95 if (tiling_flags & RADEON_TILING_MACRO) in evergreen_cs_get_aray_mode()1182 if (reloc->tiling_flags & RADEON_TILING_MACRO) { in evergreen_cs_handle_reg()1446 if (reloc->tiling_flags & RADEON_TILING_MACRO) { in evergreen_cs_handle_reg()1474 if (reloc->tiling_flags & RADEON_TILING_MACRO) { in evergreen_cs_handle_reg()2363 if (reloc->tiling_flags & RADEON_TILING_MACRO) { in evergreen_packet3_check()
1275 if (tiling_flags & RADEON_TILING_MACRO) { in dce4_crtc_do_set_base()1588 if (tiling_flags & RADEON_TILING_MACRO) in avivo_crtc_do_set_base()1593 if (tiling_flags & RADEON_TILING_MACRO) in avivo_crtc_do_set_base()
551 if (tiling_flags & RADEON_TILING_MACRO) { in radeon_crtc_page_flip_target()
838 #define RADEON_TILING_MACRO 0x1 macro