Searched refs:RADEON_SCLK_CNTL (Results 1 – 2 of 2) sorted by relevance
58 post_div = RREG32_PLL(RADEON_SCLK_CNTL) & RADEON_SCLK_SRC_SEL_MASK; in radeon_legacy_get_engine_clock()404 tmp = RREG32_PLL(RADEON_SCLK_CNTL); in radeon_legacy_set_engine_clock()406 WREG32_PLL(RADEON_SCLK_CNTL, tmp); in radeon_legacy_set_engine_clock()448 tmp = RREG32_PLL(RADEON_SCLK_CNTL); in radeon_legacy_set_engine_clock()465 WREG32_PLL(RADEON_SCLK_CNTL, tmp); in radeon_legacy_set_engine_clock()482 tmp = RREG32_PLL(RADEON_SCLK_CNTL); in radeon_legacy_set_clock_gating()496 WREG32_PLL(RADEON_SCLK_CNTL, tmp); in radeon_legacy_set_clock_gating()500 tmp = RREG32_PLL(RADEON_SCLK_CNTL); in radeon_legacy_set_clock_gating()519 WREG32_PLL(RADEON_SCLK_CNTL, tmp); in radeon_legacy_set_clock_gating()556 tmp = RREG32_PLL(RADEON_SCLK_CNTL); in radeon_legacy_set_clock_gating()[all …]
1663 #define RADEON_SCLK_CNTL 0x000d /* PLL */ macro
