| /Linux-v5.10/drivers/gpu/drm/amd/pm/inc/ |
| D | smu9_driver_if.h | 237 uint8_t PcieLaneCount[NUM_LINK_LEVELS]; /* 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16 */ member
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| D | smu7_discrete.h | 212 uint8_t PcieLaneCount; member
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| D | smu71_discrete.h | 154 uint8_t PcieLaneCount; ///< 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16 member
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| D | smu72_discrete.h | 145 uint8_t PcieLaneCount; /*< 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16 */ member
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| D | smu73_discrete.h | 130 uint8_t PcieLaneCount; ///< 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16 member
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| D | smu11_driver_if.h | 453 uint8_t PcieLaneCount[NUM_LINK_LEVELS]; member
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| D | smu74_discrete.h | 158 uint8_t PcieLaneCount; member
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| D | smu75_discrete.h | 168 uint8_t PcieLaneCount; member
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| D | smu11_driver_if_navi10.h | 626 uint8_t PcieLaneCount[NUM_LINK_LEVELS]; ///< 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16 member
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| D | smu11_driver_if_sienna_cichlid.h | 729 uint8_t PcieLaneCount[NUM_LINK_LEVELS]; ///< 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16 member
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| /Linux-v5.10/drivers/gpu/drm/radeon/ |
| D | smu7_discrete.h | 212 uint8_t PcieLaneCount; member
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| D | ci_dpm.c | 2621 table->LinkLevel[i].PcieLaneCount = in ci_populate_smc_link_level()
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| /Linux-v5.10/drivers/gpu/drm/amd/pm/inc/vega12/ |
| D | smu9_driver_if.h | 341 uint8_t PcieLaneCount[NUM_LINK_LEVELS]; member
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| /Linux-v5.10/drivers/gpu/drm/amd/pm/swsmu/smu11/ |
| D | navi10_ppt.c | 1871 dpm_context->dpm_tables.pcie_table.pcie_lane[i] = pptable->PcieLaneCount[i]; in navi10_update_pcie_parameters()
1877 (pcie_gen_cap << 8)) | ((pptable->PcieLaneCount[i] <= pcie_width_cap) ? in navi10_update_pcie_parameters()
1878 pptable->PcieLaneCount[i] : pcie_width_cap); in navi10_update_pcie_parameters()
1889 if (pptable->PcieLaneCount[i] > pcie_width_cap) in navi10_update_pcie_parameters()
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| D | sienna_cichlid_ppt.c | 1684 dpm_context->dpm_tables.pcie_table.pcie_lane[i] = pptable->PcieLaneCount[i]; in sienna_cichlid_update_pcie_parameters()
1692 ((pptable->PcieLaneCount[i] <= pcie_width_cap) ? in sienna_cichlid_update_pcie_parameters()
1693 pptable->PcieLaneCount[i] : in sienna_cichlid_update_pcie_parameters()
1706 if (pptable->PcieLaneCount[i] > pcie_width_cap) in sienna_cichlid_update_pcie_parameters()
2153 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->PcieLaneCount[i]); in sienna_cichlid_dump_pptable()
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| /Linux-v5.10/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ |
| D | vega20_processpptables.c | 404 pr_info(" .[%d] = %d\n", i, pptable->PcieLaneCount[i]);
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| D | vega10_hwmgr.c | 1520 pp_table->PcieLaneCount[i] = pcie_table->pcie_lane[i]; in vega10_populate_smc_link_levels()
1533 pp_table->PcieLaneCount[i] = pcie_table->pcie_lane[j]; in vega10_populate_smc_link_levels()
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| D | vega20_hwmgr.c | 3429 lane_width = pptable->PcieLaneCount[i]; in vega20_print_clock_levels()
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| /Linux-v5.10/drivers/gpu/drm/amd/pm/powerplay/smumgr/ |
| D | vegam_smumgr.c | 583 table->LinkLevel[i].PcieLaneCount = (uint8_t)encode_pcie_lane_width( in vegam_populate_smc_link_level()
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| D | fiji_smumgr.c | 840 table->LinkLevel[i].PcieLaneCount = (uint8_t)encode_pcie_lane_width( in fiji_populate_smc_link_level()
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| D | iceland_smumgr.c | 775 table->LinkLevel[i].PcieLaneCount = in iceland_populate_smc_link_level()
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| D | polaris10_smumgr.c | 780 table->LinkLevel[i].PcieLaneCount = (uint8_t)encode_pcie_lane_width( in polaris10_populate_smc_link_level()
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| D | ci_smumgr.c | 1007 table->LinkLevel[i].PcieLaneCount = in ci_populate_smc_link_level()
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| D | tonga_smumgr.c | 518 table->LinkLevel[i].PcieLaneCount = in tonga_populate_smc_link_level()
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