1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Driver for Allwinner sun4i Pulse Width Modulation Controller
4 *
5 * Copyright (C) 2014 Alexandre Belloni <alexandre.belloni@free-electrons.com>
6 *
7 * Limitations:
8 * - When outputing the source clock directly, the PWM logic will be bypassed
9 * and the currently running period is not guaranteed to be completed
10 */
11
12 #include <linux/bitops.h>
13 #include <linux/clk.h>
14 #include <linux/delay.h>
15 #include <linux/err.h>
16 #include <linux/io.h>
17 #include <linux/jiffies.h>
18 #include <linux/module.h>
19 #include <linux/of.h>
20 #include <linux/of_device.h>
21 #include <linux/platform_device.h>
22 #include <linux/pwm.h>
23 #include <linux/reset.h>
24 #include <linux/slab.h>
25 #include <linux/spinlock.h>
26 #include <linux/time.h>
27
28 #define PWM_CTRL_REG 0x0
29
30 #define PWM_CH_PRD_BASE 0x4
31 #define PWM_CH_PRD_OFFSET 0x4
32 #define PWM_CH_PRD(ch) (PWM_CH_PRD_BASE + PWM_CH_PRD_OFFSET * (ch))
33
34 #define PWMCH_OFFSET 15
35 #define PWM_PRESCAL_MASK GENMASK(3, 0)
36 #define PWM_PRESCAL_OFF 0
37 #define PWM_EN BIT(4)
38 #define PWM_ACT_STATE BIT(5)
39 #define PWM_CLK_GATING BIT(6)
40 #define PWM_MODE BIT(7)
41 #define PWM_PULSE BIT(8)
42 #define PWM_BYPASS BIT(9)
43
44 #define PWM_RDY_BASE 28
45 #define PWM_RDY_OFFSET 1
46 #define PWM_RDY(ch) BIT(PWM_RDY_BASE + PWM_RDY_OFFSET * (ch))
47
48 #define PWM_PRD(prd) (((prd) - 1) << 16)
49 #define PWM_PRD_MASK GENMASK(15, 0)
50
51 #define PWM_DTY_MASK GENMASK(15, 0)
52
53 #define PWM_REG_PRD(reg) ((((reg) >> 16) & PWM_PRD_MASK) + 1)
54 #define PWM_REG_DTY(reg) ((reg) & PWM_DTY_MASK)
55 #define PWM_REG_PRESCAL(reg, chan) (((reg) >> ((chan) * PWMCH_OFFSET)) & PWM_PRESCAL_MASK)
56
57 #define BIT_CH(bit, chan) ((bit) << ((chan) * PWMCH_OFFSET))
58
59 static const u32 prescaler_table[] = {
60 120,
61 180,
62 240,
63 360,
64 480,
65 0,
66 0,
67 0,
68 12000,
69 24000,
70 36000,
71 48000,
72 72000,
73 0,
74 0,
75 0, /* Actually 1 but tested separately */
76 };
77
78 struct sun4i_pwm_data {
79 bool has_prescaler_bypass;
80 bool has_direct_mod_clk_output;
81 unsigned int npwm;
82 };
83
84 struct sun4i_pwm_chip {
85 struct pwm_chip chip;
86 struct clk *bus_clk;
87 struct clk *clk;
88 struct reset_control *rst;
89 void __iomem *base;
90 spinlock_t ctrl_lock;
91 const struct sun4i_pwm_data *data;
92 unsigned long next_period[2];
93 };
94
to_sun4i_pwm_chip(struct pwm_chip * chip)95 static inline struct sun4i_pwm_chip *to_sun4i_pwm_chip(struct pwm_chip *chip)
96 {
97 return container_of(chip, struct sun4i_pwm_chip, chip);
98 }
99
sun4i_pwm_readl(struct sun4i_pwm_chip * chip,unsigned long offset)100 static inline u32 sun4i_pwm_readl(struct sun4i_pwm_chip *chip,
101 unsigned long offset)
102 {
103 return readl(chip->base + offset);
104 }
105
sun4i_pwm_writel(struct sun4i_pwm_chip * chip,u32 val,unsigned long offset)106 static inline void sun4i_pwm_writel(struct sun4i_pwm_chip *chip,
107 u32 val, unsigned long offset)
108 {
109 writel(val, chip->base + offset);
110 }
111
sun4i_pwm_get_state(struct pwm_chip * chip,struct pwm_device * pwm,struct pwm_state * state)112 static void sun4i_pwm_get_state(struct pwm_chip *chip,
113 struct pwm_device *pwm,
114 struct pwm_state *state)
115 {
116 struct sun4i_pwm_chip *sun4i_pwm = to_sun4i_pwm_chip(chip);
117 u64 clk_rate, tmp;
118 u32 val;
119 unsigned int prescaler;
120
121 clk_rate = clk_get_rate(sun4i_pwm->clk);
122
123 val = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);
124
125 /*
126 * PWM chapter in H6 manual has a diagram which explains that if bypass
127 * bit is set, no other setting has any meaning. Even more, experiment
128 * proved that also enable bit is ignored in this case.
129 */
130 if ((val & BIT_CH(PWM_BYPASS, pwm->hwpwm)) &&
131 sun4i_pwm->data->has_direct_mod_clk_output) {
132 state->period = DIV_ROUND_UP_ULL(NSEC_PER_SEC, clk_rate);
133 state->duty_cycle = DIV_ROUND_UP_ULL(state->period, 2);
134 state->polarity = PWM_POLARITY_NORMAL;
135 state->enabled = true;
136 return;
137 }
138
139 if ((PWM_REG_PRESCAL(val, pwm->hwpwm) == PWM_PRESCAL_MASK) &&
140 sun4i_pwm->data->has_prescaler_bypass)
141 prescaler = 1;
142 else
143 prescaler = prescaler_table[PWM_REG_PRESCAL(val, pwm->hwpwm)];
144
145 if (prescaler == 0)
146 return;
147
148 if (val & BIT_CH(PWM_ACT_STATE, pwm->hwpwm))
149 state->polarity = PWM_POLARITY_NORMAL;
150 else
151 state->polarity = PWM_POLARITY_INVERSED;
152
153 if ((val & BIT_CH(PWM_CLK_GATING | PWM_EN, pwm->hwpwm)) ==
154 BIT_CH(PWM_CLK_GATING | PWM_EN, pwm->hwpwm))
155 state->enabled = true;
156 else
157 state->enabled = false;
158
159 val = sun4i_pwm_readl(sun4i_pwm, PWM_CH_PRD(pwm->hwpwm));
160
161 tmp = (u64)prescaler * NSEC_PER_SEC * PWM_REG_DTY(val);
162 state->duty_cycle = DIV_ROUND_CLOSEST_ULL(tmp, clk_rate);
163
164 tmp = (u64)prescaler * NSEC_PER_SEC * PWM_REG_PRD(val);
165 state->period = DIV_ROUND_CLOSEST_ULL(tmp, clk_rate);
166 }
167
sun4i_pwm_calculate(struct sun4i_pwm_chip * sun4i_pwm,const struct pwm_state * state,u32 * dty,u32 * prd,unsigned int * prsclr,bool * bypass)168 static int sun4i_pwm_calculate(struct sun4i_pwm_chip *sun4i_pwm,
169 const struct pwm_state *state,
170 u32 *dty, u32 *prd, unsigned int *prsclr,
171 bool *bypass)
172 {
173 u64 clk_rate, div = 0;
174 unsigned int prescaler = 0;
175
176 clk_rate = clk_get_rate(sun4i_pwm->clk);
177
178 *bypass = sun4i_pwm->data->has_direct_mod_clk_output &&
179 state->enabled &&
180 (state->period * clk_rate >= NSEC_PER_SEC) &&
181 (state->period * clk_rate < 2 * NSEC_PER_SEC) &&
182 (state->duty_cycle * clk_rate * 2 >= NSEC_PER_SEC);
183
184 /* Skip calculation of other parameters if we bypass them */
185 if (*bypass)
186 return 0;
187
188 if (sun4i_pwm->data->has_prescaler_bypass) {
189 /* First, test without any prescaler when available */
190 prescaler = PWM_PRESCAL_MASK;
191 /*
192 * When not using any prescaler, the clock period in nanoseconds
193 * is not an integer so round it half up instead of
194 * truncating to get less surprising values.
195 */
196 div = clk_rate * state->period + NSEC_PER_SEC / 2;
197 do_div(div, NSEC_PER_SEC);
198 if (div - 1 > PWM_PRD_MASK)
199 prescaler = 0;
200 }
201
202 if (prescaler == 0) {
203 /* Go up from the first divider */
204 for (prescaler = 0; prescaler < PWM_PRESCAL_MASK; prescaler++) {
205 unsigned int pval = prescaler_table[prescaler];
206
207 if (!pval)
208 continue;
209
210 div = clk_rate;
211 do_div(div, pval);
212 div = div * state->period;
213 do_div(div, NSEC_PER_SEC);
214 if (div - 1 <= PWM_PRD_MASK)
215 break;
216 }
217
218 if (div - 1 > PWM_PRD_MASK)
219 return -EINVAL;
220 }
221
222 *prd = div;
223 div *= state->duty_cycle;
224 do_div(div, state->period);
225 *dty = div;
226 *prsclr = prescaler;
227
228 return 0;
229 }
230
sun4i_pwm_apply(struct pwm_chip * chip,struct pwm_device * pwm,const struct pwm_state * state)231 static int sun4i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
232 const struct pwm_state *state)
233 {
234 struct sun4i_pwm_chip *sun4i_pwm = to_sun4i_pwm_chip(chip);
235 struct pwm_state cstate;
236 u32 ctrl, duty = 0, period = 0, val;
237 int ret;
238 unsigned int delay_us, prescaler = 0;
239 unsigned long now;
240 bool bypass;
241
242 pwm_get_state(pwm, &cstate);
243
244 if (!cstate.enabled) {
245 ret = clk_prepare_enable(sun4i_pwm->clk);
246 if (ret) {
247 dev_err(chip->dev, "failed to enable PWM clock\n");
248 return ret;
249 }
250 }
251
252 ret = sun4i_pwm_calculate(sun4i_pwm, state, &duty, &period, &prescaler,
253 &bypass);
254 if (ret) {
255 dev_err(chip->dev, "period exceeds the maximum value\n");
256 if (!cstate.enabled)
257 clk_disable_unprepare(sun4i_pwm->clk);
258 return ret;
259 }
260
261 spin_lock(&sun4i_pwm->ctrl_lock);
262 ctrl = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);
263
264 if (sun4i_pwm->data->has_direct_mod_clk_output) {
265 if (bypass) {
266 ctrl |= BIT_CH(PWM_BYPASS, pwm->hwpwm);
267 /* We can skip other parameter */
268 sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG);
269 spin_unlock(&sun4i_pwm->ctrl_lock);
270 return 0;
271 }
272
273 ctrl &= ~BIT_CH(PWM_BYPASS, pwm->hwpwm);
274 }
275
276 if (PWM_REG_PRESCAL(ctrl, pwm->hwpwm) != prescaler) {
277 /* Prescaler changed, the clock has to be gated */
278 ctrl &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
279 sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG);
280
281 ctrl &= ~BIT_CH(PWM_PRESCAL_MASK, pwm->hwpwm);
282 ctrl |= BIT_CH(prescaler, pwm->hwpwm);
283 }
284
285 val = (duty & PWM_DTY_MASK) | PWM_PRD(period);
286 sun4i_pwm_writel(sun4i_pwm, val, PWM_CH_PRD(pwm->hwpwm));
287 sun4i_pwm->next_period[pwm->hwpwm] = jiffies +
288 nsecs_to_jiffies(cstate.period + 1000);
289
290 if (state->polarity != PWM_POLARITY_NORMAL)
291 ctrl &= ~BIT_CH(PWM_ACT_STATE, pwm->hwpwm);
292 else
293 ctrl |= BIT_CH(PWM_ACT_STATE, pwm->hwpwm);
294
295 ctrl |= BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
296
297 if (state->enabled) {
298 ctrl |= BIT_CH(PWM_EN, pwm->hwpwm);
299 } else {
300 ctrl &= ~BIT_CH(PWM_EN, pwm->hwpwm);
301 ctrl &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
302 }
303
304 sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG);
305
306 spin_unlock(&sun4i_pwm->ctrl_lock);
307
308 if (state->enabled)
309 return 0;
310
311 /* We need a full period to elapse before disabling the channel. */
312 now = jiffies;
313 if (time_before(now, sun4i_pwm->next_period[pwm->hwpwm])) {
314 delay_us = jiffies_to_usecs(sun4i_pwm->next_period[pwm->hwpwm] -
315 now);
316 if ((delay_us / 500) > MAX_UDELAY_MS)
317 msleep(delay_us / 1000 + 1);
318 else
319 usleep_range(delay_us, delay_us * 2);
320 }
321
322 spin_lock(&sun4i_pwm->ctrl_lock);
323 ctrl = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);
324 ctrl &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
325 ctrl &= ~BIT_CH(PWM_EN, pwm->hwpwm);
326 sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG);
327 spin_unlock(&sun4i_pwm->ctrl_lock);
328
329 clk_disable_unprepare(sun4i_pwm->clk);
330
331 return 0;
332 }
333
334 static const struct pwm_ops sun4i_pwm_ops = {
335 .apply = sun4i_pwm_apply,
336 .get_state = sun4i_pwm_get_state,
337 .owner = THIS_MODULE,
338 };
339
340 static const struct sun4i_pwm_data sun4i_pwm_dual_nobypass = {
341 .has_prescaler_bypass = false,
342 .npwm = 2,
343 };
344
345 static const struct sun4i_pwm_data sun4i_pwm_dual_bypass = {
346 .has_prescaler_bypass = true,
347 .npwm = 2,
348 };
349
350 static const struct sun4i_pwm_data sun4i_pwm_single_bypass = {
351 .has_prescaler_bypass = true,
352 .npwm = 1,
353 };
354
355 static const struct sun4i_pwm_data sun50i_a64_pwm_data = {
356 .has_prescaler_bypass = true,
357 .has_direct_mod_clk_output = true,
358 .npwm = 1,
359 };
360
361 static const struct sun4i_pwm_data sun50i_h6_pwm_data = {
362 .has_prescaler_bypass = true,
363 .has_direct_mod_clk_output = true,
364 .npwm = 2,
365 };
366
367 static const struct of_device_id sun4i_pwm_dt_ids[] = {
368 {
369 .compatible = "allwinner,sun4i-a10-pwm",
370 .data = &sun4i_pwm_dual_nobypass,
371 }, {
372 .compatible = "allwinner,sun5i-a10s-pwm",
373 .data = &sun4i_pwm_dual_bypass,
374 }, {
375 .compatible = "allwinner,sun5i-a13-pwm",
376 .data = &sun4i_pwm_single_bypass,
377 }, {
378 .compatible = "allwinner,sun7i-a20-pwm",
379 .data = &sun4i_pwm_dual_bypass,
380 }, {
381 .compatible = "allwinner,sun8i-h3-pwm",
382 .data = &sun4i_pwm_single_bypass,
383 }, {
384 .compatible = "allwinner,sun50i-a64-pwm",
385 .data = &sun50i_a64_pwm_data,
386 }, {
387 .compatible = "allwinner,sun50i-h6-pwm",
388 .data = &sun50i_h6_pwm_data,
389 }, {
390 /* sentinel */
391 },
392 };
393 MODULE_DEVICE_TABLE(of, sun4i_pwm_dt_ids);
394
sun4i_pwm_probe(struct platform_device * pdev)395 static int sun4i_pwm_probe(struct platform_device *pdev)
396 {
397 struct sun4i_pwm_chip *pwm;
398 struct resource *res;
399 int ret;
400
401 pwm = devm_kzalloc(&pdev->dev, sizeof(*pwm), GFP_KERNEL);
402 if (!pwm)
403 return -ENOMEM;
404
405 pwm->data = of_device_get_match_data(&pdev->dev);
406 if (!pwm->data)
407 return -ENODEV;
408
409 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
410 pwm->base = devm_ioremap_resource(&pdev->dev, res);
411 if (IS_ERR(pwm->base))
412 return PTR_ERR(pwm->base);
413
414 /*
415 * All hardware variants need a source clock that is divided and
416 * then feeds the counter that defines the output wave form. In the
417 * device tree this clock is either unnamed or called "mod".
418 * Some variants (e.g. H6) need another clock to access the
419 * hardware registers; this is called "bus".
420 * So we request "mod" first (and ignore the corner case that a
421 * parent provides a "mod" clock while the right one would be the
422 * unnamed one of the PWM device) and if this is not found we fall
423 * back to the first clock of the PWM.
424 */
425 pwm->clk = devm_clk_get_optional(&pdev->dev, "mod");
426 if (IS_ERR(pwm->clk))
427 return dev_err_probe(&pdev->dev, PTR_ERR(pwm->clk),
428 "get mod clock failed\n");
429
430 if (!pwm->clk) {
431 pwm->clk = devm_clk_get(&pdev->dev, NULL);
432 if (IS_ERR(pwm->clk))
433 return dev_err_probe(&pdev->dev, PTR_ERR(pwm->clk),
434 "get unnamed clock failed\n");
435 }
436
437 pwm->bus_clk = devm_clk_get_optional(&pdev->dev, "bus");
438 if (IS_ERR(pwm->bus_clk))
439 return dev_err_probe(&pdev->dev, PTR_ERR(pwm->bus_clk),
440 "get bus clock failed\n");
441
442 pwm->rst = devm_reset_control_get_optional_shared(&pdev->dev, NULL);
443 if (IS_ERR(pwm->rst))
444 return dev_err_probe(&pdev->dev, PTR_ERR(pwm->rst),
445 "get reset failed\n");
446
447 /* Deassert reset */
448 ret = reset_control_deassert(pwm->rst);
449 if (ret) {
450 dev_err(&pdev->dev, "cannot deassert reset control: %pe\n",
451 ERR_PTR(ret));
452 return ret;
453 }
454
455 /*
456 * We're keeping the bus clock on for the sake of simplicity.
457 * Actually it only needs to be on for hardware register accesses.
458 */
459 ret = clk_prepare_enable(pwm->bus_clk);
460 if (ret) {
461 dev_err(&pdev->dev, "cannot prepare and enable bus_clk %pe\n",
462 ERR_PTR(ret));
463 goto err_bus;
464 }
465
466 pwm->chip.dev = &pdev->dev;
467 pwm->chip.ops = &sun4i_pwm_ops;
468 pwm->chip.base = -1;
469 pwm->chip.npwm = pwm->data->npwm;
470 pwm->chip.of_xlate = of_pwm_xlate_with_flags;
471 pwm->chip.of_pwm_n_cells = 3;
472
473 spin_lock_init(&pwm->ctrl_lock);
474
475 ret = pwmchip_add(&pwm->chip);
476 if (ret < 0) {
477 dev_err(&pdev->dev, "failed to add PWM chip: %d\n", ret);
478 goto err_pwm_add;
479 }
480
481 platform_set_drvdata(pdev, pwm);
482
483 return 0;
484
485 err_pwm_add:
486 clk_disable_unprepare(pwm->bus_clk);
487 err_bus:
488 reset_control_assert(pwm->rst);
489
490 return ret;
491 }
492
sun4i_pwm_remove(struct platform_device * pdev)493 static int sun4i_pwm_remove(struct platform_device *pdev)
494 {
495 struct sun4i_pwm_chip *pwm = platform_get_drvdata(pdev);
496 int ret;
497
498 ret = pwmchip_remove(&pwm->chip);
499 if (ret)
500 return ret;
501
502 clk_disable_unprepare(pwm->bus_clk);
503 reset_control_assert(pwm->rst);
504
505 return 0;
506 }
507
508 static struct platform_driver sun4i_pwm_driver = {
509 .driver = {
510 .name = "sun4i-pwm",
511 .of_match_table = sun4i_pwm_dt_ids,
512 },
513 .probe = sun4i_pwm_probe,
514 .remove = sun4i_pwm_remove,
515 };
516 module_platform_driver(sun4i_pwm_driver);
517
518 MODULE_ALIAS("platform:sun4i-pwm");
519 MODULE_AUTHOR("Alexandre Belloni <alexandre.belloni@free-electrons.com>");
520 MODULE_DESCRIPTION("Allwinner sun4i PWM driver");
521 MODULE_LICENSE("GPL v2");
522
