Searched refs:PSW (Results 1 – 14 of 14) sorted by relevance
| /Linux-v5.10/arch/sh/boards/mach-highlander/ |
| D | irq-r7780rp.c | 20 PSW, /* Push Switch */ enumerator
35 INTC_IRQ(PSW, IRQ_PSW),
42 0, 0, 0, 0, 0, 0, PSW, AX88796 } },
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| D | irq-r7780mp.c | 25 PSW, /* Push Switch */ enumerator
39 INTC_IRQ(PSW, IRQ_PSW),
49 0, EXT6, EXT5, EXT4, EXT2, EXT1, PSW, AX88796 } },
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| /Linux-v5.10/arch/s390/boot/ |
| D | text_dma.S | 118 larl %r4,.Lcontinue_psw # Save PSW flags
121 larl %r4,restart_part2 # Setup restart PSW at absolute 0
123 og %r4,0(%r3) # Save PSW
140 larl %r4,.Lcontinue_psw # Restore PSW flags
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| D | head.S | 40 .long 0x02000068,0x60000050 # (a PSW and two CCWs).
50 .long 0x02000370,0x60000050 # the channel program the PSW
274 # this is called either by the ipl loader or directly by PSW restart
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| /Linux-v5.10/arch/nds32/kernel/ |
| D | ex-entry.S | 57 mfsr $r19, $PSW
75 mtsr $r17, $PSW
121 mfsr $r21, $PSW
124 mtsr $r21, $PSW
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| D | ex-exit.S | 43 mtsr $r19, $PSW
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| D | head.S | 158 mfsr $p1, $PSW
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| /Linux-v5.10/Documentation/parisc/ |
| D | registers.rst | 27 CR22 Interrupt PSW
92 PSW default W value 0
93 PSW default E value 0
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| D | debugging.rst | 38 Certain, very critical code has to clear the Q bit in the PSW. What
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| /Linux-v5.10/Documentation/virt/kvm/ |
| D | s390-pv-boot.rst | 57 decrypt and verify the PV, as well as control flags and a start PSW.
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| D | s390-pv.rst | 60 PSW bit 13 has been changed, indicating that a machine check
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| D | api.rst | 6229 This capability indicates that the PSW is exposed via the kvm_run structure.
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| /Linux-v5.10/arch/s390/kernel/ |
| D | entry.S | 333 # will rewind the PSW by the ILC, which is often 4 bytes in case of SIE. There
1202 mvc __LC_RETURN_MCCK_PSW(16),__PT_PSW(%r11) # move return PSW
1217 # PSW restart interrupt handler
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| /Linux-v5.10/arch/powerpc/xmon/ |
| D | ppc-opc.c | 350 #define PSW E macro
6339 {"psq_l", OP(56), OP_MASK, PPCPS, PPCVLE, {FRT,PSD,RA,PSW,PSQ}},
6345 {"psq_lu", OP(57), OP_MASK, PPCPS, PPCVLE, {FRT,PSD,RA,PSW,PSQ}},
6662 {"psq_st", OP(60), OP_MASK, PPCPS, PPCVLE, {FRS,PSD,RA,PSW,PSQ}},
6670 {"psq_stu", OP(61), OP_MASK, PPCPS, PPCVLE, {FRS,PSD,RA,PSW,PSQ}},
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