| /Linux-v5.10/arch/arm64/include/asm/ |
| D | daifflags.h | 16 #define DAIF_PROCCTX_NOIRQ PSR_I_BIT
17 #define DAIF_ERRCTX (PSR_I_BIT | PSR_A_BIT)
18 #define DAIF_MASK (PSR_D_BIT | PSR_A_BIT | PSR_I_BIT | PSR_F_BIT)
50 flags |= PSR_I_BIT; in local_daif_save_flags()
69 bool irq_disabled = flags & PSR_I_BIT; in local_daif_restore()
72 !(read_sysreg(daif) & PSR_I_BIT)); in local_daif_restore()
89 flags &= ~PSR_I_BIT; in local_daif_restore()
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| D | irqflags.h | 88 "and %w0, %w1, #" __stringify(PSR_I_BIT), in arch_irqs_disabled_flags()
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| D | efi.h | 45 #define ARCH_EFI_IRQ_FLAGS_MASK (PSR_D_BIT | PSR_A_BIT | PSR_I_BIT | PSR_F_BIT)
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| D | ptrace.h | 239 (!((regs)->pstate & PSR_I_BIT) && irqs_priority_unmasked(regs))
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| /Linux-v5.10/arch/arm/kernel/ |
| D | fiqasm.S | 26 mov r2, #PSR_I_BIT | PSR_F_BIT | FIQ_MODE
39 mov r2, #PSR_I_BIT | PSR_F_BIT | FIQ_MODE
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| D | entry-armv.S | 331 ARM( msr cpsr_c, #ABT_MODE | PSR_I_BIT | PSR_F_BIT )
332 THUMB( mov r0, #ABT_MODE | PSR_I_BIT | PSR_F_BIT )
336 ARM( msr cpsr_c, #SVC_MODE | PSR_I_BIT | PSR_F_BIT )
337 THUMB( mov r0, #SVC_MODE | PSR_I_BIT | PSR_F_BIT )
345 ARM( msr cpsr_c, #ABT_MODE | PSR_I_BIT | PSR_F_BIT )
346 THUMB( mov r0, #ABT_MODE | PSR_I_BIT | PSR_F_BIT )
350 ARM( msr cpsr_c, #SVC_MODE | PSR_I_BIT | PSR_F_BIT )
351 THUMB( mov r0, #SVC_MODE | PSR_I_BIT | PSR_F_BIT )
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| D | iwmmxt.S | 197 orr r2, ip, #PSR_I_BIT @ disable interrupts
249 orr r2, ip, #PSR_I_BIT @ disable interrupts
287 orr r2, ip, #PSR_I_BIT @ disable interrupts
354 orr ip, r2, #PSR_I_BIT @ disable interrupts
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| D | setup.c | 570 PLC (PSR_F_BIT | PSR_I_BIT | IRQ_MODE), in cpu_init()
572 PLC (PSR_F_BIT | PSR_I_BIT | ABT_MODE), in cpu_init()
574 PLC (PSR_F_BIT | PSR_I_BIT | UND_MODE), in cpu_init()
576 PLC (PSR_F_BIT | PSR_I_BIT | FIQ_MODE), in cpu_init()
578 PLC (PSR_F_BIT | PSR_I_BIT | SVC_MODE) in cpu_init()
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| /Linux-v5.10/arch/arm/include/asm/ |
| D | ptrace.h | 49 (!((regs)->ARM_cpsr & PSR_I_BIT))
67 if ((regs->ARM_cpsr & PSR_I_BIT) == 0) { in valid_user_regs()
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| D | assembler.h | 102 msr cpsr_c, #PSR_I_BIT | SVC_MODE
182 tst \oldcpsr, #PSR_I_BIT
348 orr \reg , \reg , #PSR_I_BIT | PSR_F_BIT | SVC_MODE
363 setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, \reg
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| D | efi.h | 35 (PSR_J_BIT | PSR_E_BIT | PSR_A_BIT | PSR_I_BIT | PSR_F_BIT | \
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| D | irqflags.h | 19 #define IRQMASK_I_BIT PSR_I_BIT
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| /Linux-v5.10/tools/testing/selftests/arm64/signal/testcases/ |
| D | mangle_pstate_invalid_daif_bits.c | 23 uc->uc_mcontext.pstate |= PSR_D_BIT | PSR_A_BIT | PSR_I_BIT | PSR_F_BIT; in mangle_invalid_pstate_run()
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| /Linux-v5.10/arch/arm/mach-s3c/ |
| D | sleep-s3c24xx.S | 42 mov r0, #PSR_I_BIT | PSR_F_BIT | SVC_MODE
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| D | sleep-s3c64xx.S | 40 msr cpsr_c, #PSR_I_BIT | PSR_F_BIT | SVC_MODE
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| /Linux-v5.10/arch/arm/mach-rockchip/ |
| D | sleep.S | 20 setmode PSR_I_BIT | PSR_F_BIT | SVC_MODE, r1 @ set svc, irqs off
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| /Linux-v5.10/arch/arm/mach-ep93xx/ |
| D | crunch-bits.S | 210 orr r2, ip, #PSR_I_BIT @ disable interrupts
256 orr r2, ip, #PSR_I_BIT @ disable interrupts
289 orr r2, ip, #PSR_I_BIT @ disable interrupts
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| /Linux-v5.10/arch/arm/include/uapi/asm/ |
| D | ptrace.h | 79 #define PSR_I_BIT 0x00000080 /* >= V4, but not V7M */ macro
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| /Linux-v5.10/arch/arm/mm/ |
| D | proc-feroceon.S | 250 orr r3, r2, #PSR_I_BIT
296 orr r3, r2, #PSR_I_BIT
328 orr r3, r2, #PSR_I_BIT
359 orr r3, r2, #PSR_I_BIT
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| /Linux-v5.10/arch/arm64/include/uapi/asm/ |
| D | ptrace.h | 46 #define PSR_I_BIT 0x00000080 macro
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| /Linux-v5.10/arch/arm64/kvm/ |
| D | inject_fault.c | 114 new |= PSR_I_BIT; in enter_exception64()
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| D | reset.c | 39 #define VCPU_RESET_PSTATE_EL1 (PSR_MODE_EL1h | PSR_A_BIT | PSR_I_BIT | \
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| /Linux-v5.10/arch/arm64/kernel/ |
| D | process.c | 87 write_sysreg(daif_bits | PSR_I_BIT, daif); in __cpu_do_idle_irqprio()
252 pstate & PSR_I_BIT ? 'I' : 'i', in print_pstate()
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| /Linux-v5.10/arch/arm64/kvm/hyp/nvhe/ |
| D | hyp-init.S | 152 mov x0, #(PSR_F_BIT | PSR_I_BIT | PSR_A_BIT | PSR_D_BIT | PSR_MODE_EL2h)
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| D | host.S | 79 mov lr, #(PSR_F_BIT | PSR_I_BIT | PSR_A_BIT | PSR_D_BIT |\
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