1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DC_DP_TYPES_H 27 #define DC_DP_TYPES_H 28 29 #include "os_types.h" 30 31 enum dc_lane_count { 32 LANE_COUNT_UNKNOWN = 0, 33 LANE_COUNT_ONE = 1, 34 LANE_COUNT_TWO = 2, 35 LANE_COUNT_FOUR = 4, 36 LANE_COUNT_EIGHT = 8, 37 LANE_COUNT_DP_MAX = LANE_COUNT_FOUR 38 }; 39 40 /* This is actually a reference clock (27MHz) multiplier 41 * 162MBps bandwidth for 1.62GHz like rate, 42 * 270MBps for 2.70GHz, 43 * 324MBps for 3.24Ghz, 44 * 540MBps for 5.40GHz 45 * 810MBps for 8.10GHz 46 */ 47 enum dc_link_rate { 48 LINK_RATE_UNKNOWN = 0, 49 LINK_RATE_LOW = 0x06, // Rate_1 (RBR) - 1.62 Gbps/Lane 50 LINK_RATE_RATE_2 = 0x08, // Rate_2 - 2.16 Gbps/Lane 51 LINK_RATE_RATE_3 = 0x09, // Rate_3 - 2.43 Gbps/Lane 52 LINK_RATE_HIGH = 0x0A, // Rate_4 (HBR) - 2.70 Gbps/Lane 53 LINK_RATE_RBR2 = 0x0C, // Rate_5 (RBR2)- 3.24 Gbps/Lane 54 LINK_RATE_RATE_6 = 0x10, // Rate_6 - 4.32 Gbps/Lane 55 LINK_RATE_HIGH2 = 0x14, // Rate_7 (HBR2)- 5.40 Gbps/Lane 56 LINK_RATE_HIGH3 = 0x1E // Rate_8 (HBR3)- 8.10 Gbps/Lane 57 }; 58 59 enum dc_link_spread { 60 LINK_SPREAD_DISABLED = 0x00, 61 /* 0.5 % downspread 30 kHz */ 62 LINK_SPREAD_05_DOWNSPREAD_30KHZ = 0x10, 63 /* 0.5 % downspread 33 kHz */ 64 LINK_SPREAD_05_DOWNSPREAD_33KHZ = 0x11 65 }; 66 67 enum dc_voltage_swing { 68 VOLTAGE_SWING_LEVEL0 = 0, /* direct HW translation! */ 69 VOLTAGE_SWING_LEVEL1, 70 VOLTAGE_SWING_LEVEL2, 71 VOLTAGE_SWING_LEVEL3, 72 VOLTAGE_SWING_MAX_LEVEL = VOLTAGE_SWING_LEVEL3 73 }; 74 75 enum dc_pre_emphasis { 76 PRE_EMPHASIS_DISABLED = 0, /* direct HW translation! */ 77 PRE_EMPHASIS_LEVEL1, 78 PRE_EMPHASIS_LEVEL2, 79 PRE_EMPHASIS_LEVEL3, 80 PRE_EMPHASIS_MAX_LEVEL = PRE_EMPHASIS_LEVEL3 81 }; 82 /* Post Cursor 2 is optional for transmitter 83 * and it applies only to the main link operating at HBR2 84 */ 85 enum dc_post_cursor2 { 86 POST_CURSOR2_DISABLED = 0, /* direct HW translation! */ 87 POST_CURSOR2_LEVEL1, 88 POST_CURSOR2_LEVEL2, 89 POST_CURSOR2_LEVEL3, 90 POST_CURSOR2_MAX_LEVEL = POST_CURSOR2_LEVEL3, 91 }; 92 93 enum dc_dp_training_pattern { 94 DP_TRAINING_PATTERN_SEQUENCE_1 = 0, 95 DP_TRAINING_PATTERN_SEQUENCE_2, 96 DP_TRAINING_PATTERN_SEQUENCE_3, 97 DP_TRAINING_PATTERN_SEQUENCE_4, 98 }; 99 100 struct dc_link_settings { 101 enum dc_lane_count lane_count; 102 enum dc_link_rate link_rate; 103 enum dc_link_spread link_spread; 104 bool use_link_rate_set; 105 uint8_t link_rate_set; 106 }; 107 108 struct dc_lane_settings { 109 enum dc_voltage_swing VOLTAGE_SWING; 110 enum dc_pre_emphasis PRE_EMPHASIS; 111 enum dc_post_cursor2 POST_CURSOR2; 112 }; 113 114 struct dc_link_training_settings { 115 struct dc_link_settings link; 116 struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX]; 117 }; 118 119 struct dc_link_training_overrides { 120 enum dc_voltage_swing *voltage_swing; 121 enum dc_pre_emphasis *pre_emphasis; 122 enum dc_post_cursor2 *post_cursor2; 123 124 uint16_t *cr_pattern_time; 125 uint16_t *eq_pattern_time; 126 enum dc_dp_training_pattern *pattern_for_cr; 127 enum dc_dp_training_pattern *pattern_for_eq; 128 129 enum dc_link_spread *downspread; 130 bool *alternate_scrambler_reset; 131 bool *enhanced_framing; 132 bool *mst_enable; 133 bool *fec_enable; 134 }; 135 136 union dpcd_rev { 137 struct { 138 uint8_t MINOR:4; 139 uint8_t MAJOR:4; 140 } bits; 141 uint8_t raw; 142 }; 143 144 union max_lane_count { 145 struct { 146 uint8_t MAX_LANE_COUNT:5; 147 uint8_t POST_LT_ADJ_REQ_SUPPORTED:1; 148 uint8_t TPS3_SUPPORTED:1; 149 uint8_t ENHANCED_FRAME_CAP:1; 150 } bits; 151 uint8_t raw; 152 }; 153 154 union max_down_spread { 155 struct { 156 uint8_t MAX_DOWN_SPREAD:1; 157 uint8_t RESERVED:5; 158 uint8_t NO_AUX_HANDSHAKE_LINK_TRAINING:1; 159 uint8_t TPS4_SUPPORTED:1; 160 } bits; 161 uint8_t raw; 162 }; 163 164 union mstm_cap { 165 struct { 166 uint8_t MST_CAP:1; 167 uint8_t RESERVED:7; 168 } bits; 169 uint8_t raw; 170 }; 171 172 union lane_count_set { 173 struct { 174 uint8_t LANE_COUNT_SET:5; 175 uint8_t POST_LT_ADJ_REQ_GRANTED:1; 176 uint8_t RESERVED:1; 177 uint8_t ENHANCED_FRAMING:1; 178 } bits; 179 uint8_t raw; 180 }; 181 182 union lane_status { 183 struct { 184 uint8_t CR_DONE_0:1; 185 uint8_t CHANNEL_EQ_DONE_0:1; 186 uint8_t SYMBOL_LOCKED_0:1; 187 uint8_t RESERVED0:1; 188 uint8_t CR_DONE_1:1; 189 uint8_t CHANNEL_EQ_DONE_1:1; 190 uint8_t SYMBOL_LOCKED_1:1; 191 uint8_t RESERVED_1:1; 192 } bits; 193 uint8_t raw; 194 }; 195 196 union device_service_irq { 197 struct { 198 uint8_t REMOTE_CONTROL_CMD_PENDING:1; 199 uint8_t AUTOMATED_TEST:1; 200 uint8_t CP_IRQ:1; 201 uint8_t MCCS_IRQ:1; 202 uint8_t DOWN_REP_MSG_RDY:1; 203 uint8_t UP_REQ_MSG_RDY:1; 204 uint8_t SINK_SPECIFIC:1; 205 uint8_t reserved:1; 206 } bits; 207 uint8_t raw; 208 }; 209 210 union sink_count { 211 struct { 212 uint8_t SINK_COUNT:6; 213 uint8_t CPREADY:1; 214 uint8_t RESERVED:1; 215 } bits; 216 uint8_t raw; 217 }; 218 219 union lane_align_status_updated { 220 struct { 221 uint8_t INTERLANE_ALIGN_DONE:1; 222 uint8_t POST_LT_ADJ_REQ_IN_PROGRESS:1; 223 uint8_t RESERVED:4; 224 uint8_t DOWNSTREAM_PORT_STATUS_CHANGED:1; 225 uint8_t LINK_STATUS_UPDATED:1; 226 } bits; 227 uint8_t raw; 228 }; 229 230 union lane_adjust { 231 struct { 232 uint8_t VOLTAGE_SWING_LANE:2; 233 uint8_t PRE_EMPHASIS_LANE:2; 234 uint8_t RESERVED:4; 235 } bits; 236 uint8_t raw; 237 }; 238 239 union dpcd_training_pattern { 240 struct { 241 uint8_t TRAINING_PATTERN_SET:4; 242 uint8_t RECOVERED_CLOCK_OUT_EN:1; 243 uint8_t SCRAMBLING_DISABLE:1; 244 uint8_t SYMBOL_ERROR_COUNT_SEL:2; 245 } v1_4; 246 struct { 247 uint8_t TRAINING_PATTERN_SET:2; 248 uint8_t LINK_QUAL_PATTERN_SET:2; 249 uint8_t RESERVED:4; 250 } v1_3; 251 uint8_t raw; 252 }; 253 254 /* Training Lane is used to configure downstream DP device's voltage swing 255 and pre-emphasis levels*/ 256 /* The DPCD addresses are from 0x103 to 0x106*/ 257 union dpcd_training_lane { 258 struct { 259 uint8_t VOLTAGE_SWING_SET:2; 260 uint8_t MAX_SWING_REACHED:1; 261 uint8_t PRE_EMPHASIS_SET:2; 262 uint8_t MAX_PRE_EMPHASIS_REACHED:1; 263 uint8_t RESERVED:2; 264 } bits; 265 uint8_t raw; 266 }; 267 268 /* TMDS-converter related */ 269 union dwnstream_port_caps_byte0 { 270 struct { 271 uint8_t DWN_STRM_PORTX_TYPE:3; 272 uint8_t DWN_STRM_PORTX_HPD:1; 273 uint8_t RESERVERD:4; 274 } bits; 275 uint8_t raw; 276 }; 277 278 /* these are the detailed types stored at DWN_STRM_PORTX_CAP (00080h)*/ 279 enum dpcd_downstream_port_detailed_type { 280 DOWN_STREAM_DETAILED_DP = 0, 281 DOWN_STREAM_DETAILED_VGA, 282 DOWN_STREAM_DETAILED_DVI, 283 DOWN_STREAM_DETAILED_HDMI, 284 DOWN_STREAM_DETAILED_NONDDC,/* has no EDID (TV,CV)*/ 285 DOWN_STREAM_DETAILED_DP_PLUS_PLUS 286 }; 287 288 union dwnstream_port_caps_byte2 { 289 struct { 290 uint8_t MAX_BITS_PER_COLOR_COMPONENT:2; 291 uint8_t RESERVED:6; 292 } bits; 293 uint8_t raw; 294 }; 295 296 union dp_downstream_port_present { 297 uint8_t byte; 298 struct { 299 uint8_t PORT_PRESENT:1; 300 uint8_t PORT_TYPE:2; 301 uint8_t FMT_CONVERSION:1; 302 uint8_t DETAILED_CAPS:1; 303 uint8_t RESERVED:3; 304 } fields; 305 }; 306 307 union dwnstream_port_caps_byte3_dvi { 308 struct { 309 uint8_t RESERVED1:1; 310 uint8_t DUAL_LINK:1; 311 uint8_t HIGH_COLOR_DEPTH:1; 312 uint8_t RESERVED2:5; 313 } bits; 314 uint8_t raw; 315 }; 316 317 union dwnstream_port_caps_byte3_hdmi { 318 struct { 319 uint8_t FRAME_SEQ_TO_FRAME_PACK:1; 320 uint8_t YCrCr422_PASS_THROUGH:1; 321 uint8_t YCrCr420_PASS_THROUGH:1; 322 uint8_t YCrCr422_CONVERSION:1; 323 uint8_t YCrCr420_CONVERSION:1; 324 uint8_t RESERVED:3; 325 } bits; 326 uint8_t raw; 327 }; 328 329 /*4-byte structure for detailed capabilities of a down-stream port 330 (DP-to-TMDS converter).*/ 331 union dwnstream_portxcaps { 332 struct { 333 union dwnstream_port_caps_byte0 byte0; 334 unsigned char max_TMDS_clock; //byte1 335 union dwnstream_port_caps_byte2 byte2; 336 337 union { 338 union dwnstream_port_caps_byte3_dvi byteDVI; 339 union dwnstream_port_caps_byte3_hdmi byteHDMI; 340 } byte3; 341 } bytes; 342 343 unsigned char raw[4]; 344 }; 345 346 union downstream_port { 347 struct { 348 unsigned char present:1; 349 unsigned char type:2; 350 unsigned char format_conv:1; 351 unsigned char detailed_caps:1; 352 unsigned char reserved:3; 353 } bits; 354 unsigned char raw; 355 }; 356 357 358 union sink_status { 359 struct { 360 uint8_t RX_PORT0_STATUS:1; 361 uint8_t RX_PORT1_STATUS:1; 362 uint8_t RESERVED:6; 363 } bits; 364 uint8_t raw; 365 }; 366 367 /*6-byte structure corresponding to 6 registers (200h-205h) 368 read during handling of HPD-IRQ*/ 369 union hpd_irq_data { 370 struct { 371 union sink_count sink_cnt;/* 200h */ 372 union device_service_irq device_service_irq;/* 201h */ 373 union lane_status lane01_status;/* 202h */ 374 union lane_status lane23_status;/* 203h */ 375 union lane_align_status_updated lane_status_updated;/* 204h */ 376 union sink_status sink_status; 377 } bytes; 378 uint8_t raw[6]; 379 }; 380 381 union down_stream_port_count { 382 struct { 383 uint8_t DOWN_STR_PORT_COUNT:4; 384 uint8_t RESERVED:2; /*Bits 5:4 = RESERVED. Read all 0s.*/ 385 /*Bit 6 = MSA_TIMING_PAR_IGNORED 386 0 = Sink device requires the MSA timing parameters 387 1 = Sink device is capable of rendering incoming video 388 stream without MSA timing parameters*/ 389 uint8_t IGNORE_MSA_TIMING_PARAM:1; 390 /*Bit 7 = OUI Support 391 0 = OUI not supported 392 1 = OUI supported 393 (OUI and Device Identification mandatory for DP 1.2)*/ 394 uint8_t OUI_SUPPORT:1; 395 } bits; 396 uint8_t raw; 397 }; 398 399 union down_spread_ctrl { 400 struct { 401 uint8_t RESERVED1:4;/* Bit 3:0 = RESERVED. Read all 0s*/ 402 /* Bits 4 = SPREAD_AMP. Spreading amplitude 403 0 = Main link signal is not downspread 404 1 = Main link signal is downspread <= 0.5% 405 with frequency in the range of 30kHz ~ 33kHz*/ 406 uint8_t SPREAD_AMP:1; 407 uint8_t RESERVED2:2;/*Bit 6:5 = RESERVED. Read all 0s*/ 408 /*Bit 7 = MSA_TIMING_PAR_IGNORE_EN 409 0 = Source device will send valid data for the MSA Timing Params 410 1 = Source device may send invalid data for these MSA Timing Params*/ 411 uint8_t IGNORE_MSA_TIMING_PARAM:1; 412 } bits; 413 uint8_t raw; 414 }; 415 416 union dpcd_edp_config { 417 struct { 418 uint8_t PANEL_MODE_EDP:1; 419 uint8_t FRAMING_CHANGE_ENABLE:1; 420 uint8_t RESERVED:5; 421 uint8_t PANEL_SELF_TEST_ENABLE:1; 422 } bits; 423 uint8_t raw; 424 }; 425 426 struct dp_device_vendor_id { 427 uint8_t ieee_oui[3];/*24-bit IEEE OUI*/ 428 uint8_t ieee_device_id[6];/*usually 6-byte ASCII name*/ 429 }; 430 431 struct dp_sink_hw_fw_revision { 432 uint8_t ieee_hw_rev; 433 uint8_t ieee_fw_rev[2]; 434 }; 435 436 struct dpcd_vendor_signature { 437 bool is_valid; 438 439 union dpcd_ieee_vendor_signature { 440 struct { 441 uint8_t ieee_oui[3];/*24-bit IEEE OUI*/ 442 uint8_t ieee_device_id[6];/*usually 6-byte ASCII name*/ 443 uint8_t ieee_hw_rev; 444 uint8_t ieee_fw_rev[2]; 445 }; 446 uint8_t raw[12]; 447 } data; 448 }; 449 450 struct dpcd_amd_signature { 451 uint8_t AMD_IEEE_TxSignature_byte1; 452 uint8_t AMD_IEEE_TxSignature_byte2; 453 uint8_t AMD_IEEE_TxSignature_byte3; 454 uint8_t device_id_byte1; 455 uint8_t device_id_byte2; 456 uint8_t zero[4]; 457 uint8_t dce_version; 458 uint8_t dal_version_byte1; 459 uint8_t dal_version_byte2; 460 }; 461 462 struct dpcd_source_backlight_set { 463 struct { 464 uint8_t byte0; 465 uint8_t byte1; 466 uint8_t byte2; 467 uint8_t byte3; 468 } backlight_level_millinits; 469 470 struct { 471 uint8_t byte0; 472 uint8_t byte1; 473 } backlight_transition_time_ms; 474 }; 475 476 union dpcd_source_backlight_get { 477 struct { 478 uint32_t backlight_millinits_peak; /* 326h */ 479 uint32_t backlight_millinits_avg; /* 32Ah */ 480 } bytes; 481 uint8_t raw[8]; 482 }; 483 484 /*DPCD register of DP receiver capability field bits-*/ 485 union edp_configuration_cap { 486 struct { 487 uint8_t ALT_SCRAMBLER_RESET:1; 488 uint8_t FRAMING_CHANGE:1; 489 uint8_t RESERVED:1; 490 uint8_t DPCD_DISPLAY_CONTROL_CAPABLE:1; 491 uint8_t RESERVED2:4; 492 } bits; 493 uint8_t raw; 494 }; 495 496 union dprx_feature { 497 struct { 498 uint8_t GTC_CAP:1; // bit 0: DP 1.3+ 499 uint8_t SST_SPLIT_SDP_CAP:1; // bit 1: DP 1.4 500 uint8_t AV_SYNC_CAP:1; // bit 2: DP 1.3+ 501 uint8_t VSC_SDP_COLORIMETRY_SUPPORTED:1; // bit 3: DP 1.3+ 502 uint8_t VSC_EXT_VESA_SDP_SUPPORTED:1; // bit 4: DP 1.4 503 uint8_t VSC_EXT_VESA_SDP_CHAINING_SUPPORTED:1; // bit 5: DP 1.4 504 uint8_t VSC_EXT_CEA_SDP_SUPPORTED:1; // bit 6: DP 1.4 505 uint8_t VSC_EXT_CEA_SDP_CHAINING_SUPPORTED:1; // bit 7: DP 1.4 506 } bits; 507 uint8_t raw; 508 }; 509 510 union training_aux_rd_interval { 511 struct { 512 uint8_t TRAINIG_AUX_RD_INTERVAL:7; 513 uint8_t EXT_RECEIVER_CAP_FIELD_PRESENT:1; 514 } bits; 515 uint8_t raw; 516 }; 517 518 /* Automated test structures */ 519 union test_request { 520 struct { 521 uint8_t LINK_TRAINING :1; 522 uint8_t LINK_TEST_PATTRN :1; 523 uint8_t EDID_READ :1; 524 uint8_t PHY_TEST_PATTERN :1; 525 uint8_t RESERVED :1; 526 uint8_t AUDIO_TEST_PATTERN :1; 527 uint8_t TEST_AUDIO_DISABLED_VIDEO :1; 528 } bits; 529 uint8_t raw; 530 }; 531 532 union test_response { 533 struct { 534 uint8_t ACK :1; 535 uint8_t NO_ACK :1; 536 uint8_t EDID_CHECKSUM_WRITE:1; 537 uint8_t RESERVED :5; 538 } bits; 539 uint8_t raw; 540 }; 541 542 union phy_test_pattern { 543 struct { 544 /* DpcdPhyTestPatterns. This field is 2 bits for DP1.1 545 * and 3 bits for DP1.2. 546 */ 547 uint8_t PATTERN :3; 548 /* BY speci, bit7:2 is 0 for DP1.1. */ 549 uint8_t RESERVED :5; 550 } bits; 551 uint8_t raw; 552 }; 553 554 /* States of Compliance Test Specification (CTS DP1.2). */ 555 union compliance_test_state { 556 struct { 557 unsigned char STEREO_3D_RUNNING : 1; 558 unsigned char RESERVED : 7; 559 } bits; 560 unsigned char raw; 561 }; 562 563 union link_test_pattern { 564 struct { 565 /* dpcd_link_test_patterns */ 566 unsigned char PATTERN :2; 567 unsigned char RESERVED:6; 568 } bits; 569 unsigned char raw; 570 }; 571 572 union test_misc { 573 struct dpcd_test_misc_bits { 574 unsigned char SYNC_CLOCK :1; 575 /* dpcd_test_color_format */ 576 unsigned char CLR_FORMAT :2; 577 /* dpcd_test_dyn_range */ 578 unsigned char DYN_RANGE :1; 579 unsigned char YCBCR_COEFS :1; 580 /* dpcd_test_bit_depth */ 581 unsigned char BPC :3; 582 } bits; 583 unsigned char raw; 584 }; 585 586 union audio_test_mode { 587 struct { 588 unsigned char sampling_rate :4; 589 unsigned char channel_count :4; 590 } bits; 591 unsigned char raw; 592 }; 593 594 union audio_test_pattern_period { 595 struct { 596 unsigned char pattern_period :4; 597 unsigned char reserved :4; 598 } bits; 599 unsigned char raw; 600 }; 601 602 struct audio_test_pattern_type { 603 unsigned char value; 604 }; 605 606 struct dp_audio_test_data_flags { 607 uint8_t test_requested :1; 608 uint8_t disable_video :1; 609 }; 610 611 struct dp_audio_test_data { 612 613 struct dp_audio_test_data_flags flags; 614 uint8_t sampling_rate; 615 uint8_t channel_count; 616 uint8_t pattern_type; 617 uint8_t pattern_period[8]; 618 }; 619 620 /* FEC capability DPCD register field bits-*/ 621 union dpcd_fec_capability { 622 struct { 623 uint8_t FEC_CAPABLE:1; 624 uint8_t UNCORRECTED_BLOCK_ERROR_COUNT_CAPABLE:1; 625 uint8_t CORRECTED_BLOCK_ERROR_COUNT_CAPABLE:1; 626 uint8_t BIT_ERROR_COUNT_CAPABLE:1; 627 uint8_t RESERVED:4; 628 } bits; 629 uint8_t raw; 630 }; 631 632 /* DSC capability DPCD register field bits-*/ 633 struct dpcd_dsc_support { 634 uint8_t DSC_SUPPORT :1; 635 uint8_t DSC_PASSTHROUGH_SUPPORT :1; 636 uint8_t RESERVED :6; 637 }; 638 639 struct dpcd_dsc_algorithm_revision { 640 uint8_t DSC_VERSION_MAJOR :4; 641 uint8_t DSC_VERSION_MINOR :4; 642 }; 643 644 struct dpcd_dsc_rc_buffer_block_size { 645 uint8_t RC_BLOCK_BUFFER_SIZE :2; 646 uint8_t RESERVED :6; 647 }; 648 649 struct dpcd_dsc_slice_capability1 { 650 uint8_t ONE_SLICE_PER_DP_DSC_SINK_DEVICE :1; 651 uint8_t TWO_SLICES_PER_DP_DSC_SINK_DEVICE :1; 652 uint8_t RESERVED :1; 653 uint8_t FOUR_SLICES_PER_DP_DSC_SINK_DEVICE :1; 654 uint8_t SIX_SLICES_PER_DP_DSC_SINK_DEVICE :1; 655 uint8_t EIGHT_SLICES_PER_DP_DSC_SINK_DEVICE :1; 656 uint8_t TEN_SLICES_PER_DP_DSC_SINK_DEVICE :1; 657 uint8_t TWELVE_SLICES_PER_DP_DSC_SINK_DEVICE :1; 658 }; 659 660 struct dpcd_dsc_line_buffer_bit_depth { 661 uint8_t LINE_BUFFER_BIT_DEPTH :4; 662 uint8_t RESERVED :4; 663 }; 664 665 struct dpcd_dsc_block_prediction_support { 666 uint8_t BLOCK_PREDICTION_SUPPORT:1; 667 uint8_t RESERVED :7; 668 }; 669 670 struct dpcd_maximum_bits_per_pixel_supported_by_the_decompressor { 671 uint8_t MAXIMUM_BITS_PER_PIXEL_SUPPORTED_BY_THE_DECOMPRESSOR_LOW :7; 672 uint8_t MAXIMUM_BITS_PER_PIXEL_SUPPORTED_BY_THE_DECOMPRESSOR_HIGH :7; 673 uint8_t RESERVED :2; 674 }; 675 676 struct dpcd_dsc_decoder_color_format_capabilities { 677 uint8_t RGB_SUPPORT :1; 678 uint8_t Y_CB_CR_444_SUPPORT :1; 679 uint8_t Y_CB_CR_SIMPLE_422_SUPPORT :1; 680 uint8_t Y_CB_CR_NATIVE_422_SUPPORT :1; 681 uint8_t Y_CB_CR_NATIVE_420_SUPPORT :1; 682 uint8_t RESERVED :3; 683 }; 684 685 struct dpcd_dsc_decoder_color_depth_capabilities { 686 uint8_t RESERVED0 :1; 687 uint8_t EIGHT_BITS_PER_COLOR_SUPPORT :1; 688 uint8_t TEN_BITS_PER_COLOR_SUPPORT :1; 689 uint8_t TWELVE_BITS_PER_COLOR_SUPPORT :1; 690 uint8_t RESERVED1 :4; 691 }; 692 693 struct dpcd_peak_dsc_throughput_dsc_sink { 694 uint8_t THROUGHPUT_MODE_0:4; 695 uint8_t THROUGHPUT_MODE_1:4; 696 }; 697 698 struct dpcd_dsc_slice_capabilities_2 { 699 uint8_t SIXTEEN_SLICES_PER_DSC_SINK_DEVICE :1; 700 uint8_t TWENTY_SLICES_PER_DSC_SINK_DEVICE :1; 701 uint8_t TWENTYFOUR_SLICES_PER_DSC_SINK_DEVICE :1; 702 uint8_t RESERVED :5; 703 }; 704 705 struct dpcd_bits_per_pixel_increment{ 706 uint8_t INCREMENT_OF_BITS_PER_PIXEL_SUPPORTED :3; 707 uint8_t RESERVED :5; 708 }; 709 union dpcd_dsc_basic_capabilities { 710 struct { 711 struct dpcd_dsc_support dsc_support; 712 struct dpcd_dsc_algorithm_revision dsc_algorithm_revision; 713 struct dpcd_dsc_rc_buffer_block_size dsc_rc_buffer_block_size; 714 uint8_t dsc_rc_buffer_size; 715 struct dpcd_dsc_slice_capability1 dsc_slice_capabilities_1; 716 struct dpcd_dsc_line_buffer_bit_depth dsc_line_buffer_bit_depth; 717 struct dpcd_dsc_block_prediction_support dsc_block_prediction_support; 718 struct dpcd_maximum_bits_per_pixel_supported_by_the_decompressor maximum_bits_per_pixel_supported_by_the_decompressor; 719 struct dpcd_dsc_decoder_color_format_capabilities dsc_decoder_color_format_capabilities; 720 struct dpcd_dsc_decoder_color_depth_capabilities dsc_decoder_color_depth_capabilities; 721 struct dpcd_peak_dsc_throughput_dsc_sink peak_dsc_throughput_dsc_sink; 722 uint8_t dsc_maximum_slice_width; 723 struct dpcd_dsc_slice_capabilities_2 dsc_slice_capabilities_2; 724 uint8_t reserved; 725 struct dpcd_bits_per_pixel_increment bits_per_pixel_increment; 726 } fields; 727 uint8_t raw[16]; 728 }; 729 730 union dpcd_dsc_branch_decoder_capabilities { 731 struct { 732 uint8_t BRANCH_OVERALL_THROUGHPUT_0; 733 uint8_t BRANCH_OVERALL_THROUGHPUT_1; 734 uint8_t BRANCH_MAX_LINE_WIDTH; 735 } fields; 736 uint8_t raw[3]; 737 }; 738 739 struct dpcd_dsc_capabilities { 740 union dpcd_dsc_basic_capabilities dsc_basic_caps; 741 union dpcd_dsc_branch_decoder_capabilities dsc_branch_decoder_caps; 742 }; 743 744 /* These parameters are from PSR capabilities reported by Sink DPCD */ 745 struct psr_caps { 746 unsigned char psr_version; 747 unsigned int psr_rfb_setup_time; 748 bool psr_exit_link_training_required; 749 }; 750 751 #endif /* DC_DP_TYPES_H */ 752
