Home
last modified time | relevance | path

Searched refs:PLL_DIV (Results 1 – 5 of 5) sorted by relevance

/Linux-v5.10/drivers/clk/x86/
Dclk-lgm.c112 #define PLL_DIV(x) ((x) + 0x04) macro
193 LGM_DIV(LGM_CLK_PP_HW, "pp_hw", "pllpp", 0, PLL_DIV(CGU_PLLPP_CFG0),
195 LGM_DIV(LGM_CLK_PP_UC, "pp_uc", "pllpp", 0, PLL_DIV(CGU_PLLPP_CFG0),
197 LGM_DIV(LGM_CLK_PP_FXD, "pp_fxd", "pllpp", 0, PLL_DIV(CGU_PLLPP_CFG0),
199 LGM_DIV(LGM_CLK_PP_TBM, "pp_tbm", "pllpp", 0, PLL_DIV(CGU_PLLPP_CFG0),
202 PLL_DIV(CGU_PLL2_CFG0), 0, PLL_DIV_WIDTH, 24, 1, 0, 0,
204 LGM_DIV(LGM_CLK_CM, "cpu_cm", "pll0cz", 0, PLL_DIV(CGU_PLL0CZ_CFG0),
208 PLL_DIV(CGU_PLL0CZ_CFG0), 4, PLL_DIV_WIDTH, 25,
211 LGM_DIV(LGM_CLK_SDXC3, "sdxc3", "pll0cz", 0, PLL_DIV(CGU_PLL0CZ_CFG0),
215 CLK_IGNORE_UNUSED, PLL_DIV(CGU_PLL0CM0_CFG0),
[all …]
/Linux-v5.10/drivers/mfd/
Ddb8500-prcmu.c463 PLL_DIV enumerator
471 CLK_MGT_ENTRY(SGACLK, PLL_DIV, false),
476 CLK_MGT_ENTRY(SDMMCCLK, PLL_DIV, true),
478 CLK_MGT_ENTRY(PER1CLK, PLL_DIV, true),
479 CLK_MGT_ENTRY(PER2CLK, PLL_DIV, true),
480 CLK_MGT_ENTRY(PER3CLK, PLL_DIV, true),
481 CLK_MGT_ENTRY(PER5CLK, PLL_DIV, true),
482 CLK_MGT_ENTRY(PER6CLK, PLL_DIV, true),
483 CLK_MGT_ENTRY(PER7CLK, PLL_DIV, true),
485 CLK_MGT_ENTRY(BMLCLK, PLL_DIV, true),
[all …]
/Linux-v5.10/drivers/clk/
Dclk-sparx5.c19 #define PLL_DIV GENMASK(7, 0) macro
179 val |= FIELD_PREP(PLL_DIV, conf.div); in s5_pll_set_rate()
202 conf.div = FIELD_GET(PLL_DIV, val); in s5_pll_recalc_rate()
/Linux-v5.10/drivers/clk/at91/
Dclk-pll.c19 #define PLL_DIV(reg) ((reg) & PLL_DIV_MASK) macro
71 div = PLL_DIV(pllr); in clk_pll_prepare()
304 pll->div = PLL_DIV(pllr); in at91_clk_register_pll()
/Linux-v5.10/arch/mips/ar7/
Dclock.c54 #define PLL_DIV 0x00000002 macro
192 if ((pll & (PLL_NDIV | PLL_DIV)) == (PLL_NDIV | PLL_DIV)) { in tnetd7300_get_clock()