Searched refs:PHY_TMR_LPCLK_CFG (Results 1 – 2 of 2) sorted by relevance
57 #define PHY_TMR_LPCLK_CFG 0x98 /* clock lane timing configuration */ macro
353 dw_update_bits(base + PHY_TMR_LPCLK_CFG, 16, MASK(10), in dsi_set_phy_timer()355 dw_update_bits(base + PHY_TMR_LPCLK_CFG, 0, MASK(10), in dsi_set_phy_timer()
