| /Linux-v5.10/drivers/phy/broadcom/ |
| D | phy-bcm-sr-usb.c | 21 PHY_CTRL, enumerator
29 [PHY_CTRL] = 0x14,
34 [PHY_CTRL] = 0x10,
39 [PHY_CTRL] = 0xc,
134 rd_data = readl(regs + offset[PHY_CTRL]); in bcm_usb_ss_phy_init()
137 writel(rd_data, regs + offset[PHY_CTRL]); in bcm_usb_ss_phy_init()
183 bcm_usb_reg32_clrbits(regs + offset[PHY_CTRL], in bcm_usb_phy_reset()
185 bcm_usb_reg32_setbits(regs + offset[PHY_CTRL], in bcm_usb_phy_reset()
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| /Linux-v5.10/drivers/phy/renesas/ |
| D | phy-rcar-gen3-pcie.c | 17 #define PHY_CTRL 0x4000 /* R8A77980 only */ macro
49 rcar_gen3_phy_pcie_modify_reg(p, PHY_CTRL, PHY_CTRL_PHY_PWDN, 0); in r8a77980_phy_pcie_power_on()
57 rcar_gen3_phy_pcie_modify_reg(p, PHY_CTRL, 0, PHY_CTRL_PHY_PWDN); in r8a77980_phy_pcie_power_off()
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| /Linux-v5.10/drivers/net/ethernet/intel/e1000/ |
| D | e1000_ethtool.c | 1165 e1000_write_phy_reg(hw, PHY_CTRL, 0x8100); in e1000_nonintegrated_phy_loopback()
1177 e1000_read_phy_reg(hw, PHY_CTRL, &phy_reg); in e1000_nonintegrated_phy_loopback()
1179 e1000_write_phy_reg(hw, PHY_CTRL, phy_reg); in e1000_nonintegrated_phy_loopback()
1185 e1000_read_phy_reg(hw, PHY_CTRL, &phy_reg); in e1000_nonintegrated_phy_loopback()
1213 e1000_write_phy_reg(hw, PHY_CTRL, 0x9140); in e1000_integrated_phy_loopback()
1215 e1000_write_phy_reg(hw, PHY_CTRL, 0x8140); in e1000_integrated_phy_loopback()
1221 e1000_write_phy_reg(hw, PHY_CTRL, 0x4140); in e1000_integrated_phy_loopback()
1291 e1000_read_phy_reg(hw, PHY_CTRL, &phy_reg); in e1000_set_phy_loopback()
1293 e1000_write_phy_reg(hw, PHY_CTRL, phy_reg); in e1000_set_phy_loopback()
1343 e1000_read_phy_reg(hw, PHY_CTRL, &phy_reg); in e1000_loopback_cleanup()
[all …]
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| D | e1000_main.c | 423 e1000_read_phy_reg(hw, PHY_CTRL, &mii_reg); in e1000_power_up_phy()
425 e1000_write_phy_reg(hw, PHY_CTRL, mii_reg); in e1000_power_up_phy()
460 e1000_read_phy_reg(hw, PHY_CTRL, &mii_reg); in e1000_power_down_phy()
462 e1000_write_phy_reg(hw, PHY_CTRL, mii_reg); in e1000_power_down_phy()
4704 !e1000_read_phy_reg(hw, PHY_CTRL, in e1000_smartspeed()
4708 e1000_write_phy_reg(hw, PHY_CTRL, in e1000_smartspeed()
4719 !e1000_read_phy_reg(hw, PHY_CTRL, &phy_ctrl)) { in e1000_smartspeed()
4722 e1000_write_phy_reg(hw, PHY_CTRL, phy_ctrl); in e1000_smartspeed()
4793 case PHY_CTRL: in e1000_mii_ioctl()
4828 case PHY_CTRL: in e1000_mii_ioctl()
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| D | e1000_hw.c | 1338 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data); in e1000_copper_link_autoneg()
1343 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data); in e1000_copper_link_autoneg()
1666 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &mii_ctrl_reg); in e1000_phy_force_speed_duplex()
1753 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, mii_ctrl_reg); in e1000_phy_force_speed_duplex()
1924 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data); in e1000_config_mac_to_phy()
3107 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data); in e1000_phy_reset()
3112 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data); in e1000_phy_reset()
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| D | e1000_hw.h | 2481 #define PHY_CTRL 0x00 /* Control Register */ macro
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| /Linux-v5.10/drivers/net/ethernet/intel/e1000e/ |
| D | ich8lan.c | 2355 mac_reg = er32(PHY_CTRL); in e1000_oem_bits_config_ich8lan()
2983 phy_ctrl = er32(PHY_CTRL); in e1000_set_d0_lplu_state_ich8lan()
2987 ew32(PHY_CTRL, phy_ctrl); in e1000_set_d0_lplu_state_ich8lan()
3008 ew32(PHY_CTRL, phy_ctrl); in e1000_set_d0_lplu_state_ich8lan()
3066 phy_ctrl = er32(PHY_CTRL); in e1000_set_d3_lplu_state_ich8lan()
3070 ew32(PHY_CTRL, phy_ctrl); in e1000_set_d3_lplu_state_ich8lan()
3107 ew32(PHY_CTRL, phy_ctrl); in e1000_set_d3_lplu_state_ich8lan()
5183 phy_ctrl = er32(PHY_CTRL); in e1000_kmrn_lock_loss_workaround_ich8lan()
5186 ew32(PHY_CTRL, phy_ctrl); in e1000_kmrn_lock_loss_workaround_ich8lan()
5240 reg = er32(PHY_CTRL); in e1000e_igp3_phy_powerdown_workaround_ich8lan()
[all …]
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| D | phy.c | 2646 (!(er32(PHY_CTRL) & E1000_PHY_CTRL_GBE_DISABLE))) in e1000_access_phy_wakeup_reg_bm()
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| /Linux-v5.10/drivers/mmc/host/ |
| D | sdhci-pci-arasan.c | 44 #define PHY_CTRL 0x24 macro
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| /Linux-v5.10/drivers/scsi/hisi_sas/ |
| D | hisi_sas_v1_hw.c | 126 #define PHY_CTRL (PORT_BASE + 0x14) macro
566 u32 phy_ctrl = hisi_sas_phy_read32(hisi_hba, i, PHY_CTRL); in reset_hw_v1_hw()
569 hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL, phy_ctrl); in reset_hw_v1_hw()
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| D | hisi_sas_v2_hw.c | 181 #define PHY_CTRL (PORT_BASE + 0x14) macro
1266 hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL, 0x199B694); in init_reg_v2_hw()
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| D | hisi_sas_v3_hw.c | 198 #define PHY_CTRL (PORT_BASE + 0x14) macro
2773 HISI_SAS_DEBUGFS_REG(PHY_CTRL),
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| /Linux-v5.10/drivers/mtd/nand/raw/ |
| D | cadence-nand-controller.c | 262 #define PHY_CTRL 0x2080 macro
1323 writel_relaxed(t->phy_ctrl, cdns_ctrl->reg + PHY_CTRL); in cadence_nand_set_timings()
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