1 /* 2 * PCI / PCI-X / PCI-Express support for 4xx parts 3 * 4 * Copyright 2007 Ben. Herrenschmidt <benh@kernel.crashing.org>, IBM Corp. 5 * 6 * Bits and pieces extracted from arch/ppc support by 7 * 8 * Matt Porter <mporter@kernel.crashing.org> 9 * 10 * Copyright 2002-2005 MontaVista Software Inc. 11 */ 12 #ifndef __PPC4XX_PCI_H__ 13 #define __PPC4XX_PCI_H__ 14 15 /* 16 * 4xx PCI-X bridge register definitions 17 */ 18 #define PCIX0_VENDID 0x000 19 #define PCIX0_DEVID 0x002 20 #define PCIX0_COMMAND 0x004 21 #define PCIX0_STATUS 0x006 22 #define PCIX0_REVID 0x008 23 #define PCIX0_CLS 0x009 24 #define PCIX0_CACHELS 0x00c 25 #define PCIX0_LATTIM 0x00d 26 #define PCIX0_HDTYPE 0x00e 27 #define PCIX0_BIST 0x00f 28 #define PCIX0_BAR0L 0x010 29 #define PCIX0_BAR0H 0x014 30 #define PCIX0_BAR1 0x018 31 #define PCIX0_BAR2L 0x01c 32 #define PCIX0_BAR2H 0x020 33 #define PCIX0_BAR3 0x024 34 #define PCIX0_CISPTR 0x028 35 #define PCIX0_SBSYSVID 0x02c 36 #define PCIX0_SBSYSID 0x02e 37 #define PCIX0_EROMBA 0x030 38 #define PCIX0_CAP 0x034 39 #define PCIX0_RES0 0x035 40 #define PCIX0_RES1 0x036 41 #define PCIX0_RES2 0x038 42 #define PCIX0_INTLN 0x03c 43 #define PCIX0_INTPN 0x03d 44 #define PCIX0_MINGNT 0x03e 45 #define PCIX0_MAXLTNCY 0x03f 46 #define PCIX0_BRDGOPT1 0x040 47 #define PCIX0_BRDGOPT2 0x044 48 #define PCIX0_ERREN 0x050 49 #define PCIX0_ERRSTS 0x054 50 #define PCIX0_PLBBESR 0x058 51 #define PCIX0_PLBBEARL 0x05c 52 #define PCIX0_PLBBEARH 0x060 53 #define PCIX0_POM0LAL 0x068 54 #define PCIX0_POM0LAH 0x06c 55 #define PCIX0_POM0SA 0x070 56 #define PCIX0_POM0PCIAL 0x074 57 #define PCIX0_POM0PCIAH 0x078 58 #define PCIX0_POM1LAL 0x07c 59 #define PCIX0_POM1LAH 0x080 60 #define PCIX0_POM1SA 0x084 61 #define PCIX0_POM1PCIAL 0x088 62 #define PCIX0_POM1PCIAH 0x08c 63 #define PCIX0_POM2SA 0x090 64 #define PCIX0_PIM0SAL 0x098 65 #define PCIX0_PIM0SA PCIX0_PIM0SAL 66 #define PCIX0_PIM0LAL 0x09c 67 #define PCIX0_PIM0LAH 0x0a0 68 #define PCIX0_PIM1SA 0x0a4 69 #define PCIX0_PIM1LAL 0x0a8 70 #define PCIX0_PIM1LAH 0x0ac 71 #define PCIX0_PIM2SAL 0x0b0 72 #define PCIX0_PIM2SA PCIX0_PIM2SAL 73 #define PCIX0_PIM2LAL 0x0b4 74 #define PCIX0_PIM2LAH 0x0b8 75 #define PCIX0_OMCAPID 0x0c0 76 #define PCIX0_OMNIPTR 0x0c1 77 #define PCIX0_OMMC 0x0c2 78 #define PCIX0_OMMA 0x0c4 79 #define PCIX0_OMMUA 0x0c8 80 #define PCIX0_OMMDATA 0x0cc 81 #define PCIX0_OMMEOI 0x0ce 82 #define PCIX0_PMCAPID 0x0d0 83 #define PCIX0_PMNIPTR 0x0d1 84 #define PCIX0_PMC 0x0d2 85 #define PCIX0_PMCSR 0x0d4 86 #define PCIX0_PMCSRBSE 0x0d6 87 #define PCIX0_PMDATA 0x0d7 88 #define PCIX0_PMSCRR 0x0d8 89 #define PCIX0_CAPID 0x0dc 90 #define PCIX0_NIPTR 0x0dd 91 #define PCIX0_CMD 0x0de 92 #define PCIX0_STS 0x0e0 93 #define PCIX0_IDR 0x0e4 94 #define PCIX0_CID 0x0e8 95 #define PCIX0_RID 0x0ec 96 #define PCIX0_PIM0SAH 0x0f8 97 #define PCIX0_PIM2SAH 0x0fc 98 #define PCIX0_MSGIL 0x100 99 #define PCIX0_MSGIH 0x104 100 #define PCIX0_MSGOL 0x108 101 #define PCIX0_MSGOH 0x10c 102 #define PCIX0_IM 0x1f8 103 104 /* 105 * 4xx PCI bridge register definitions 106 */ 107 #define PCIL0_PMM0LA 0x00 108 #define PCIL0_PMM0MA 0x04 109 #define PCIL0_PMM0PCILA 0x08 110 #define PCIL0_PMM0PCIHA 0x0c 111 #define PCIL0_PMM1LA 0x10 112 #define PCIL0_PMM1MA 0x14 113 #define PCIL0_PMM1PCILA 0x18 114 #define PCIL0_PMM1PCIHA 0x1c 115 #define PCIL0_PMM2LA 0x20 116 #define PCIL0_PMM2MA 0x24 117 #define PCIL0_PMM2PCILA 0x28 118 #define PCIL0_PMM2PCIHA 0x2c 119 #define PCIL0_PTM1MS 0x30 120 #define PCIL0_PTM1LA 0x34 121 #define PCIL0_PTM2MS 0x38 122 #define PCIL0_PTM2LA 0x3c 123 124 /* 125 * 4xx PCIe bridge register definitions 126 */ 127 128 /* DCR offsets */ 129 #define DCRO_PEGPL_CFGBAH 0x00 130 #define DCRO_PEGPL_CFGBAL 0x01 131 #define DCRO_PEGPL_CFGMSK 0x02 132 #define DCRO_PEGPL_MSGBAH 0x03 133 #define DCRO_PEGPL_MSGBAL 0x04 134 #define DCRO_PEGPL_MSGMSK 0x05 135 #define DCRO_PEGPL_OMR1BAH 0x06 136 #define DCRO_PEGPL_OMR1BAL 0x07 137 #define DCRO_PEGPL_OMR1MSKH 0x08 138 #define DCRO_PEGPL_OMR1MSKL 0x09 139 #define DCRO_PEGPL_OMR2BAH 0x0a 140 #define DCRO_PEGPL_OMR2BAL 0x0b 141 #define DCRO_PEGPL_OMR2MSKH 0x0c 142 #define DCRO_PEGPL_OMR2MSKL 0x0d 143 #define DCRO_PEGPL_OMR3BAH 0x0e 144 #define DCRO_PEGPL_OMR3BAL 0x0f 145 #define DCRO_PEGPL_OMR3MSKH 0x10 146 #define DCRO_PEGPL_OMR3MSKL 0x11 147 #define DCRO_PEGPL_REGBAH 0x12 148 #define DCRO_PEGPL_REGBAL 0x13 149 #define DCRO_PEGPL_REGMSK 0x14 150 #define DCRO_PEGPL_SPECIAL 0x15 151 #define DCRO_PEGPL_CFG 0x16 152 #define DCRO_PEGPL_ESR 0x17 153 #define DCRO_PEGPL_EARH 0x18 154 #define DCRO_PEGPL_EARL 0x19 155 #define DCRO_PEGPL_EATR 0x1a 156 157 /* DMER mask */ 158 #define GPL_DMER_MASK_DISA 0x02000000 159 160 /* 161 * System DCRs (SDRs) 162 */ 163 #define PESDR0_PLLLCT1 0x03a0 164 #define PESDR0_PLLLCT2 0x03a1 165 #define PESDR0_PLLLCT3 0x03a2 166 167 /* 168 * 440SPe additional DCRs 169 */ 170 #define PESDR0_440SPE_UTLSET1 0x0300 171 #define PESDR0_440SPE_UTLSET2 0x0301 172 #define PESDR0_440SPE_DLPSET 0x0302 173 #define PESDR0_440SPE_LOOP 0x0303 174 #define PESDR0_440SPE_RCSSET 0x0304 175 #define PESDR0_440SPE_RCSSTS 0x0305 176 #define PESDR0_440SPE_HSSL0SET1 0x0306 177 #define PESDR0_440SPE_HSSL0SET2 0x0307 178 #define PESDR0_440SPE_HSSL0STS 0x0308 179 #define PESDR0_440SPE_HSSL1SET1 0x0309 180 #define PESDR0_440SPE_HSSL1SET2 0x030a 181 #define PESDR0_440SPE_HSSL1STS 0x030b 182 #define PESDR0_440SPE_HSSL2SET1 0x030c 183 #define PESDR0_440SPE_HSSL2SET2 0x030d 184 #define PESDR0_440SPE_HSSL2STS 0x030e 185 #define PESDR0_440SPE_HSSL3SET1 0x030f 186 #define PESDR0_440SPE_HSSL3SET2 0x0310 187 #define PESDR0_440SPE_HSSL3STS 0x0311 188 #define PESDR0_440SPE_HSSL4SET1 0x0312 189 #define PESDR0_440SPE_HSSL4SET2 0x0313 190 #define PESDR0_440SPE_HSSL4STS 0x0314 191 #define PESDR0_440SPE_HSSL5SET1 0x0315 192 #define PESDR0_440SPE_HSSL5SET2 0x0316 193 #define PESDR0_440SPE_HSSL5STS 0x0317 194 #define PESDR0_440SPE_HSSL6SET1 0x0318 195 #define PESDR0_440SPE_HSSL6SET2 0x0319 196 #define PESDR0_440SPE_HSSL6STS 0x031a 197 #define PESDR0_440SPE_HSSL7SET1 0x031b 198 #define PESDR0_440SPE_HSSL7SET2 0x031c 199 #define PESDR0_440SPE_HSSL7STS 0x031d 200 #define PESDR0_440SPE_HSSCTLSET 0x031e 201 #define PESDR0_440SPE_LANE_ABCD 0x031f 202 #define PESDR0_440SPE_LANE_EFGH 0x0320 203 204 #define PESDR1_440SPE_UTLSET1 0x0340 205 #define PESDR1_440SPE_UTLSET2 0x0341 206 #define PESDR1_440SPE_DLPSET 0x0342 207 #define PESDR1_440SPE_LOOP 0x0343 208 #define PESDR1_440SPE_RCSSET 0x0344 209 #define PESDR1_440SPE_RCSSTS 0x0345 210 #define PESDR1_440SPE_HSSL0SET1 0x0346 211 #define PESDR1_440SPE_HSSL0SET2 0x0347 212 #define PESDR1_440SPE_HSSL0STS 0x0348 213 #define PESDR1_440SPE_HSSL1SET1 0x0349 214 #define PESDR1_440SPE_HSSL1SET2 0x034a 215 #define PESDR1_440SPE_HSSL1STS 0x034b 216 #define PESDR1_440SPE_HSSL2SET1 0x034c 217 #define PESDR1_440SPE_HSSL2SET2 0x034d 218 #define PESDR1_440SPE_HSSL2STS 0x034e 219 #define PESDR1_440SPE_HSSL3SET1 0x034f 220 #define PESDR1_440SPE_HSSL3SET2 0x0350 221 #define PESDR1_440SPE_HSSL3STS 0x0351 222 #define PESDR1_440SPE_HSSCTLSET 0x0352 223 #define PESDR1_440SPE_LANE_ABCD 0x0353 224 225 #define PESDR2_440SPE_UTLSET1 0x0370 226 #define PESDR2_440SPE_UTLSET2 0x0371 227 #define PESDR2_440SPE_DLPSET 0x0372 228 #define PESDR2_440SPE_LOOP 0x0373 229 #define PESDR2_440SPE_RCSSET 0x0374 230 #define PESDR2_440SPE_RCSSTS 0x0375 231 #define PESDR2_440SPE_HSSL0SET1 0x0376 232 #define PESDR2_440SPE_HSSL0SET2 0x0377 233 #define PESDR2_440SPE_HSSL0STS 0x0378 234 #define PESDR2_440SPE_HSSL1SET1 0x0379 235 #define PESDR2_440SPE_HSSL1SET2 0x037a 236 #define PESDR2_440SPE_HSSL1STS 0x037b 237 #define PESDR2_440SPE_HSSL2SET1 0x037c 238 #define PESDR2_440SPE_HSSL2SET2 0x037d 239 #define PESDR2_440SPE_HSSL2STS 0x037e 240 #define PESDR2_440SPE_HSSL3SET1 0x037f 241 #define PESDR2_440SPE_HSSL3SET2 0x0380 242 #define PESDR2_440SPE_HSSL3STS 0x0381 243 #define PESDR2_440SPE_HSSCTLSET 0x0382 244 #define PESDR2_440SPE_LANE_ABCD 0x0383 245 246 /* 247 * 405EX additional DCRs 248 */ 249 #define PESDR0_405EX_UTLSET1 0x0400 250 #define PESDR0_405EX_UTLSET2 0x0401 251 #define PESDR0_405EX_DLPSET 0x0402 252 #define PESDR0_405EX_LOOP 0x0403 253 #define PESDR0_405EX_RCSSET 0x0404 254 #define PESDR0_405EX_RCSSTS 0x0405 255 #define PESDR0_405EX_PHYSET1 0x0406 256 #define PESDR0_405EX_PHYSET2 0x0407 257 #define PESDR0_405EX_BIST 0x0408 258 #define PESDR0_405EX_LPB 0x040B 259 #define PESDR0_405EX_PHYSTA 0x040C 260 261 #define PESDR1_405EX_UTLSET1 0x0440 262 #define PESDR1_405EX_UTLSET2 0x0441 263 #define PESDR1_405EX_DLPSET 0x0442 264 #define PESDR1_405EX_LOOP 0x0443 265 #define PESDR1_405EX_RCSSET 0x0444 266 #define PESDR1_405EX_RCSSTS 0x0445 267 #define PESDR1_405EX_PHYSET1 0x0446 268 #define PESDR1_405EX_PHYSET2 0x0447 269 #define PESDR1_405EX_BIST 0x0448 270 #define PESDR1_405EX_LPB 0x044B 271 #define PESDR1_405EX_PHYSTA 0x044C 272 273 /* 274 * 460EX additional DCRs 275 */ 276 #define PESDR0_460EX_L0BIST 0x0308 277 #define PESDR0_460EX_L0BISTSTS 0x0309 278 #define PESDR0_460EX_L0CDRCTL 0x030A 279 #define PESDR0_460EX_L0DRV 0x030B 280 #define PESDR0_460EX_L0REC 0x030C 281 #define PESDR0_460EX_L0LPB 0x030D 282 #define PESDR0_460EX_L0CLK 0x030E 283 #define PESDR0_460EX_PHY_CTL_RST 0x030F 284 #define PESDR0_460EX_RSTSTA 0x0310 285 #define PESDR0_460EX_OBS 0x0311 286 #define PESDR0_460EX_L0ERRC 0x0320 287 288 #define PESDR1_460EX_L0BIST 0x0348 289 #define PESDR1_460EX_L1BIST 0x0349 290 #define PESDR1_460EX_L2BIST 0x034A 291 #define PESDR1_460EX_L3BIST 0x034B 292 #define PESDR1_460EX_L0BISTSTS 0x034C 293 #define PESDR1_460EX_L1BISTSTS 0x034D 294 #define PESDR1_460EX_L2BISTSTS 0x034E 295 #define PESDR1_460EX_L3BISTSTS 0x034F 296 #define PESDR1_460EX_L0CDRCTL 0x0350 297 #define PESDR1_460EX_L1CDRCTL 0x0351 298 #define PESDR1_460EX_L2CDRCTL 0x0352 299 #define PESDR1_460EX_L3CDRCTL 0x0353 300 #define PESDR1_460EX_L0DRV 0x0354 301 #define PESDR1_460EX_L1DRV 0x0355 302 #define PESDR1_460EX_L2DRV 0x0356 303 #define PESDR1_460EX_L3DRV 0x0357 304 #define PESDR1_460EX_L0REC 0x0358 305 #define PESDR1_460EX_L1REC 0x0359 306 #define PESDR1_460EX_L2REC 0x035A 307 #define PESDR1_460EX_L3REC 0x035B 308 #define PESDR1_460EX_L0LPB 0x035C 309 #define PESDR1_460EX_L1LPB 0x035D 310 #define PESDR1_460EX_L2LPB 0x035E 311 #define PESDR1_460EX_L3LPB 0x035F 312 #define PESDR1_460EX_L0CLK 0x0360 313 #define PESDR1_460EX_L1CLK 0x0361 314 #define PESDR1_460EX_L2CLK 0x0362 315 #define PESDR1_460EX_L3CLK 0x0363 316 #define PESDR1_460EX_PHY_CTL_RST 0x0364 317 #define PESDR1_460EX_RSTSTA 0x0365 318 #define PESDR1_460EX_OBS 0x0366 319 #define PESDR1_460EX_L0ERRC 0x0368 320 #define PESDR1_460EX_L1ERRC 0x0369 321 #define PESDR1_460EX_L2ERRC 0x036A 322 #define PESDR1_460EX_L3ERRC 0x036B 323 #define PESDR0_460EX_IHS1 0x036C 324 #define PESDR0_460EX_IHS2 0x036D 325 326 /* 327 * 460SX additional DCRs 328 */ 329 #define PESDRn_460SX_RCEI 0x02 330 331 #define PESDR0_460SX_HSSL0DAMP 0x320 332 #define PESDR0_460SX_HSSL1DAMP 0x321 333 #define PESDR0_460SX_HSSL2DAMP 0x322 334 #define PESDR0_460SX_HSSL3DAMP 0x323 335 #define PESDR0_460SX_HSSL4DAMP 0x324 336 #define PESDR0_460SX_HSSL5DAMP 0x325 337 #define PESDR0_460SX_HSSL6DAMP 0x326 338 #define PESDR0_460SX_HSSL7DAMP 0x327 339 340 #define PESDR1_460SX_HSSL0DAMP 0x354 341 #define PESDR1_460SX_HSSL1DAMP 0x355 342 #define PESDR1_460SX_HSSL2DAMP 0x356 343 #define PESDR1_460SX_HSSL3DAMP 0x357 344 345 #define PESDR2_460SX_HSSL0DAMP 0x384 346 #define PESDR2_460SX_HSSL1DAMP 0x385 347 #define PESDR2_460SX_HSSL2DAMP 0x386 348 #define PESDR2_460SX_HSSL3DAMP 0x387 349 350 #define PESDR0_460SX_HSSL0COEFA 0x328 351 #define PESDR0_460SX_HSSL1COEFA 0x329 352 #define PESDR0_460SX_HSSL2COEFA 0x32A 353 #define PESDR0_460SX_HSSL3COEFA 0x32B 354 #define PESDR0_460SX_HSSL4COEFA 0x32C 355 #define PESDR0_460SX_HSSL5COEFA 0x32D 356 #define PESDR0_460SX_HSSL6COEFA 0x32E 357 #define PESDR0_460SX_HSSL7COEFA 0x32F 358 359 #define PESDR1_460SX_HSSL0COEFA 0x358 360 #define PESDR1_460SX_HSSL1COEFA 0x359 361 #define PESDR1_460SX_HSSL2COEFA 0x35A 362 #define PESDR1_460SX_HSSL3COEFA 0x35B 363 364 #define PESDR2_460SX_HSSL0COEFA 0x388 365 #define PESDR2_460SX_HSSL1COEFA 0x389 366 #define PESDR2_460SX_HSSL2COEFA 0x38A 367 #define PESDR2_460SX_HSSL3COEFA 0x38B 368 369 #define PESDR0_460SX_HSSL1CALDRV 0x339 370 #define PESDR1_460SX_HSSL1CALDRV 0x361 371 #define PESDR2_460SX_HSSL1CALDRV 0x391 372 373 #define PESDR0_460SX_HSSSLEW 0x338 374 #define PESDR1_460SX_HSSSLEW 0x360 375 #define PESDR2_460SX_HSSSLEW 0x390 376 377 #define PESDR0_460SX_HSSCTLSET 0x31E 378 #define PESDR1_460SX_HSSCTLSET 0x352 379 #define PESDR2_460SX_HSSCTLSET 0x382 380 381 #define PESDR0_460SX_RCSSET 0x304 382 #define PESDR1_460SX_RCSSET 0x344 383 #define PESDR2_460SX_RCSSET 0x374 384 /* 385 * Of the above, some are common offsets from the base 386 */ 387 #define PESDRn_UTLSET1 0x00 388 #define PESDRn_UTLSET2 0x01 389 #define PESDRn_DLPSET 0x02 390 #define PESDRn_LOOP 0x03 391 #define PESDRn_RCSSET 0x04 392 #define PESDRn_RCSSTS 0x05 393 394 /* 440spe only */ 395 #define PESDRn_440SPE_HSSL0SET1 0x06 396 #define PESDRn_440SPE_HSSL0SET2 0x07 397 #define PESDRn_440SPE_HSSL0STS 0x08 398 #define PESDRn_440SPE_HSSL1SET1 0x09 399 #define PESDRn_440SPE_HSSL1SET2 0x0a 400 #define PESDRn_440SPE_HSSL1STS 0x0b 401 #define PESDRn_440SPE_HSSL2SET1 0x0c 402 #define PESDRn_440SPE_HSSL2SET2 0x0d 403 #define PESDRn_440SPE_HSSL2STS 0x0e 404 #define PESDRn_440SPE_HSSL3SET1 0x0f 405 #define PESDRn_440SPE_HSSL3SET2 0x10 406 #define PESDRn_440SPE_HSSL3STS 0x11 407 408 /* 440spe port 0 only */ 409 #define PESDRn_440SPE_HSSL4SET1 0x12 410 #define PESDRn_440SPE_HSSL4SET2 0x13 411 #define PESDRn_440SPE_HSSL4STS 0x14 412 #define PESDRn_440SPE_HSSL5SET1 0x15 413 #define PESDRn_440SPE_HSSL5SET2 0x16 414 #define PESDRn_440SPE_HSSL5STS 0x17 415 #define PESDRn_440SPE_HSSL6SET1 0x18 416 #define PESDRn_440SPE_HSSL6SET2 0x19 417 #define PESDRn_440SPE_HSSL6STS 0x1a 418 #define PESDRn_440SPE_HSSL7SET1 0x1b 419 #define PESDRn_440SPE_HSSL7SET2 0x1c 420 #define PESDRn_440SPE_HSSL7STS 0x1d 421 422 /* 405ex only */ 423 #define PESDRn_405EX_PHYSET1 0x06 424 #define PESDRn_405EX_PHYSET2 0x07 425 #define PESDRn_405EX_PHYSTA 0x0c 426 427 /* 428 * UTL register offsets 429 */ 430 #define PEUTL_PBCTL 0x00 431 #define PEUTL_PBBSZ 0x20 432 #define PEUTL_OPDBSZ 0x68 433 #define PEUTL_IPHBSZ 0x70 434 #define PEUTL_IPDBSZ 0x78 435 #define PEUTL_OUTTR 0x90 436 #define PEUTL_INTR 0x98 437 #define PEUTL_PCTL 0xa0 438 #define PEUTL_RCSTA 0xB0 439 #define PEUTL_RCIRQEN 0xb8 440 441 /* 442 * Config space register offsets 443 */ 444 #define PECFG_ECRTCTL 0x074 445 446 #define PECFG_BAR0LMPA 0x210 447 #define PECFG_BAR0HMPA 0x214 448 #define PECFG_BAR1MPA 0x218 449 #define PECFG_BAR2LMPA 0x220 450 #define PECFG_BAR2HMPA 0x224 451 452 #define PECFG_PIMEN 0x33c 453 #define PECFG_PIM0LAL 0x340 454 #define PECFG_PIM0LAH 0x344 455 #define PECFG_PIM1LAL 0x348 456 #define PECFG_PIM1LAH 0x34c 457 #define PECFG_PIM01SAL 0x350 458 #define PECFG_PIM01SAH 0x354 459 460 #define PECFG_POM0LAL 0x380 461 #define PECFG_POM0LAH 0x384 462 #define PECFG_POM1LAL 0x388 463 #define PECFG_POM1LAH 0x38c 464 #define PECFG_POM2LAL 0x390 465 #define PECFG_POM2LAH 0x394 466 467 /* 460sx only */ 468 #define PECFG_460SX_DLLSTA 0x3f8 469 470 /* 460sx Bit Mappings */ 471 #define PECFG_460SX_DLLSTA_LINKUP 0x00000010 472 #define DCRO_PEGPL_460SX_OMR1MSKL_UOT 0x00000004 473 474 /* PEGPL Bit Mappings */ 475 #define DCRO_PEGPL_OMRxMSKL_VAL 0x00000001 476 #define DCRO_PEGPL_OMR1MSKL_UOT 0x00000002 477 #define DCRO_PEGPL_OMR3MSKL_IO 0x00000002 478 479 /* 476FPE */ 480 #define PCCFG_LCPA 0x270 481 #define PECFG_TLDLP 0x3F8 482 #define PECFG_TLDLP_LNKUP 0x00000008 483 #define PECFG_TLDLP_PRESENT 0x00000010 484 #define DCRO_PEGPL_476FPE_OMR1MSKL_UOT 0x00000004 485 486 /* SDR Bit Mappings */ 487 #define PESDRx_RCSSET_HLDPLB 0x10000000 488 #define PESDRx_RCSSET_RSTGU 0x01000000 489 #define PESDRx_RCSSET_RDY 0x00100000 490 #define PESDRx_RCSSET_RSTDL 0x00010000 491 #define PESDRx_RCSSET_RSTPYN 0x00001000 492 493 enum 494 { 495 PTYPE_ENDPOINT = 0x0, 496 PTYPE_LEGACY_ENDPOINT = 0x1, 497 PTYPE_ROOT_PORT = 0x4, 498 499 LNKW_X1 = 0x1, 500 LNKW_X4 = 0x4, 501 LNKW_X8 = 0x8 502 }; 503 504 505 #endif /* __PPC4XX_PCI_H__ */ 506
