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Searched refs:PD0 (Results 1 – 20 of 20) sorted by relevance

/Linux-v5.10/arch/arc/mm/
Dtlbex.S251 ; A one-word PTE entry is programmed as two-word TLB Entry [PD0:PD1] in mmu
252 ; (for PAE40, two-words PTE, while three-word TLB Entry [PD0:PD1:PD1HI])
272 lr r3,[ARC_REG_TLBPD0] ; MMU prepares PD0 with vaddr and asid
275 sr r3,[ARC_REG_TLBPD0] ; rewrite PD0
/Linux-v5.10/Documentation/hwmon/
Dmax197.rst47 7,6 PD1,PD0 Clock and Power-Down modes
/Linux-v5.10/arch/arm/boot/dts/
Dat91sam9m10g45ek.dts161 <AT91_PIOD 0 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PD0 periph B */
Dat91sam9g45.dtsi461 <AT91_PIOD 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD0 periph A */
Dsunxi-h3-h5.dtsi415 pins = "PD0", "PD1", "PD2", "PD3", "PD4",
Dsama5d3.dtsi723 AT91_PIOD 0 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD0 periph A MCI0_CDA with pullup */
Dsun9i-a80.dtsi997 pins = "PD0", "PD1", "PD2", "PD3",
Dsun6i-a31.dtsi679 pins = "PD0", "PD1", "PD2", "PD3",
Dsun7i-a20.dtsi939 pins = "PD0", "PD1", "PD2", "PD3", "PD4",
/Linux-v5.10/arch/mips/boot/dts/ingenic/
Dqi_lb60.dts343 pins = "PD0", "PD2";
/Linux-v5.10/arch/arm64/boot/dts/allwinner/
Dsun50i-a64.dtsi686 pins = "PD0", "PD1", "PD2", "PD3", "PD4",
757 pins = "PD0", "PD1", "PD2", "PD3";
782 pins = "PD0", "PD1";
Dsun50i-h6.dtsi309 pins = "PD0", "PD1", "PD2", "PD3", "PD4",
/Linux-v5.10/arch/powerpc/boot/dts/
Dkmeter1.dts223 3 0 1 0 1 0 /* TxD0 (PD0, out, f1) */
/Linux-v5.10/drivers/pinctrl/renesas/
Dpfc-shx3.c324 PINMUX_GPIO(PD0),
Dpfc-sh7786.c446 PINMUX_GPIO(PD0),
Dpfc-sh7785.c710 PINMUX_GPIO(PD0),
Dpfc-sh7203.c761 PINMUX_GPIO(PD0),
Dpfc-sh7264.c1129 PINMUX_GPIO(PD0),
Dpfc-sh7269.c1510 PINMUX_GPIO(PD0),
/Linux-v5.10/drivers/iommu/
Dmsm_iommu_hw-8xxx.h588 #define SET_PD0(b, c, v) SET_CONTEXT_FIELD(b, c, TTBCR, PD0, v)
775 #define GET_PD0(b, c) GET_CONTEXT_FIELD(b, c, TTBCR, PD0)
1155 #define PD0 (PD0_MASK << PD0_SHIFT) macro