Searched refs:PCI_BASE_ADDRESS_MEM_MASK (Results 1 – 25 of 31) sorted by relevance
12
317 plxphys = pci_resource_start(pdev,0) & PCI_BASE_ADDRESS_MEM_MASK; in pci200_pci_init_one()320 scaphys = pci_resource_start(pdev,2) & PCI_BASE_ADDRESS_MEM_MASK; in pci200_pci_init_one()323 ramphys = pci_resource_start(pdev,3) & PCI_BASE_ADDRESS_MEM_MASK; in pci200_pci_init_one()
332 plxphys = pci_resource_start(pdev, 0) & PCI_BASE_ADDRESS_MEM_MASK; in pc300_pci_init_one()335 scaphys = pci_resource_start(pdev, 2) & PCI_BASE_ADDRESS_MEM_MASK; in pc300_pci_init_one()338 ramphys = pci_resource_start(pdev, 3) & PCI_BASE_ADDRESS_MEM_MASK; in pc300_pci_init_one()
325 PCI_BASE_ADDRESS_MEM_MASK; in irongate_ioremap()345 PCI_BASE_ADDRESS_MEM_MASK) + IRONGATE_MEM); in irongate_ioremap()
161 aper_base = (aperturebase & PCI_BASE_ADDRESS_MEM_MASK); in amd64_configure()427 baseaddr&= ~PCI_BASE_ADDRESS_MEM_MASK; in uli_agp_init()496 apbar &= ~PCI_BASE_ADDRESS_MEM_MASK; in nforce3_agp_init()
179 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); in serverworks_create_gatt_table()274 temp = (temp & PCI_BASE_ADDRESS_MEM_MASK); in serverworks_configure()
65 mask = (u32)PCI_BASE_ADDRESS_MEM_MASK; in pci_std_update_resource()66 new |= res->flags & ~PCI_BASE_ADDRESS_MEM_MASK; in pci_std_update_resource()
143 flags = bar & ~PCI_BASE_ADDRESS_MEM_MASK; in decode_bar()226 l64 = l & PCI_BASE_ADDRESS_MEM_MASK; in __pci_read_base()227 sz64 = sz & PCI_BASE_ADDRESS_MEM_MASK; in __pci_read_base()228 mask64 = (u32)PCI_BASE_ADDRESS_MEM_MASK; in __pci_read_base()
847 new |= res->flags & ~PCI_BASE_ADDRESS_MEM_MASK; in pci_iov_update_resource()
244 & PCI_BASE_ADDRESS_MEM_MASK; in init_ohci1394_controller()
93 bar_size &= PCI_BASE_ADDRESS_MEM_MASK; in pciauto_setup_bars()
87 return (addr & PCI_BASE_ADDRESS_MEM_MASK) | flags; in pcie_bar_low_val()289 u64 mask = (~(size - 1) & PCI_BASE_ADDRESS_MEM_MASK) | flags; in xgene_pcie_set_ib_mask()
494 (phys1 & PCI_BASE_ADDRESS_MEM_MASK); in vmd_get_phys_offsets()496 (phys2 & PCI_BASE_ADDRESS_MEM_MASK); in vmd_get_phys_offsets()
413 size = (size & PCI_BASE_ADDRESS_MEM_MASK); in fixup_pmc551()452 if ((size &= PCI_BASE_ADDRESS_MEM_MASK) == 0) { in fixup_pmc551()
56 val64 = val & PCI_BASE_ADDRESS_MEM_MASK; in xdbc_map_pci_mmio()57 sz64 = sz & PCI_BASE_ADDRESS_MEM_MASK; in xdbc_map_pci_mmio()58 mask64 = PCI_BASE_ADDRESS_MEM_MASK; in xdbc_map_pci_mmio()
864 if (bar_val & ~PCI_BASE_ADDRESS_MEM_MASK) { in early_dbgp_init()
163 cfg_addr &= PCI_BASE_ADDRESS_MEM_MASK; in handle_pci_cfg_write()169 ~PCI_BASE_ADDRESS_MEM_MASK); in handle_pci_cfg_write()
320 cfg_addr &= PCI_BASE_ADDRESS_MEM_MASK; in handle_pci_cfg_write()327 ~PCI_BASE_ADDRESS_MEM_MASK); in handle_pci_cfg_write()
611 PCI_BASE_ADDRESS_MEM_MASK; in mdev_read_base()
1264 start_address &= PCI_BASE_ADDRESS_MEM_MASK; in unconfigure_boot_device()1278 start_address &= PCI_BASE_ADDRESS_MEM_MASK; in unconfigure_boot_device()1383 start_address &= PCI_BASE_ADDRESS_MEM_MASK; in unconfigure_boot_bridge()1395 start_address &= PCI_BASE_ADDRESS_MEM_MASK; in unconfigure_boot_bridge()
291 ep->fb_base_reg &= PCI_BASE_ADDRESS_MEM_MASK; in e3d_pci_register()
195 mask = ~PCI_BASE_ADDRESS_MEM_MASK; in bar_write()
531 PCI_BASE_ADDRESS_MEM_MASK; in intel_vgpu_get_bar_gpa()
109 #define PCI_BASE_ADDRESS_MEM_MASK (~0x0fUL) macro
648 addr &= PCI_BASE_ADDRESS_MEM_MASK; in apple_airport_reset()
923 base &= PCI_BASE_ADDRESS_MEM_MASK; in fsl_pci_immrbar_base()
