Searched refs:ORION5X_BRIDGE_VIRT_BASE (Results 1 – 3 of 3) sorted by relevance
14 #define CPU_CONF (ORION5X_BRIDGE_VIRT_BASE + 0x100)16 #define CPU_CTRL (ORION5X_BRIDGE_VIRT_BASE + 0x104)18 #define RSTOUTn_MASK (ORION5X_BRIDGE_VIRT_BASE + 0x108)21 #define CPU_SOFT_RESET (ORION5X_BRIDGE_VIRT_BASE + 0x10c)23 #define BRIDGE_CAUSE (ORION5X_BRIDGE_VIRT_BASE + 0x110)25 #define POWER_MNG_CTRL_REG (ORION5X_BRIDGE_VIRT_BASE + 0x11C)29 #define MAIN_IRQ_CAUSE (ORION5X_BRIDGE_VIRT_BASE + 0x200)31 #define MAIN_IRQ_MASK (ORION5X_BRIDGE_VIRT_BASE + 0x204)33 #define TIMER_VIRT_BASE (ORION5X_BRIDGE_VIRT_BASE + 0x300)
84 #define ORION5X_BRIDGE_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0x20000) macro
276 orion_time_init(ORION5X_BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR, in orion5x_timer_init()
