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Searched refs:OMAP1_IO_ADDRESS (Results 1 – 8 of 8) sorted by relevance

/Linux-v5.10/arch/arm/mach-omap1/
Dclock_data.c98 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
110 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_1),
132 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
151 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
162 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
175 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
188 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
212 .enable_reg = OMAP1_IO_ADDRESS(ARM_CKCTL),
298 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT3),
307 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT3),
[all …]
Dsram.S25 mov r2, #OMAP1_IO_ADDRESS(DPLL_CTL) & 0xff000000
26 orr r2, r2, #OMAP1_IO_ADDRESS(DPLL_CTL) & 0x00ff0000
27 orr r2, r2, #OMAP1_IO_ADDRESS(DPLL_CTL) & 0x0000ff00
29 mov r3, #OMAP1_IO_ADDRESS(ARM_CKCTL) & 0xff000000
30 orr r3, r3, #OMAP1_IO_ADDRESS(ARM_CKCTL) & 0x00ff0000
31 orr r3, r3, #OMAP1_IO_ADDRESS(ARM_CKCTL) & 0x0000ff00
Dio.c147 return __raw_readb(OMAP1_IO_ADDRESS(pa)); in omap_readb()
153 return __raw_readw(OMAP1_IO_ADDRESS(pa)); in omap_readw()
159 return __raw_readl(OMAP1_IO_ADDRESS(pa)); in omap_readl()
165 __raw_writeb(v, OMAP1_IO_ADDRESS(pa)); in omap_writeb()
171 __raw_writew(v, OMAP1_IO_ADDRESS(pa)); in omap_writew()
177 __raw_writel(v, OMAP1_IO_ADDRESS(pa)); in omap_writel()
Dpm.h42 #define CLKGEN_REG_ASM_BASE OMAP1_IO_ADDRESS(0xfffece00)
46 #define TCMIF_ASM_BASE OMAP1_IO_ADDRESS(0xfffecc00)
Dreset.c52 rs = __raw_readw(OMAP1_IO_ADDRESS(ARM_SYSST)); in omap1_get_reset_sources()
Dtime.c69 ((omap_mpu_timer_regs_t __iomem *)OMAP1_IO_ADDRESS(OMAP_MPU_TIMER_BASE + \
/Linux-v5.10/arch/arm/mach-omap1/include/mach/
Dmtd-xip.h28 ((volatile xip_omap_mpu_timer_regs_t*)OMAP1_IO_ADDRESS(OMAP_MPU_TIMER_BASE + \
Dhardware.h76 #define OMAP1_IO_ADDRESS(pa) IOMEM((pa) - OMAP1_IO_OFFSET) macro