Searched refs:MVPP22_XLG_CTRL0_REG (Results 1 – 2 of 2) sorted by relevance
1440 val = readl(port->base + MVPP22_XLG_CTRL0_REG); in mvpp2_port_enable()1443 writel(val, port->base + MVPP22_XLG_CTRL0_REG); in mvpp2_port_enable()1458 val = readl(port->base + MVPP22_XLG_CTRL0_REG); in mvpp2_port_disable()1460 writel(val, port->base + MVPP22_XLG_CTRL0_REG); in mvpp2_port_disable()1821 val = readl(port->base + MVPP22_XLG_CTRL0_REG) & in mvpp2_mac_reset_assert()1823 writel(val, port->base + MVPP22_XLG_CTRL0_REG); in mvpp2_mac_reset_assert()5707 val = readl(port->base + MVPP22_XLG_CTRL0_REG); in mvpp2_xlg_pcs_get_state()5930 mvpp2_modify(port->base + MVPP22_XLG_CTRL0_REG, in mvpp2_xlg_config()5941 val = readl(port->base + MVPP22_XLG_CTRL0_REG); in mvpp2_xlg_config()6029 mvpp2_modify(port->base + MVPP22_XLG_CTRL0_REG, in mvpp2__mac_prepare()[all …]
475 #define MVPP22_XLG_CTRL0_REG 0x100 macro
