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Searched refs:MLXSW_CORE_RES_GET (Results 1 – 23 of 23) sorted by relevance

/Linux-v5.10/drivers/net/ethernet/mellanox/mlxsw/
Dspectrum_policer.c92 family->start_index = MLXSW_CORE_RES_GET(core, MAX_CPU_POLICERS); in mlxsw_sp_policer_single_rate_family_init()
93 family->end_index = MLXSW_CORE_RES_GET(core, MAX_GLOBAL_POLICERS); in mlxsw_sp_policer_single_rate_family_init()
415 global_policers = MLXSW_CORE_RES_GET(mlxsw_core, MAX_GLOBAL_POLICERS); in mlxsw_sp_policer_resources_register()
416 cpu_policers = MLXSW_CORE_RES_GET(mlxsw_core, MAX_CPU_POLICERS); in mlxsw_sp_policer_resources_register()
Dspectrum1_kvdl.c393 kvdl_max_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE) - in mlxsw_sp1_kvdl_resources_register()
394 MLXSW_CORE_RES_GET(mlxsw_core, KVD_SINGLE_MIN_SIZE) - in mlxsw_sp1_kvdl_resources_register()
395 MLXSW_CORE_RES_GET(mlxsw_core, KVD_DOUBLE_MIN_SIZE); in mlxsw_sp1_kvdl_resources_register()
Dspectrum_dpipe.c213 rif_count = MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_RIFS); in mlxsw_sp_dpipe_table_erif_entries_dump()
263 for (i = 0; i < MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_RIFS); i++) { in mlxsw_sp_dpipe_table_erif_counters_update()
283 return MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_RIFS); in mlxsw_sp_dpipe_table_erif_size_get()
552 rif_count = MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_RIFS); in mlxsw_sp_dpipe_table_host_entries_get()
559 for (; i < MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_RIFS); i++) { in mlxsw_sp_dpipe_table_host_entries_get()
667 for (i = 0; i < MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_RIFS); i++) { in mlxsw_sp_dpipe_table_host_counters_update()
706 for (i = 0; i < MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_RIFS); i++) { in mlxsw_sp_dpipe_table_host_size_get()
Dspectrum_cnt.c262 pool_size = MLXSW_CORE_RES_GET(mlxsw_core, COUNTER_POOL_SIZE); in mlxsw_sp_counter_resources_register()
263 bank_size = MLXSW_CORE_RES_GET(mlxsw_core, COUNTER_BANK_SIZE); in mlxsw_sp_counter_resources_register()
Dspectrum.c2247 max_cpu_policers = MLXSW_CORE_RES_GET(mlxsw_core, MAX_CPU_POLICERS); in mlxsw_sp_cpu_policers_set()
2287 max_trap_groups = MLXSW_CORE_RES_GET(mlxsw_core, MAX_TRAP_GROUPS); in mlxsw_sp_trap_groups_set()
2288 max_cpu_policers = MLXSW_CORE_RES_GET(mlxsw_core, MAX_CPU_POLICERS); in mlxsw_sp_trap_groups_set()
2368 max_policers = MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_CPU_POLICERS); in mlxsw_sp_traps_init()
2442 mlxsw_sp->lags = kcalloc(MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_LAG), in mlxsw_sp_lag_init()
2899 u32 single_size_min = MLXSW_CORE_RES_GET(mlxsw_core, in mlxsw_sp_resource_size_params_prepare()
2901 u32 double_size_min = MLXSW_CORE_RES_GET(mlxsw_core, in mlxsw_sp_resource_size_params_prepare()
2903 u32 kvd_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE); in mlxsw_sp_resource_size_params_prepare()
2948 kvd_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE); in mlxsw_sp1_resources_kvd_register()
3003 kvd_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE); in mlxsw_sp2_resources_kvd_register()
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Dspectrum_acl_erp.c1503 size = MLXSW_CORE_RES_GET(mlxsw_sp->core, ACL_ERPT_ENTRIES_2KB); in mlxsw_sp_acl_erp_tables_sizes_query()
1506 size = MLXSW_CORE_RES_GET(mlxsw_sp->core, ACL_ERPT_ENTRIES_4KB); in mlxsw_sp_acl_erp_tables_sizes_query()
1509 size = MLXSW_CORE_RES_GET(mlxsw_sp->core, ACL_ERPT_ENTRIES_8KB); in mlxsw_sp_acl_erp_tables_sizes_query()
1512 size = MLXSW_CORE_RES_GET(mlxsw_sp->core, ACL_ERPT_ENTRIES_12KB); in mlxsw_sp_acl_erp_tables_sizes_query()
1527 erpt_bank_size = MLXSW_CORE_RES_GET(mlxsw_sp->core, in mlxsw_sp_acl_erp_tables_init()
1529 erp_core->num_erp_banks = MLXSW_CORE_RES_GET(mlxsw_sp->core, in mlxsw_sp_acl_erp_tables_init()
Dspectrum_acl_bloom_filter.c253 bf_bank_size = 1 << MLXSW_CORE_RES_GET(mlxsw_sp->core, ACL_MAX_BF_LOG); in mlxsw_sp_acl_bf_init()
Dspectrum_acl_flex_actions.c226 mlxsw_sp->afa = mlxsw_afa_create(MLXSW_CORE_RES_GET(mlxsw_sp->core, in mlxsw_sp_afa_init()
Dspectrum_acl_tcam.c47 max_tcam_regions = MLXSW_CORE_RES_GET(mlxsw_sp->core, in mlxsw_sp_acl_tcam_init()
49 max_regions = MLXSW_CORE_RES_GET(mlxsw_sp->core, ACL_MAX_REGIONS); in mlxsw_sp_acl_tcam_init()
61 max_groups = MLXSW_CORE_RES_GET(mlxsw_sp->core, ACL_MAX_GROUPS); in mlxsw_sp_acl_tcam_init()
69 tcam->max_group_size = MLXSW_CORE_RES_GET(mlxsw_sp->core, in mlxsw_sp_acl_tcam_init()
111 max_priority = MLXSW_CORE_RES_GET(mlxsw_sp->core, KVD_SIZE) - 1; in mlxsw_sp_acl_tcam_priority_get()
Dspectrum_acl_ctcam.c129 max_tcam_rules = MLXSW_CORE_RES_GET(mlxsw_sp->core, ACL_MAX_TCAM_RULES); in mlxsw_sp_acl_ctcam_region_parman_resize()
Dspectrum_acl_atcam.c129 max_lkey_id = MLXSW_CORE_RES_GET(mlxsw_sp->core, ACL_MAX_LARGE_KEY_ID); in mlxsw_sp_acl_atcam_region_12kb_init()
284 max_regions = MLXSW_CORE_RES_GET(mlxsw_sp->core, ACL_MAX_REGIONS); in mlxsw_sp_acl_atcam_region_associate()
Dspectrum1_mr_tcam.c206 max_tcam_rules = MLXSW_CORE_RES_GET(mlxsw_sp->core, ACL_MAX_TCAM_RULES); in mlxsw_sp1_mr_tcam_region_parman_resize()
Dspectrum_buffers.c1240 mlxsw_sp->sb->cell_size = MLXSW_CORE_RES_GET(mlxsw_sp->core, CELL_SIZE); in mlxsw_sp_buffers_init()
1241 mlxsw_sp->sb->sb_size = MLXSW_CORE_RES_GET(mlxsw_sp->core, in mlxsw_sp_buffers_init()
1243 max_headroom_size = MLXSW_CORE_RES_GET(mlxsw_sp->core, in mlxsw_sp_buffers_init()
1358 if (size > MLXSW_CORE_RES_GET(mlxsw_sp->core, in mlxsw_sp_sb_pool_set()
Dspectrum_nve.c962 max = MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_NVE_MC_ENTRIES_IPV4); in mlxsw_sp_nve_resources_query()
964 max = MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_NVE_MC_ENTRIES_IPV6); in mlxsw_sp_nve_resources_query()
Dcore.c103 mlxsw_core->max_ports = MLXSW_CORE_RES_GET(mlxsw_core, in mlxsw_ports_init()
1915 MLXSW_CORE_RES_GET(mlxsw_core, MAX_LAG) * in __mlxsw_core_bus_device_register()
1916 MLXSW_CORE_RES_GET(mlxsw_core, MAX_LAG_MEMBERS); in __mlxsw_core_bus_device_register()
2659 return MLXSW_CORE_RES_GET(mlxsw_core, MAX_LAG_MEMBERS) * lag_id + in mlxsw_core_lag_mapping_index()
2688 for (i = 0; i < MLXSW_CORE_RES_GET(mlxsw_core, MAX_LAG_MEMBERS); i++) { in mlxsw_core_lag_mapping_clear()
Dspectrum_router.c612 max_trees = MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_LPM_TREES); in mlxsw_sp_lpm_init()
676 for (i = 0; i < MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_VRS); i++) { in mlxsw_sp_vr_find_unused()
722 for (i = 0; i < MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_VRS); i++) { in mlxsw_sp_vr_find()
893 for (i = 0; i < MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_VRS); i++) { in mlxsw_sp_vrs_lpm_tree_replace()
931 max_vrs = MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_VRS); in mlxsw_sp_vrs_init()
5676 for (i = 0; i < MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_VRS); i++) { in __mlxsw_sp_router_set_abort_trap()
5861 for (i = 0; i < MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_VRS); i++) { in mlxsw_sp_router_fib_flush()
6295 for (i = 0; i < MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_RIFS); i++) in mlxsw_sp_rif_find_by_dev()
6428 for (i = 0; i < MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_RIFS); i++) { in mlxsw_sp_rif_index_alloc()
7005 for (i = 0; i < MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_RIFS); i++) { in mlxsw_sp_router_port_check_rif_addr()
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Dpci.c1485 MLXSW_CORE_RES_GET(mlxsw_core, CQE_V2)) in mlxsw_pci_init()
1488 MLXSW_CORE_RES_GET(mlxsw_core, CQE_V1)) in mlxsw_pci_init()
1491 MLXSW_CORE_RES_GET(mlxsw_core, CQE_V0)) || in mlxsw_pci_init()
Dcore.h400 #define MLXSW_CORE_RES_GET(mlxsw_core, short_res_id) \ macro
Dspectrum_mr_tcam.c36 int erif_list_entries = MLXSW_CORE_RES_GET(mlxsw_sp->core, in mlxsw_sp_mr_erif_sublist_full()
Dspectrum_acl.c943 acl->afk = mlxsw_afk_create(MLXSW_CORE_RES_GET(mlxsw_sp->core, in mlxsw_sp_acl_init()
Dspectrum_switchdev.c1544 max_lag_members = MLXSW_CORE_RES_GET(mlxsw_sp->core, in mlxsw_sp_bridge_port_get_ports_bitmap()
1967 max_lag_members = MLXSW_CORE_RES_GET(mlxsw_sp->core, in mlxsw_sp_lag_rep_port()
Dspectrum_span.c89 entries_count = MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_SPAN); in mlxsw_sp_span_init()
Dspectrum_qdisc.c449 if (p->max > MLXSW_CORE_RES_GET(mlxsw_sp->core, in mlxsw_sp_qdisc_red_check_params()