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Searched refs:LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_POL__SHIFT (Results 1 – 10 of 10) sorted by relevance

/Linux-v5.10/drivers/gpu/drm/amd/include/asic_reg/dce/
Ddce_6_0_sh_mask.h7617 #define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_POL__SHIFT 0x00000012 macro
Ddce_8_0_sh_mask.h3194 #define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_POL__SHIFT 0x12 macro
Ddce_10_0_sh_mask.h3116 #define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_POL__SHIFT 0x12 macro
Ddce_11_0_sh_mask.h3186 #define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_POL__SHIFT 0x12 macro
Ddce_11_2_sh_mask.h3434 #define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_POL__SHIFT 0x12 macro
Ddce_12_0_sh_mask.h9253 #define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_POL__SHIFT … macro
/Linux-v5.10/drivers/gpu/drm/amd/include/asic_reg/dcn/
Ddcn_2_1_0_sh_mask.h43236 #define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_POL__SHIFT … macro
Ddcn_1_0_sh_mask.h40002 #define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_POL__SHIFT … macro
Ddcn_3_0_0_sh_mask.h49113 #define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_POL__SHIFT … macro
Ddcn_2_0_0_sh_mask.h48745 #define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_POL__SHIFT … macro