1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 #ifndef DC_TYPES_H_ 26 #define DC_TYPES_H_ 27 28 /* AND EdidUtility only needs a portion 29 * of this file, including the rest only 30 * causes additional issues. 31 */ 32 #include "os_types.h" 33 #include "fixed31_32.h" 34 #include "irq_types.h" 35 #include "dc_dp_types.h" 36 #include "dc_hw_types.h" 37 #include "dal_types.h" 38 #include "grph_object_defs.h" 39 40 #ifdef CONFIG_DRM_AMD_DC_HDCP 41 #include "dm_cp_psp.h" 42 #endif 43 44 /* forward declarations */ 45 struct dc_plane_state; 46 struct dc_stream_state; 47 struct dc_link; 48 struct dc_sink; 49 struct dal; 50 struct dc_dmub_srv; 51 52 /******************************** 53 * Environment definitions 54 ********************************/ 55 enum dce_environment { 56 DCE_ENV_PRODUCTION_DRV = 0, 57 /* Emulation on FPGA, in "Maximus" System. 58 * This environment enforces that *only* DC registers accessed. 59 * (access to non-DC registers will hang FPGA) */ 60 DCE_ENV_FPGA_MAXIMUS, 61 /* Emulation on real HW or on FPGA. Used by Diagnostics, enforces 62 * requirements of Diagnostics team. */ 63 DCE_ENV_DIAG, 64 /* 65 * Guest VM system, DC HW may exist but is not virtualized and 66 * should not be used. SW support for VDI only. 67 */ 68 DCE_ENV_VIRTUAL_HW 69 }; 70 71 /* Note: use these macro definitions instead of direct comparison! */ 72 #define IS_FPGA_MAXIMUS_DC(dce_environment) \ 73 (dce_environment == DCE_ENV_FPGA_MAXIMUS) 74 75 #define IS_DIAG_DC(dce_environment) \ 76 (IS_FPGA_MAXIMUS_DC(dce_environment) || (dce_environment == DCE_ENV_DIAG)) 77 78 struct hw_asic_id { 79 uint32_t chip_id; 80 uint32_t chip_family; 81 uint32_t pci_revision_id; 82 uint32_t hw_internal_rev; 83 uint32_t vram_type; 84 uint32_t vram_width; 85 uint32_t feature_flags; 86 uint32_t fake_paths_num; 87 void *atombios_base_address; 88 }; 89 90 struct dc_perf_trace { 91 unsigned long read_count; 92 unsigned long write_count; 93 unsigned long last_entry_read; 94 unsigned long last_entry_write; 95 }; 96 97 struct dc_context { 98 struct dc *dc; 99 100 void *driver_context; /* e.g. amdgpu_device */ 101 struct dc_perf_trace *perf_trace; 102 void *cgs_device; 103 104 enum dce_environment dce_environment; 105 struct hw_asic_id asic_id; 106 107 /* todo: below should probably move to dc. to facilitate removal 108 * of AS we will store these here 109 */ 110 enum dce_version dce_version; 111 struct dc_bios *dc_bios; 112 bool created_bios; 113 struct gpio_service *gpio_service; 114 uint32_t dc_sink_id_count; 115 uint32_t dc_stream_id_count; 116 uint64_t fbc_gpu_addr; 117 struct dc_dmub_srv *dmub_srv; 118 119 #ifdef CONFIG_DRM_AMD_DC_HDCP 120 struct cp_psp cp_psp; 121 #endif 122 }; 123 124 125 #define DC_MAX_EDID_BUFFER_SIZE 1280 126 #define DC_EDID_BLOCK_SIZE 128 127 #define MAX_SURFACE_NUM 4 128 #define NUM_PIXEL_FORMATS 10 129 #define MAX_REPEATER_CNT 8 130 131 #include "dc_ddc_types.h" 132 133 enum tiling_mode { 134 TILING_MODE_INVALID, 135 TILING_MODE_LINEAR, 136 TILING_MODE_TILED, 137 TILING_MODE_COUNT 138 }; 139 140 enum view_3d_format { 141 VIEW_3D_FORMAT_NONE = 0, 142 VIEW_3D_FORMAT_FRAME_SEQUENTIAL, 143 VIEW_3D_FORMAT_SIDE_BY_SIDE, 144 VIEW_3D_FORMAT_TOP_AND_BOTTOM, 145 VIEW_3D_FORMAT_COUNT, 146 VIEW_3D_FORMAT_FIRST = VIEW_3D_FORMAT_FRAME_SEQUENTIAL 147 }; 148 149 enum plane_stereo_format { 150 PLANE_STEREO_FORMAT_NONE = 0, 151 PLANE_STEREO_FORMAT_SIDE_BY_SIDE = 1, 152 PLANE_STEREO_FORMAT_TOP_AND_BOTTOM = 2, 153 PLANE_STEREO_FORMAT_FRAME_ALTERNATE = 3, 154 PLANE_STEREO_FORMAT_ROW_INTERLEAVED = 5, 155 PLANE_STEREO_FORMAT_COLUMN_INTERLEAVED = 6, 156 PLANE_STEREO_FORMAT_CHECKER_BOARD = 7 157 }; 158 159 /* TODO: Find way to calculate number of bits 160 * Please increase if pixel_format enum increases 161 * num from PIXEL_FORMAT_INDEX8 to PIXEL_FORMAT_444BPP32 162 */ 163 164 enum dc_edid_connector_type { 165 DC_EDID_CONNECTOR_UNKNOWN = 0, 166 DC_EDID_CONNECTOR_ANALOG = 1, 167 DC_EDID_CONNECTOR_DIGITAL = 10, 168 DC_EDID_CONNECTOR_DVI = 11, 169 DC_EDID_CONNECTOR_HDMIA = 12, 170 DC_EDID_CONNECTOR_MDDI = 14, 171 DC_EDID_CONNECTOR_DISPLAYPORT = 15 172 }; 173 174 enum dc_edid_status { 175 EDID_OK, 176 EDID_BAD_INPUT, 177 EDID_NO_RESPONSE, 178 EDID_BAD_CHECKSUM, 179 EDID_THE_SAME, 180 EDID_FALL_BACK, 181 }; 182 183 enum act_return_status { 184 ACT_SUCCESS, 185 ACT_LINK_LOST, 186 ACT_FAILED 187 }; 188 189 /* audio capability from EDID*/ 190 struct dc_cea_audio_mode { 191 uint8_t format_code; /* ucData[0] [6:3]*/ 192 uint8_t channel_count; /* ucData[0] [2:0]*/ 193 uint8_t sample_rate; /* ucData[1]*/ 194 union { 195 uint8_t sample_size; /* for LPCM*/ 196 /* for Audio Formats 2-8 (Max bit rate divided by 8 kHz)*/ 197 uint8_t max_bit_rate; 198 uint8_t audio_codec_vendor_specific; /* for Audio Formats 9-15*/ 199 }; 200 }; 201 202 struct dc_edid { 203 uint32_t length; 204 uint8_t raw_edid[DC_MAX_EDID_BUFFER_SIZE]; 205 }; 206 207 /* When speaker location data block is not available, DEFAULT_SPEAKER_LOCATION 208 * is used. In this case we assume speaker location are: front left, front 209 * right and front center. */ 210 #define DEFAULT_SPEAKER_LOCATION 5 211 212 #define DC_MAX_AUDIO_DESC_COUNT 16 213 214 #define AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS 20 215 216 union display_content_support { 217 unsigned int raw; 218 struct { 219 unsigned int valid_content_type :1; 220 unsigned int game_content :1; 221 unsigned int cinema_content :1; 222 unsigned int photo_content :1; 223 unsigned int graphics_content :1; 224 unsigned int reserved :27; 225 } bits; 226 }; 227 228 struct dc_panel_patch { 229 unsigned int dppowerup_delay; 230 unsigned int extra_t12_ms; 231 unsigned int extra_delay_backlight_off; 232 unsigned int extra_t7_ms; 233 unsigned int skip_scdc_overwrite; 234 unsigned int delay_ignore_msa; 235 unsigned int disable_fec; 236 unsigned int extra_t3_ms; 237 }; 238 239 struct dc_edid_caps { 240 /* sink identification */ 241 uint16_t manufacturer_id; 242 uint16_t product_id; 243 uint32_t serial_number; 244 uint8_t manufacture_week; 245 uint8_t manufacture_year; 246 uint8_t display_name[AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS]; 247 248 /* audio caps */ 249 uint8_t speaker_flags; 250 uint32_t audio_mode_count; 251 struct dc_cea_audio_mode audio_modes[DC_MAX_AUDIO_DESC_COUNT]; 252 uint32_t audio_latency; 253 uint32_t video_latency; 254 255 union display_content_support content_support; 256 257 uint8_t qs_bit; 258 uint8_t qy_bit; 259 260 uint32_t max_tmds_clk_mhz; 261 262 /*HDMI 2.0 caps*/ 263 bool lte_340mcsc_scramble; 264 265 bool edid_hdmi; 266 bool hdr_supported; 267 268 struct dc_panel_patch panel_patch; 269 }; 270 271 struct view { 272 uint32_t width; 273 uint32_t height; 274 }; 275 276 struct dc_mode_flags { 277 /* note: part of refresh rate flag*/ 278 uint32_t INTERLACE :1; 279 /* native display timing*/ 280 uint32_t NATIVE :1; 281 /* preferred is the recommended mode, one per display */ 282 uint32_t PREFERRED :1; 283 /* true if this mode should use reduced blanking timings 284 *_not_ related to the Reduced Blanking adjustment*/ 285 uint32_t REDUCED_BLANKING :1; 286 /* note: part of refreshrate flag*/ 287 uint32_t VIDEO_OPTIMIZED_RATE :1; 288 /* should be reported to upper layers as mode_flags*/ 289 uint32_t PACKED_PIXEL_FORMAT :1; 290 /*< preferred view*/ 291 uint32_t PREFERRED_VIEW :1; 292 /* this timing should be used only in tiled mode*/ 293 uint32_t TILED_MODE :1; 294 uint32_t DSE_MODE :1; 295 /* Refresh rate divider when Miracast sink is using a 296 different rate than the output display device 297 Must be zero for wired displays and non-zero for 298 Miracast displays*/ 299 uint32_t MIRACAST_REFRESH_DIVIDER; 300 }; 301 302 303 enum dc_timing_source { 304 TIMING_SOURCE_UNDEFINED, 305 306 /* explicitly specifed by user, most important*/ 307 TIMING_SOURCE_USER_FORCED, 308 TIMING_SOURCE_USER_OVERRIDE, 309 TIMING_SOURCE_CUSTOM, 310 TIMING_SOURCE_EXPLICIT, 311 312 /* explicitly specified by the display device, more important*/ 313 TIMING_SOURCE_EDID_CEA_SVD_3D, 314 TIMING_SOURCE_EDID_CEA_SVD_PREFERRED, 315 TIMING_SOURCE_EDID_CEA_SVD_420, 316 TIMING_SOURCE_EDID_DETAILED, 317 TIMING_SOURCE_EDID_ESTABLISHED, 318 TIMING_SOURCE_EDID_STANDARD, 319 TIMING_SOURCE_EDID_CEA_SVD, 320 TIMING_SOURCE_EDID_CVT_3BYTE, 321 TIMING_SOURCE_EDID_4BYTE, 322 TIMING_SOURCE_VBIOS, 323 TIMING_SOURCE_CV, 324 TIMING_SOURCE_TV, 325 TIMING_SOURCE_HDMI_VIC, 326 327 /* implicitly specified by display device, still safe but less important*/ 328 TIMING_SOURCE_DEFAULT, 329 330 /* only used for custom base modes */ 331 TIMING_SOURCE_CUSTOM_BASE, 332 333 /* these timing might not work, least important*/ 334 TIMING_SOURCE_RANGELIMIT, 335 TIMING_SOURCE_OS_FORCED, 336 TIMING_SOURCE_IMPLICIT, 337 338 /* only used by default mode list*/ 339 TIMING_SOURCE_BASICMODE, 340 341 TIMING_SOURCE_COUNT 342 }; 343 344 345 struct stereo_3d_features { 346 bool supported ; 347 bool allTimings ; 348 bool cloneMode ; 349 bool scaling ; 350 bool singleFrameSWPacked; 351 }; 352 353 enum dc_timing_support_method { 354 TIMING_SUPPORT_METHOD_UNDEFINED, 355 TIMING_SUPPORT_METHOD_EXPLICIT, 356 TIMING_SUPPORT_METHOD_IMPLICIT, 357 TIMING_SUPPORT_METHOD_NATIVE 358 }; 359 360 struct dc_mode_info { 361 uint32_t pixel_width; 362 uint32_t pixel_height; 363 uint32_t field_rate; 364 /* Vertical refresh rate for progressive modes. 365 * Field rate for interlaced modes.*/ 366 367 enum dc_timing_standard timing_standard; 368 enum dc_timing_source timing_source; 369 struct dc_mode_flags flags; 370 }; 371 372 enum dc_power_state { 373 DC_POWER_STATE_ON = 1, 374 DC_POWER_STATE_STANDBY, 375 DC_POWER_STATE_SUSPEND, 376 DC_POWER_STATE_OFF 377 }; 378 379 /* DC PowerStates */ 380 enum dc_video_power_state { 381 DC_VIDEO_POWER_UNSPECIFIED = 0, 382 DC_VIDEO_POWER_ON = 1, 383 DC_VIDEO_POWER_STANDBY, 384 DC_VIDEO_POWER_SUSPEND, 385 DC_VIDEO_POWER_OFF, 386 DC_VIDEO_POWER_HIBERNATE, 387 DC_VIDEO_POWER_SHUTDOWN, 388 DC_VIDEO_POWER_ULPS, /* BACO or Ultra-Light-Power-State */ 389 DC_VIDEO_POWER_AFTER_RESET, 390 DC_VIDEO_POWER_MAXIMUM 391 }; 392 393 enum dc_acpi_cm_power_state { 394 DC_ACPI_CM_POWER_STATE_D0 = 1, 395 DC_ACPI_CM_POWER_STATE_D1 = 2, 396 DC_ACPI_CM_POWER_STATE_D2 = 4, 397 DC_ACPI_CM_POWER_STATE_D3 = 8 398 }; 399 400 enum dc_connection_type { 401 dc_connection_none, 402 dc_connection_single, 403 dc_connection_mst_branch, 404 dc_connection_active_dongle 405 }; 406 407 struct dc_csc_adjustments { 408 struct fixed31_32 contrast; 409 struct fixed31_32 saturation; 410 struct fixed31_32 brightness; 411 struct fixed31_32 hue; 412 }; 413 414 enum dpcd_downstream_port_max_bpc { 415 DOWN_STREAM_MAX_8BPC = 0, 416 DOWN_STREAM_MAX_10BPC, 417 DOWN_STREAM_MAX_12BPC, 418 DOWN_STREAM_MAX_16BPC 419 }; 420 421 422 enum link_training_offset { 423 DPRX = 0, 424 LTTPR_PHY_REPEATER1 = 1, 425 LTTPR_PHY_REPEATER2 = 2, 426 LTTPR_PHY_REPEATER3 = 3, 427 LTTPR_PHY_REPEATER4 = 4, 428 LTTPR_PHY_REPEATER5 = 5, 429 LTTPR_PHY_REPEATER6 = 6, 430 LTTPR_PHY_REPEATER7 = 7, 431 LTTPR_PHY_REPEATER8 = 8 432 }; 433 434 struct dc_lttpr_caps { 435 union dpcd_rev revision; 436 uint8_t mode; 437 uint8_t max_lane_count; 438 uint8_t max_link_rate; 439 uint8_t phy_repeater_cnt; 440 uint8_t max_ext_timeout; 441 uint8_t aux_rd_interval[MAX_REPEATER_CNT - 1]; 442 }; 443 444 struct dc_dongle_caps { 445 /* dongle type (DP converter, CV smart dongle) */ 446 enum display_dongle_type dongle_type; 447 bool extendedCapValid; 448 /* If dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER, 449 indicates 'Frame Sequential-to-lllFrame Pack' conversion capability.*/ 450 bool is_dp_hdmi_s3d_converter; 451 bool is_dp_hdmi_ycbcr422_pass_through; 452 bool is_dp_hdmi_ycbcr420_pass_through; 453 bool is_dp_hdmi_ycbcr422_converter; 454 bool is_dp_hdmi_ycbcr420_converter; 455 uint32_t dp_hdmi_max_bpc; 456 uint32_t dp_hdmi_max_pixel_clk_in_khz; 457 }; 458 /* Scaling format */ 459 enum scaling_transformation { 460 SCALING_TRANSFORMATION_UNINITIALIZED, 461 SCALING_TRANSFORMATION_IDENTITY = 0x0001, 462 SCALING_TRANSFORMATION_CENTER_TIMING = 0x0002, 463 SCALING_TRANSFORMATION_FULL_SCREEN_SCALE = 0x0004, 464 SCALING_TRANSFORMATION_PRESERVE_ASPECT_RATIO_SCALE = 0x0008, 465 SCALING_TRANSFORMATION_DAL_DECIDE = 0x0010, 466 SCALING_TRANSFORMATION_INVALID = 0x80000000, 467 468 /* Flag the first and last */ 469 SCALING_TRANSFORMATION_BEGING = SCALING_TRANSFORMATION_IDENTITY, 470 SCALING_TRANSFORMATION_END = 471 SCALING_TRANSFORMATION_PRESERVE_ASPECT_RATIO_SCALE 472 }; 473 474 enum display_content_type { 475 DISPLAY_CONTENT_TYPE_NO_DATA = 0, 476 DISPLAY_CONTENT_TYPE_GRAPHICS = 1, 477 DISPLAY_CONTENT_TYPE_PHOTO = 2, 478 DISPLAY_CONTENT_TYPE_CINEMA = 4, 479 DISPLAY_CONTENT_TYPE_GAME = 8 480 }; 481 482 #if defined(CONFIG_DRM_AMD_DC_DCN3_0) 483 enum cm_gamut_adjust_type { 484 CM_GAMUT_ADJUST_TYPE_BYPASS = 0, 485 CM_GAMUT_ADJUST_TYPE_HW, /* without adjustments */ 486 CM_GAMUT_ADJUST_TYPE_SW /* use adjustments */ 487 }; 488 489 struct cm_grph_csc_adjustment { 490 struct fixed31_32 temperature_matrix[12]; 491 enum cm_gamut_adjust_type gamut_adjust_type; 492 enum cm_gamut_coef_format gamut_coef_format; 493 }; 494 #endif 495 /* writeback */ 496 struct dwb_stereo_params { 497 bool stereo_enabled; /* false: normal mode, true: 3D stereo */ 498 enum dwb_stereo_type stereo_type; /* indicates stereo format */ 499 bool stereo_polarity; /* indicates left eye or right eye comes first in stereo mode */ 500 enum dwb_stereo_eye_select stereo_eye_select; /* indicate which eye should be captured */ 501 }; 502 503 struct dc_dwb_cnv_params { 504 unsigned int src_width; /* input active width */ 505 unsigned int src_height; /* input active height (half-active height in interlaced mode) */ 506 unsigned int crop_width; /* cropped window width at cnv output */ 507 bool crop_en; /* window cropping enable in cnv */ 508 unsigned int crop_height; /* cropped window height at cnv output */ 509 unsigned int crop_x; /* cropped window start x value at cnv output */ 510 unsigned int crop_y; /* cropped window start y value at cnv output */ 511 enum dwb_cnv_out_bpc cnv_out_bpc; /* cnv output pixel depth - 8bpc or 10bpc */ 512 #if defined(CONFIG_DRM_AMD_DC_DCN3_0) 513 enum dwb_out_format fc_out_format; /* dwb output pixel format - 2101010 or 16161616 and ARGB or RGBA */ 514 enum dwb_out_denorm out_denorm_mode;/* dwb output denormalization mode */ 515 unsigned int out_max_pix_val;/* pixel values greater than out_max_pix_val are clamped to out_max_pix_val */ 516 unsigned int out_min_pix_val;/* pixel values less than out_min_pix_val are clamped to out_min_pix_val */ 517 #endif 518 }; 519 520 struct dc_dwb_params { 521 #if defined(CONFIG_DRM_AMD_DC_DCN3_0) 522 unsigned int dwbscl_black_color; /* must be in FP1.5.10 */ 523 unsigned int hdr_mult; /* must be in FP1.6.12 */ 524 struct cm_grph_csc_adjustment csc_params; 525 struct dwb_stereo_params stereo_params; 526 #endif 527 struct dc_dwb_cnv_params cnv_params; /* CNV source size and cropping window parameters */ 528 unsigned int dest_width; /* Destination width */ 529 unsigned int dest_height; /* Destination height */ 530 enum dwb_scaler_mode out_format; /* default = YUV420 - TODO: limit this to 0 and 1 on dcn3 */ 531 enum dwb_output_depth output_depth; /* output pixel depth - 8bpc or 10bpc */ 532 enum dwb_capture_rate capture_rate; /* controls the frame capture rate */ 533 struct scaling_taps scaler_taps; /* Scaling taps */ 534 enum dwb_subsample_position subsample_position; 535 struct dc_transfer_func *out_transfer_func; 536 }; 537 538 /* audio*/ 539 540 union audio_sample_rates { 541 struct sample_rates { 542 uint8_t RATE_32:1; 543 uint8_t RATE_44_1:1; 544 uint8_t RATE_48:1; 545 uint8_t RATE_88_2:1; 546 uint8_t RATE_96:1; 547 uint8_t RATE_176_4:1; 548 uint8_t RATE_192:1; 549 } rate; 550 551 uint8_t all; 552 }; 553 554 struct audio_speaker_flags { 555 uint32_t FL_FR:1; 556 uint32_t LFE:1; 557 uint32_t FC:1; 558 uint32_t RL_RR:1; 559 uint32_t RC:1; 560 uint32_t FLC_FRC:1; 561 uint32_t RLC_RRC:1; 562 uint32_t SUPPORT_AI:1; 563 }; 564 565 struct audio_speaker_info { 566 uint32_t ALLSPEAKERS:7; 567 uint32_t SUPPORT_AI:1; 568 }; 569 570 571 struct audio_info_flags { 572 573 union { 574 575 struct audio_speaker_flags speaker_flags; 576 struct audio_speaker_info info; 577 578 uint8_t all; 579 }; 580 }; 581 582 enum audio_format_code { 583 AUDIO_FORMAT_CODE_FIRST = 1, 584 AUDIO_FORMAT_CODE_LINEARPCM = AUDIO_FORMAT_CODE_FIRST, 585 586 AUDIO_FORMAT_CODE_AC3, 587 /*Layers 1 & 2 */ 588 AUDIO_FORMAT_CODE_MPEG1, 589 /*MPEG1 Layer 3 */ 590 AUDIO_FORMAT_CODE_MP3, 591 /*multichannel */ 592 AUDIO_FORMAT_CODE_MPEG2, 593 AUDIO_FORMAT_CODE_AAC, 594 AUDIO_FORMAT_CODE_DTS, 595 AUDIO_FORMAT_CODE_ATRAC, 596 AUDIO_FORMAT_CODE_1BITAUDIO, 597 AUDIO_FORMAT_CODE_DOLBYDIGITALPLUS, 598 AUDIO_FORMAT_CODE_DTS_HD, 599 AUDIO_FORMAT_CODE_MAT_MLP, 600 AUDIO_FORMAT_CODE_DST, 601 AUDIO_FORMAT_CODE_WMAPRO, 602 AUDIO_FORMAT_CODE_LAST, 603 AUDIO_FORMAT_CODE_COUNT = 604 AUDIO_FORMAT_CODE_LAST - AUDIO_FORMAT_CODE_FIRST 605 }; 606 607 struct audio_mode { 608 /* ucData[0] [6:3] */ 609 enum audio_format_code format_code; 610 /* ucData[0] [2:0] */ 611 uint8_t channel_count; 612 /* ucData[1] */ 613 union audio_sample_rates sample_rates; 614 union { 615 /* for LPCM */ 616 uint8_t sample_size; 617 /* for Audio Formats 2-8 (Max bit rate divided by 8 kHz) */ 618 uint8_t max_bit_rate; 619 /* for Audio Formats 9-15 */ 620 uint8_t vendor_specific; 621 }; 622 }; 623 624 struct audio_info { 625 struct audio_info_flags flags; 626 uint32_t video_latency; 627 uint32_t audio_latency; 628 uint32_t display_index; 629 uint8_t display_name[AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS]; 630 uint32_t manufacture_id; 631 uint32_t product_id; 632 /* PortID used for ContainerID when defined */ 633 uint32_t port_id[2]; 634 uint32_t mode_count; 635 /* this field must be last in this struct */ 636 struct audio_mode modes[DC_MAX_AUDIO_DESC_COUNT]; 637 }; 638 struct audio_check { 639 unsigned int audio_packet_type; 640 unsigned int max_audiosample_rate; 641 unsigned int acat; 642 }; 643 enum dc_infoframe_type { 644 DC_HDMI_INFOFRAME_TYPE_VENDOR = 0x81, 645 DC_HDMI_INFOFRAME_TYPE_AVI = 0x82, 646 DC_HDMI_INFOFRAME_TYPE_SPD = 0x83, 647 DC_HDMI_INFOFRAME_TYPE_AUDIO = 0x84, 648 DC_DP_INFOFRAME_TYPE_PPS = 0x10, 649 }; 650 651 struct dc_info_packet { 652 bool valid; 653 uint8_t hb0; 654 uint8_t hb1; 655 uint8_t hb2; 656 uint8_t hb3; 657 uint8_t sb[32]; 658 }; 659 660 struct dc_info_packet_128 { 661 bool valid; 662 uint8_t hb0; 663 uint8_t hb1; 664 uint8_t hb2; 665 uint8_t hb3; 666 uint8_t sb[128]; 667 }; 668 669 #define DC_PLANE_UPDATE_TIMES_MAX 10 670 671 struct dc_plane_flip_time { 672 unsigned int time_elapsed_in_us[DC_PLANE_UPDATE_TIMES_MAX]; 673 unsigned int index; 674 unsigned int prev_update_time_in_us; 675 }; 676 677 struct psr_config { 678 unsigned char psr_version; 679 unsigned int psr_rfb_setup_time; 680 bool psr_exit_link_training_required; 681 bool psr_frame_capture_indication_req; 682 unsigned int psr_sdp_transmit_line_num_deadline; 683 bool allow_smu_optimizations; 684 }; 685 686 union dmcu_psr_level { 687 struct { 688 unsigned int SKIP_CRC:1; 689 unsigned int SKIP_DP_VID_STREAM_DISABLE:1; 690 unsigned int SKIP_PHY_POWER_DOWN:1; 691 unsigned int SKIP_AUX_ACK_CHECK:1; 692 unsigned int SKIP_CRTC_DISABLE:1; 693 unsigned int SKIP_AUX_RFB_CAPTURE_CHECK:1; 694 unsigned int SKIP_SMU_NOTIFICATION:1; 695 unsigned int SKIP_AUTO_STATE_ADVANCE:1; 696 unsigned int DISABLE_PSR_ENTRY_ABORT:1; 697 unsigned int SKIP_SINGLE_OTG_DISABLE:1; 698 unsigned int RESERVED:22; 699 } bits; 700 unsigned int u32all; 701 }; 702 703 enum physical_phy_id { 704 PHYLD_0, 705 PHYLD_1, 706 PHYLD_2, 707 PHYLD_3, 708 PHYLD_4, 709 PHYLD_5, 710 PHYLD_6, 711 PHYLD_7, 712 PHYLD_8, 713 PHYLD_9, 714 PHYLD_COUNT, 715 PHYLD_UNKNOWN = (-1L) 716 }; 717 718 enum phy_type { 719 PHY_TYPE_UNKNOWN = 1, 720 PHY_TYPE_PCIE_PHY = 2, 721 PHY_TYPE_UNIPHY = 3, 722 }; 723 724 struct psr_context { 725 /* ddc line */ 726 enum channel_id channel; 727 /* Transmitter id */ 728 enum transmitter transmitterId; 729 /* Engine Id is used for Dig Be source select */ 730 enum engine_id engineId; 731 /* Controller Id used for Dig Fe source select */ 732 enum controller_id controllerId; 733 /* Pcie or Uniphy */ 734 enum phy_type phyType; 735 /* Physical PHY Id used by SMU interpretation */ 736 enum physical_phy_id smuPhyId; 737 /* Vertical total pixels from crtc timing. 738 * This is used for static screen detection. 739 * ie. If we want to detect half a frame, 740 * we use this to determine the hyst lines. 741 */ 742 unsigned int crtcTimingVerticalTotal; 743 /* PSR supported from panel capabilities and 744 * current display configuration 745 */ 746 bool psrSupportedDisplayConfig; 747 /* Whether fast link training is supported by the panel */ 748 bool psrExitLinkTrainingRequired; 749 /* If RFB setup time is greater than the total VBLANK time, 750 * it is not possible for the sink to capture the video frame 751 * in the same frame the SDP is sent. In this case, 752 * the frame capture indication bit should be set and an extra 753 * static frame should be transmitted to the sink. 754 */ 755 bool psrFrameCaptureIndicationReq; 756 /* Set the last possible line SDP may be transmitted without violating 757 * the RFB setup time or entering the active video frame. 758 */ 759 unsigned int sdpTransmitLineNumDeadline; 760 /* The VSync rate in Hz used to calculate the 761 * step size for smooth brightness feature 762 */ 763 unsigned int vsync_rate_hz; 764 unsigned int skipPsrWaitForPllLock; 765 unsigned int numberOfControllers; 766 /* Unused, for future use. To indicate that first changed frame from 767 * state3 shouldn't result in psr_inactive, but rather to perform 768 * an automatic single frame rfb_update. 769 */ 770 bool rfb_update_auto_en; 771 /* Number of frame before entering static screen */ 772 unsigned int timehyst_frames; 773 /* Partial frames before entering static screen */ 774 unsigned int hyst_lines; 775 /* # of repeated AUX transaction attempts to make before 776 * indicating failure to the driver 777 */ 778 unsigned int aux_repeats; 779 /* Controls hw blocks to power down during PSR active state */ 780 union dmcu_psr_level psr_level; 781 /* Controls additional delay after remote frame capture before 782 * continuing powerd own 783 */ 784 unsigned int frame_delay; 785 bool allow_smu_optimizations; 786 }; 787 788 struct colorspace_transform { 789 struct fixed31_32 matrix[12]; 790 bool enable_remap; 791 }; 792 793 enum i2c_mot_mode { 794 I2C_MOT_UNDEF, 795 I2C_MOT_TRUE, 796 I2C_MOT_FALSE 797 }; 798 799 struct AsicStateEx { 800 unsigned int memoryClock; 801 unsigned int displayClock; 802 unsigned int engineClock; 803 unsigned int maxSupportedDppClock; 804 unsigned int dppClock; 805 unsigned int socClock; 806 unsigned int dcfClockDeepSleep; 807 unsigned int fClock; 808 unsigned int phyClock; 809 }; 810 811 812 enum dc_clock_type { 813 DC_CLOCK_TYPE_DISPCLK = 0, 814 DC_CLOCK_TYPE_DPPCLK = 1, 815 }; 816 817 struct dc_clock_config { 818 uint32_t max_clock_khz; 819 uint32_t min_clock_khz; 820 uint32_t bw_requirequired_clock_khz; 821 uint32_t current_clock_khz;/*current clock in use*/ 822 }; 823 824 /* DSC DPCD capabilities */ 825 union dsc_slice_caps1 { 826 struct { 827 uint8_t NUM_SLICES_1 : 1; 828 uint8_t NUM_SLICES_2 : 1; 829 uint8_t RESERVED : 1; 830 uint8_t NUM_SLICES_4 : 1; 831 uint8_t NUM_SLICES_6 : 1; 832 uint8_t NUM_SLICES_8 : 1; 833 uint8_t NUM_SLICES_10 : 1; 834 uint8_t NUM_SLICES_12 : 1; 835 } bits; 836 uint8_t raw; 837 }; 838 839 union dsc_slice_caps2 { 840 struct { 841 uint8_t NUM_SLICES_16 : 1; 842 uint8_t NUM_SLICES_20 : 1; 843 uint8_t NUM_SLICES_24 : 1; 844 uint8_t RESERVED : 5; 845 } bits; 846 uint8_t raw; 847 }; 848 849 union dsc_color_formats { 850 struct { 851 uint8_t RGB : 1; 852 uint8_t YCBCR_444 : 1; 853 uint8_t YCBCR_SIMPLE_422 : 1; 854 uint8_t YCBCR_NATIVE_422 : 1; 855 uint8_t YCBCR_NATIVE_420 : 1; 856 uint8_t RESERVED : 3; 857 } bits; 858 uint8_t raw; 859 }; 860 861 union dsc_color_depth { 862 struct { 863 uint8_t RESERVED1 : 1; 864 uint8_t COLOR_DEPTH_8_BPC : 1; 865 uint8_t COLOR_DEPTH_10_BPC : 1; 866 uint8_t COLOR_DEPTH_12_BPC : 1; 867 uint8_t RESERVED2 : 3; 868 } bits; 869 uint8_t raw; 870 }; 871 872 struct dsc_dec_dpcd_caps { 873 bool is_dsc_supported; 874 uint8_t dsc_version; 875 int32_t rc_buffer_size; /* DSC RC buffer block size in bytes */ 876 union dsc_slice_caps1 slice_caps1; 877 union dsc_slice_caps2 slice_caps2; 878 int32_t lb_bit_depth; 879 bool is_block_pred_supported; 880 int32_t edp_max_bits_per_pixel; /* Valid only in eDP */ 881 union dsc_color_formats color_formats; 882 union dsc_color_depth color_depth; 883 int32_t throughput_mode_0_mps; /* In MPs */ 884 int32_t throughput_mode_1_mps; /* In MPs */ 885 int32_t max_slice_width; 886 uint32_t bpp_increment_div; /* bpp increment divisor, e.g. if 16, it's 1/16th of a bit */ 887 888 /* Extended DSC caps */ 889 uint32_t branch_overall_throughput_0_mps; /* In MPs */ 890 uint32_t branch_overall_throughput_1_mps; /* In MPs */ 891 uint32_t branch_max_line_width; 892 }; 893 894 struct dc_golden_table { 895 uint16_t dc_golden_table_ver; 896 uint32_t aux_dphy_rx_control0_val; 897 uint32_t aux_dphy_tx_control_val; 898 uint32_t aux_dphy_rx_control1_val; 899 uint32_t dc_gpio_aux_ctrl_0_val; 900 uint32_t dc_gpio_aux_ctrl_1_val; 901 uint32_t dc_gpio_aux_ctrl_2_val; 902 uint32_t dc_gpio_aux_ctrl_3_val; 903 uint32_t dc_gpio_aux_ctrl_4_val; 904 uint32_t dc_gpio_aux_ctrl_5_val; 905 }; 906 907 908 #if defined(CONFIG_DRM_AMD_DC_DCN3_0) 909 enum dc_gpu_mem_alloc_type { 910 DC_MEM_ALLOC_TYPE_GART, 911 DC_MEM_ALLOC_TYPE_FRAME_BUFFER, 912 DC_MEM_ALLOC_TYPE_INVISIBLE_FRAME_BUFFER, 913 DC_MEM_ALLOC_TYPE_AGP 914 }; 915 916 #endif 917 enum dc_psr_version { 918 DC_PSR_VERSION_1 = 0, 919 DC_PSR_VERSION_UNSUPPORTED = 0xFFFFFFFF, 920 }; 921 922 #endif /* DC_TYPES_H_ */ 923
